In this paper, a novel wearable electrocardiograph (ECG) monitoring system is presented. Unlike most of the existing holter monitors that are composed of conventional electrodes and multiple cables, the ECG monitoring system proposed here consists of intelligent electrodes and one single Active-Cable. A prototype of a wearable ECG monitoring system is developed and implemented on Xilinx FPGAs. The experimental results show that a reliable performance with high-quality ECG data can be achieved using this novel ECG monitoring system.

In this paper, a reconfigurable, low-power Application Specific Integrated Circuit (ASIC) that extracts and transmits electrocardiograph (ECG) signals is presented. An intelligent electrode is introduced which consists of the proposed ASIC and a micro spike array, permitting onsite ECG signal acquisition, processing and transmission. Fabricated in a standard 0.18 mum CMOS process, the ASIC consumes 78 muW with 1.0 V core voltage at 6 MHz operating frequency and only occupies 2.25 mm2. The tiny silicon size makes it possible and suitable to embed the proposed ASIC into an intelligent electrode, and the low power consumption makes it feasible for long term continuous ECG monitoring.

This paper presents a fully integrated application specific integrated circuit (ASIC) sensor for the recording of multiple bio-electric signals. It consists of an analog front-end circuit with tunable bandwidth and programmable gain, a 6-input 8-bit successive approximation register analog to digital converter (SAR ADC), and a reconfigurable digital core. The ASIC is fabricated in a 0.18-μm 1P6M CMOS technology, occupies an area of 1.5 × 3.0 mm ², and totally consumes a current of 16.7 μA from a 1.2 V supply. Incorporated with the ASIC, an Intelligent Electrode can be dynamically configured for on-site measurement of different bio-signals. A 2-wire data transmission protocol is also integrated on chip. It enables the serial connection over a group of Intelligent Electrodes, thus minimizes the number of connecting cables. A wearable healthcare system is built upon a printed Active Cable and a scalable number of Intelligent Electrodes. The system allows synchronous processing of maximum 14-channel bio-signals. The ASIC performance has been successfully verified in in-vivo bio-electric recording experiments.

This paper describes a digital CMOS Application Specific Integrated Circuit (ASIC) solution with the complete data acquisition and transmission for the use in a wearable electrocardiography (ECG) monitoring system. The main particularity of this system is related to the proposed reconfigurable microchip architecture for an intelligent electrode. The chip area is 2.3 mm(2) in a standard 0.18 mu m CMOS technology. The chip is operating at 24 MHz system clock with 3.3 V power supply for I/O cells and 1.8 V for the core circuit respectively. The estimated dynamic power dissipation is only 857 mu W. The post-layout simulation results show that the microchip embedded inside an intelligent electrode features ultra low power consumption and is quite feasible for a hand-held Personal Health Assistant (PHA) which uses a battery as energy source.

A personal medical device supporting continuous biosignals monitoring is presented. The novelty of this paper is to provide an intelligent electrode suitable for long-term ECG monitoring. The proposed intelligent electrode is composed of an ASIC chip and a micro pikes array established on a gauze plaster substrate. By comparing the signal quality, the patient's comfort and convenience, the proposed intelligent electrode could be an alternative to the traditional adhesive electrode. A prototype for the intelligent electrode is built up based on programmable FPAA and FPGA chips.

This paper presents a wearable biopatch prototype for body surface potential measurement. It combines three key technologies, including mixed-signal system on chip (SoC) technology, inkjet printing technology, and anisotropic conductive adhesive (ACA) bonding technology. An integral part of the biopatch is a low-power low-noise SoC. The SoC contains a tunable analog front end, a successive approximation register analog-to-digital converter, and a reconfigurable digital controller. The electrodes, interconnections, and interposer are implemented by inkjet-printing the silver ink precisely on a flexible substrate. The reliability of printed traces is evaluated by static bending tests. ACA is used to attach the SoC to the printed structures and form the flexible hybrid system. The biopatch prototype is light and thin with a physical size of 16 cm x 16 cm. Measurement results show that low-noise concurrent electrocardiogram signals from eight chest points have been successfully recorded using the implemented biopatch.

Facial expressions are among behavioral signs of pain that can be employed as an entry point to develop an automatic human pain assessment tool. Such a tool can be an alternative to the self-report method and particularly serve patients who are unable to self-report like patients in the intensive care unit and minors. In this paper, a wearable device with a biosensing facial mask is proposed to monitor pain intensity of a patient by utilizing facial surface electromyogram (sEMG). The wearable device works as a wireless sensor node and is integrated into an Internet of Things (IoT) system for remote pain monitoring. In the sensor node, up to eight channels of sEMG can be each sampled at 1000 Hz, to cover its full frequency range, and transmitted to the cloud server via the gateway in real time. In addition, both low energy consumption and wearing comfort are considered throughout the wearable device design for long-term monitoring. To remotely illustrate real-time pain data to caregivers, a mobile web application is developed for real-time streaming of high-volume sEMG data, digital signal processing, interpreting, and visualization. The cloud platform in the system acts as a bridge between the sensor node and web browser, managing wireless communication between the server and the web application. In summary, this study proposes a scalable IoT system for real-time biopotential monitoring and a wearable solution for automatic pain assessment via facial expressions.

This paper presents an Intelligent Electrodes and Active Cable based wearable medical system. Within each Intelligent Electrode, an Application Specific Integrated Circuit (ASIC) is integrated which includes a gain-bandwidth selectable analog front-end circuit, an 8-bit SAR ADC and a digital controller. The key of the ASIC is the analog front-end circuit with tunable gain and bandwidth which can be configured for Electrocardiogram (ECG), Electroencephalogram (EEG) or Electromyogram (EMG) measurement. Common mode interference is effectively rejected due to the circuit’s high Common Mode Rejection Ratio (CMRR), which is higher than 135 dB up to 100 Hz and better than 110dB up to 1 kHz. Since a dedicated data transmission protocol is implemented on chip, the Intelligent Electrodes can establish a self-organized network and perform synchronous measurements for multiple bio-signals.

This paper presents the prototype implementation of a Bio-Patch using fully integrated low-power System-on-Chip (SoC) sensor and paper-based inkjet printing technology. The SoC sensor is featured with programmable gain and bandwidth to accommodate a variety of bio-signals. It is fabricated in a 0.18-µm standard CMOS technology, with a total power consumption of 20 µW from a 1.2 V supply. Both the electrodes and interconnections are implemented by printing conductive nano-particle inks on a flexible photo paper substrate using inkjet printing technology. A Bio-Patch prototype is developed by integrating the SoC sensor, a soft battery, printed electrodes and interconnections on a photo paper substrate. The Bio-Patch can work alone or operate along with other patches to establish a wired network for synchronous multiple-channel bio-signals recording. The measurement results show that electrocardiogram and electromyogram are successfully measured in in-vivo tests using the implemented Bio-Patch prototype.

Network-on-Chip (NoC) is a promising architecturein the many-core on-chip systems. A hierarchical agentbased NoC architecture is proposed which enables the NoCto autonomously adjust itself, and provide maximum powerefficiency, fault/variation tolerance and system flexibility. Agentsare software or hardware components which monitor and controlthe system at different granularity. Via the joint efforts andinteractions of agents at all levels of the architecture, systemoptimization can be achieved at the runtime. Agent hierarchy,mapping of agents on regular NoC platforms and the functionpartition among the agents are elaborately discussed.Runtime power management with various Dynamic Voltageand Frequency Scaling (DVFS) techniques is analyzed on thehierarchical agent based NoC platform. Conventional powermonitoring techniques can be flexibly incorporated into the functionsof specific levels of agents. Network condition is observed bythe agents at the runtime, and the power supplies are adjusted atdifferent granularity accordingly. This paper describes the systemarchitectures of two adaptive schemes, with efficient and feasiblealgorithms presented. Quantitative experiments demonstrate thatthey achieve superior power efficiency comparing with the basicarchitecture without any runtime configuration, while different tradeoffs are applied dependent on the monitoring granularity.

Hierarchical Agent Architecture is proposed to provideonline monitoring services to NoC-based systems. Basedon circuit conditions traced at the run-time, system settingsare monitored adaptively by agents at each architectural level.This monitoring approach partitions various online diagnosticand management services onto hierarchical implementation levelsso as to provide scalability and variability for large-scale NoCdesign. This paper explains the monitoring interaction betweenagent levels, and focuses on system optimization alternativeshandled by different agent levels. It further quantitatively analyzesthe feasibility and design alternatives in monitoring communicationinterconnection upon regular tile-based NoC layout.Though still under intensive research, the proposed architectureis endowed with promising potential for highly-integrated NoCdesign.

As the size of NoCs increases, power consumption and fault/variation tolerance have become two of the most crucial problems for system designers. To address these problems, we propose a NoC architecture based on a hierarchy of monitoring agents. By tracing the circuit properties at run time, the agents at different architectural levels are able to monitor and control over the whole NoC platform. This monitoring approach partitions various online diagnostic and management services onto hierarchical implementation levels so as to provide scalability and variability for large-scale NoC design. This paper explains the monitoring interaction between agent levels, and focuses on system optimization alternatives handled by different agent levels. It further quantitatively analyzes the feasibility and design alternatives in monitoring communication interconnection upon regular tile-based NoC layout.

A feasible and scalable per-core DVFS architecture for on-chip network is presented. The supplies are dynamically adjusted at a very fine granularity based on the local traffic status. The adoption of multiple voltage supply networks and power selecting transistors provides the architecture with scalability and feasibility superior to existing similar techniques. With high-level simulation using 65nm power model obtained from widely-acknowledged tools, the effectiveness of the technique is demonstrated with quantitative analysis of energy overhead and latency penalty. Under various traffic patterns, the average flit energy is reduced considerably, ranging from 45% to 60%, with moderately increased but stable transmission latency.

Rectangular mesh and torus are the mostly used topologies in network-on-chip (NoC) based systems. In this paper, we quantitatively illustrate that the honeycomb topology is an advantageous design alternative in terms of network cost which is one of the most important parameters that reflects both network performance and implementation cost. Comparing with the rectangular mesh and torus, honeycomb mesh and torus topologies lead to 40% decrease of the network cost. Then we explore the NoC related topological properties of both honeycomb mesh and torus topologies. By transforming the honeycomb topologies into rectangular brick shapes, we demonstrate that the honeycomb topologies are feasible to be implemented with rectangular devices. We also propose a 3D honeycomb topology since 3D IC has become an emerging and promising technique. Another contribution of this paper is the proposal of deadlock free routing algorithms. Based on either the concept of turn model or the logical network, deadlock free routing for all the discussed honeycomb topologies can be achieved.

Network-on-Chip (NoC) has been widely accepted as one of the most promising on-chip communication architectures for many-core Systems-on-Chip (SoC). With billions of transistors integrated on a single chip, inter-component communication becomes more and more complicated and power hungry. By leveraging the existing technologies of computer networks, NoC enables the on-chip communication to be simpler and more predictable. With the unceasing increase of the number of on-chip components, issues such as communication delay, system throughput, power consumption and large die area start to emerge in traditional two dimensional (2D) integrated circuits (ICs). During the recent years, more attentions than ever have been focused on three dimensional (3D) ICs in both industry and academia. However, 3D ICs are known to have higher cost in several aspects, including heat dissipation, yield, testing, etc., than their 2D counterparts. In this paper, we propose a method based on the economic term of change function to analyze the profitability of using 3D rather than 2D NoCs. We compare the benefits and costs between 2D and 3D NoCs and judgments are made based on the quantized results of these comparisons.

Rectangular Mesh is the most commonly used topology in the field of Network-on-Chip (NoC) due to its high regularity, symmetry and scalability. In this paper, we examine Honeycomb topology as another candidate for NoC architectures. Based on the simulations of Mesh and Honeycomb routers and network, we compare these two topologies in terms of power consumption, area cost and communication delay. Results show that Honeycomb topology outperforms Mesh by at least 25.9%, 54.2% and 30.0% in these three aspects.

Emerging technologies such as invasive electronics andnano-scale Network-on-Chip systems frequently requireultra-low power and fault tolerance. Implementing thiskind of systems requires the use of a robust monitoringstructure and autonomous self-adjustment. In this paperdifferent distributed system monitoring agentarchitectures are analyzed. The monitored informationcan be used to determine faulty components and to adjustsystem operation points towards minimal energy.

A compact, robust, chipless radio frequency identification (RFID) tag is proposed. Resonant elements patterned in a concentric fashion encode data in the spectral domain employing frequency shift encoding. The proposed tag encodes 28.25 data bits over a miniscule physical footprint of 25 x 25 mm(2). The formulated scheme is demonstrated to be viable for encoding of temporal variables. The electromagnetic performance of the presented design is investigated for different laminates: Rogers RT/duroid (R) 5880 and Taconic TLX-0. Multiple tag prototypes employing a variety of substrates are realized and evaluated for in-laboratory performance. The proposed design is compared with existing work reported in literature. Code density of 4.52 bits/cm(2) has been successfully achieved. The tag design operates from 3.07 to 10.6 GHz and is readily realizable on flexible laminates. Smart retail, intelligent packaging, adaptive ticketing, and similar time-related applications can be materialized using the proposed tag.

This paper presents optimizations on guard time and synchronization cycle for Time Division Multiple Access (TDMA) based deterministic Radio Frequency Identification (RFID) system. The TDMA scheme can provide guaranteed latency and high throughput for RFID system that includes fixed number of users (tags) and requests long-message transmission. However, collisions due to accumulated clock drifts of the active RFID tags equipped with independent self-clocked microcontrollers are the major challenge. In this work, we model relations between guard time and synchronization cycle used to tolerate the accumulated clock drift and reduce the probability of collisions for an extended-star RFID system. Constraints of safe guard time and synchronization cycle are proposed to consider energy efficiency and time efficiency. Moreover, optimization on guard time and synchronization cycle are explored in terms of transmission time, tag number, energy efficiency and time efficiency. The simulation results indicate that system with long transmission time (around 1 ms) enjoys higher time and energy efficiency under optimal configuration of guard time and synchronization cycle.

This paper presents a 2.4-GHz radio frequency (RF) and ultra-wide bandwidth (UWB) hybrid real-time locating system (RTLS) for industrial enterprise Internet of Things (IoT). It employs asymmetric wireless link, that is, UWB radio is utilised for accurate positioning up to 10 cm in critical sites, whereas 2.4-GHz RF is used for tag control and coarse positioning in non-critical sites. The specified communication protocol and the adaptive tag synchronisation rate ensure reliable and deterministic access with a scalable system capacity and avoid unpredictable latency and additional energy consumption of retransmissions due to collisions. The tag, consisting of a commercial 2.4-GHz transceiver and a customised application-specific integrated circuit (ASIC) UWB transmitter (Tx), is able to achieve up to 3 years’ battery life at 1600 tags per position update second with 1000 mAh battery in one cluster. The time difference of arrival (TDoA)–based positioning experiment at UWB radio is performed on the designed software-defined radio (SDR) platform.

In this paper, we present an innovative, chipless and fully printable RFID technology. The proposed tag is a fully passive device. Neither power supply nor. chip assembly is required. In our design, information data is embedded in the tag as impedance mismatches along a transmission line. The RFID-reader sends a short time pulse modulated at high frequencies. The reflections due to the impedance mismatches in the tag are transmitted back and detected by the reader. A prototype of the tag has been constructed and tested. The idea has been successfully proven both by simulations and experimental measurements.

The rapid development of wireless sensor network and RFID technologies offers a wide range of novel applications and services. In this paper, we present a two-layered wireless network for warehouses and supermarkets to monitor goods storage and sale, and assist for quality management and market analysis. The hierarchical architecture uses IEEE 802.15.4a impulse ultra-wideband radio (IR-UWB) communication protocol between slave sensor nodes and master sensor nodes, and IEEE 802.11b/g between master sensor nodes and server. The performance of our proposal is evaluated based on the widely used OMNeT++ simulation environment. Simulation results are presented and discussed according to different sampling rates and traffic loads for specific scenarios requirements. © 2009 IEEE.

Optimal total solution for new radio architecture and implementation requires accurate trade-offs for off-chip versus off-chip passives. In this paper, a complete and systematic design methodology for RF blocks in SoP (system-on-package) versus SoC (system-on-chip) is presented. This methodology explores trade-offs between Performance and cost when different on-chip or off-chip passives are used. For a better presentation, the method and design techniques are demonstrated through four multi-band/multi-standard radio design examples with various technologies and different circuit topologies. Our study reveals that, in order to obtain cost benefits in RF-SoPs, small RF chips should be merged as larger chips and the integration density of each RF chip should be high enough. Our study also indicates that in a complex chip like a multi-band radio, moving passives off chip could achieve further cost savings and significant performance improvements. These are general conclusions but, our method offers a detailed analysis which can give quantitative measurements of cost savings and performance improvements in off-chip versus off-chip passives in RF SoP design.

An optimal total solution for radio and mixed-signal system integration needs tradeoffs between different design options. Among various design metrics, cost and performance are probably the two most important factors for design decisions. In this paper, we review and analyze cost-performance tradeoffs of system-on-chip (SOC) versus system-on-Package (SOP) solutions for radio and mixed-signal applications. A new design methodology, which quantitatively predicts performance and cost gains of SOP versus SOC,is presented. The performance model evaluates various mixed-signal isolation techniques between sensitive analog/RF circuits and noisy digital circuits in SOC or SOP. The cost analysis includes new factors such as extra chip area and additional process steps for mixed-signal isolation, seamless integration of "virtual components" or intellectual property (IP) modules, yield and technology compatibility for merging logic, memory and analog/RF circuits on a single chip, and extra costs for moving passives off chip. In addition to these, a complete and systematic analysis method for on-chip versus off-chip passives tradeoffs is presented. The analysis and modeling techniques explore tradeoffs between performance, cost, robustness, and yield when different on-chip or off-chip passives are used. It thus provides a complete picture of quantitative tradeoffs for using on-chip or off-chip passives. The design methodology and analysis techniques are then demonstrated through several design examples in wireless applications. It is clearly shown that for all complex and high performance mixed-signal systems, SOP is a lower cost solution than SOC. Finally,some design guidelines for SOC versus SOP and on-chip versus off-chip are concluded.

Emerging wireless applications for logistics, intelligent home networks, smart dusts, wireless body area networks (WBAN) will need integration and fusion of a diversity of technologies, which may include digital CMOS circuits, analog/RF circuits, sensors/MEMS, embedded software and memories, antenna, displays, polymer, packaging and interconnections, new materials and new integration process. System-on-package (SoP) is considered as a promising solution for the fundamental integration platform for such applications. In this paper, we show how SoP technology can address the integration platform for these applications and how this can be done in a better way than system-on-chip integration. We first demonstrate the integration process of, SoP in liquid-crystal polymer materials. We see that liquid-crystal-polymer is a promising material for low cost RF SoP. We then demonstrate some design examples. The first one is an integrated 5GHz RF receiver front-end in liquid crystal polymer. Due to high quality of passive components in SoP, superior RF performance is found in this module. In the second example, we address several critical design issues for on-chip versus off-chip passives in a multi-band multi-standard radio for beyond 3G applications. We find that not only RF performance can be improved. Cost benefits are also obvious for such a complex radio. Chip-package co-design for smart parasitic absorption is demonstrated through an RF module for an ultrawide band radio in gigabit wireless. Concept of a SoP pacemaker in a WBAN is shown. Finally, we discuss some system level integration issues and we show how a system can be smartly partitioned for SoP so that we can obtain an optimal total solution for low-cost and good-performance wireless integration.

In this paper, we present architecture, circuit implementation and integration issues of embedded smart systems on flexible substrates for future ubiquitous intelligent world. The work is exampled by several concepts of innovative, self-powered, Ion I g-range interconnected radio-frequency identification and sensor networks in warehouse and intelligent goods distribution systems. Two types of RFID concepts are designed for this network. The first one is a self-powered, ultra-low power UWB RFID. A power scavenging system is designed which can draws energy from the 802.11 access point and its surrounding electromagnetic waves. In the second demonstration, we developed a chipless passive RFID based on time-domain reflection principle. As this RFID is chipless and needs only interconnections and antenna, it is potentially fully printable on flexible substrate such as a paper board. Finally, some implementation and experimental results are presented.

Next generation RFID towards ubiquitous wireless sensing and identification requires high network throughput along with long operation range and ultra low energy consumption. In this paper, we review future RFID for ubiquitous intelligence and their technology needs from system to device perspectives. As a promising enabling technology, ultra wideband radio (UWB) and its use in various RFID implementations are investigated. A special focus on an UWB/UHF hybrid passive RFID and sensor system with asymmetric wireless links is studied as an example. Unlike conventional RFID systems relying on backscattering and narrowband radio, UWB is introduced as the uplink for tag to reader communication. It enables a high network throughput (2000 tag/sec), high data bandwidth (100MHz pulse rate), under ultra low power and low cost constraint. The hardware implementation in silicon level is also presented. Finally, applications of the system in intelligent warehouse and fresh food tracker are introduced.

In this paper, we present architecture, circuit implementation and integration issues of an embedded smart system for innovative, long-range interconnected identification/sensor network in warehouse and intelligent goods distribution systems. The network is interconnected via IEEE 802.11 and ultra-wideband (UWB) wireless air interfaces. A self-powered, ultra-low power UWB transceiver with BPSK modulation is designed for transponders and implemented in 0.18um CMOS technology. Low power consumption is achieved by developing innovative circuit and system architectures. Instead of pumping up energy from the Gaussian pluses emitted by the reader, a power converter draws energy from the 802.11 access point and its surrounding electromagnetic waves. Functionality of the transceiver is verified and integration issues for smart labels are investigated on thin foils of liquid crystal polymer.

This paper proposes a new design methodology and new models for power integrity analysis in deep submicron system-on-chip circuit design. The placement plan and interconnect plan are the first design steps, preceding a priori signal and power integrity estimations. The initial power distribution is refined progressively from early mode to final placement and layout. In order to improve accuracy and efficiency in early stage estimates, a multilevel dynamic interconnect model and a fast power distribution model are employed, which consequently result in a drastic reduction of the number of iterations through the design cycle. HSPICE simulations verify the efficiency and the accuracy of the method. Finally, some noise-reduced power distribution techniques such as self-decoupling and area array power/ground pin distribution are discussed, and measurement result for effective power distribution is presented.

As technology scales, power supply noise caused by core logic switching becomes critical. Shorter signal rise edge, high integration density, and necessity of using on-chip decoupling capacitors require that the on-chip power distribution should be modeled as an LRC transmission line network with millions of switching devices. In this paper, we propose a sophisticated power grid model consisting of distributed LRC elements excited by constant voltage sources and switching capacitors. Based on this, fast equations for core switching noise estimations were formulated. Full-chip noise distribution on the power grid with any topology was efficiently and accurately computed. SPICE simulations confirmed its efficiency and accuracy. Experimental results obtained on our benchmark circuits revealed that the proposed technique speeded up simulations by several orders of magnitude compared with SPICE, whereas typical relative error was between 0 +/- 5 %. By integrating a packaging model, the new model predicts accurately the upper boundaries of noise level for power bounce, ground bounce, and differential-mode power noise. Meanwhile, locations of hot spots in the power network are precisely identified. The model is suitable for full-chip rapid simulations for on-chip power distribution design in advanced ultra large scale integration (ULSI) circuits, particularly for early stage analysis, in which global and local optimization such as topology selection, power bus sizing, and on-chip decoupling capacitor placement can be easily conducted.

In this paper, we studied a novel packaging scenario that aims to integrate or eliminate the existing multilevel packaging hierarchies toward single level integration. This new approach is an extension of VLSI technology where standard IC processes were pursued in the whole fabrication sequence. Main benefits include very high performance, ultra high density, mixed-signal integration, and inexpensive. Several key technologies such as chip assembly and planarization were developed. A feasible fabrication procedure for single level integration has been established. Demonstrating modules were presented. Interconnect structures, signal and power distribution, and electrical performance were studied theoretically and experimentally for GHz off-chip operating. Properties of signal propagation and coupling from chip to chip were investigated both in frequency domain and in time domain by simulations and by high frequency measurements. The studies show that the new modules are capable of several Gb/s/pin data rate for off-chip communications. Besides, some design guidelines for best performance are obtained through the work.

The traditional electronic packaging hierarchies present ct bottleneck for increasing system speed and density. A revolutionary rethinking is therefore necessary which aims to integrate or eliminate the current packaging hierarchies towards single level hierarchy integration. In this paper, such a novel packaging scenario is introduced. Its technology concerns and electric performance are studied.

Deep submicron technology is rapidly leading to exceedingly complex, billiontransistor chips. This has resulted in a new circuit paradigm—system-on-chip (SoC). However, deep submicron physics indicates that wires, not transistors, dominate power and performance. Interconnects have been a key design objective in deep submicron SoC. In this chapter, we review interconnect performance as technologies migrate from 0.25μm to 0.035μm feature sizes. Challenges of deep submicron effects and their impacts on advanced chip design are summarized. Basic concepts of signal integrity and various noise sources in deep submicron SoC are illustrated. Finally, interconnect strategies and interconnect-centric design methodologies are generally described; various design techniques for signal and power integrity in deep submicron SoC are discussed.

Unique in focusing on both organic and inorganic materials from a system point of view, this text offers a complete overview of printed electronics integrated with classical silicon electronics. Following an introduction to the topic, the book discusses the materials and processes required for printed electronics, covering conducting, semiconducting and insulating materials, as well as various substrates, such as paper and plastics. Subsequent chapters describe the various building blocks for printed electronics, while the final part describes the resulting novel applications and technologies, including wearable electronics, RFID tags and flexible circuit boards. Suitable for a broad target group, both industrial and academic, ranging from mechanical engineers to ink developers, and from chemists to engineers. 

This paper addresses the issue of UWB signal acquisition in the context of wireless powered UWB RFID systems. In this scenario, the data transmission is based on short packet so as to meet the micro-power budget of autonomous power harvesting. The burst short packet transmission as well as the low duty cycling UWB pulse modulation places a stringent challenge at the UWB receiver for timing acquisition and packet detection. Besides, in a positioning enabled RFID system where variable signal-to-noise ratio (SNR) due to the variable link distance and noise background is unavoidable, conventional packet detection schemes rely on predefined threshold can hardly achieve good performance. In this study, we propose a low complexity method for burst packet detection. It is performed by sensing the preamble signal characteristic instead of the received signal strength, and thus bypassing the necessity of detection threshold. The validity of the proposed approach and its adaptivity to SNR variations is demonstrated by simulation results as well as field test with a UWB software defined radio (SDR) platform.

A compressed sensing (CS) based impulse radio ultra-wideband (IR-UWB) receiver with two-path noise-reducing RF front-end architecture is proposed. By adding an identicalinput path (antenna and gain stage) together with a mixer, the noise in the received signal before feeding into the CS sampling block is alleviated comparing with the conventional CS receiver. Moreover, the mixing stage shifts the signal frequency spectrum to the lower band which eases the CS sampling hardware as well as the complexity of back-end signal reconstruction. Simulation results for a ranging system validate that the proposed CS receiver significantly outperforms the conventional one in both additive white Gaussian noise (AWGN) channel and IEEE802.15.4a multi-path channel.

Non-coherent energy detection (ED) IR-UWB receivers exhibit strong advantages in low data rate, low power and low cost applications such as RFID and Wireless Sensor Networks. However, the performance of ED receivers is usually suffered from the noise enhancement due to the large time-bandwidth product. The integration region of the receiver integrator significantly affects the bit error rate (BER) performance. This paper presents a method of synchronization and estimating the optimal integration region (i.e., the starting point and the length of the integration window), which is based on the analysis of received signal energy capture and combined with a time of arrival (TOA) estimation. The proposed scheme is based on the symbol rate sampling and does not require a priori information about the channel delay profile. Besides, it can adapt to various indoor channel environments. The algorithm has a moderate accuracy but a very low complexity and fast synchronization speed. The validity of the proposed approach is demonstrated by numerical results using IEEE 802.15.4a channel models.

Compressed sensing (CS) based impulse radio ultra-wideband (IR-UWB) receiver has attracted much attention in recent years. This paper presents an architectural analysis of the CS-based IR-UWB receiver with focuses on investigating the random noise processes in the CS measurement procedure. We find that different noise sources (sky noise or amplifier noise) and different receiver architectures (parallel or serial) will results in different noise situation (correlated or uncorrelated) in the CS measurement procedure. Bit error rate (BER) simulation for a communication system and time-of-arrival (TOA) estimation for a ranging system in additive white Gaussian noise (AWGN) channel as well as IEEE 802.15.4a CM1 channel are performed. It shows that CS-based signal detection in uncorrelated noise situation outperforms the correlated noise situation. This noise driven architectural analysis can be used as a design guideline for the CS-based IR-UWB receiver regarding different application scenarios.

Compressed sensing (CS) is an emerging technique which enables sub-Nyquist sampling of sparse or compressible signals. The application of CS theory in the impulse radio ultrawideband (IR-UWB) receiver design has recently attracted much attention. This paper provides an exploration of the CS-based IR-UWB receiver from different aspects: front-end hardware architectures, back-end signal processing algorithms as well as application scenarios. And the performance of the CS receiver regarding the number of CS measurement and different CS recovery algorithms is evaluated and compared against the conventional sub-Nyquist sampling receiver based on energy detection (ED) scheme. Moreover, a strategy to improve the CS receiver performance in handling UWB signals with heavy noise and multipath propagation is proposed.

The next generation RFID system for ubiquitous identification and sensing requires both energy and system efficiency. This paper describes an efficient passive RFID system using impulse ultra-wideband radio (IR-UWB), at a 10 m operation range. Unlike conventional passive RFID systems which rely on backscatter and narrowband radio, IR-UWB is introduced as the uplink (communication from a tag to a reader). By utilizing a specialized communication protocol and a novel ALOHA-based anti-collision algorithm, such semi-UWB systems enable a high network throughput (2000 tag/sec) under the low power and low cost constraint. A low power tag design for proof of concept is finally presented.

The next generation RFID system for ubiquitous identification and sensing requires both energy and system efficiency. This paper describes an efficient passive RFID system using impulse ultra-wideband radio (IR-UWB), at a 10m operation range. Unlike conventional passive RFID systems which rely on backscatter and narrowband radio, IR-UWB is introduced as the uplink (communication from a tag to a reader). By utilizing a specialized communication protocol and a novel ALOHA-based anti-collision algorithm, such Semi-UWB architecture enables a high network throughput (2000 tag/sec) under the low power and low cost constraint. A tag design for proof of concept is finally presented.

This paper presents a digital baseband design for passive sensor and identification systems using asymmetric wireless links with ultra wideband (UWB) radio. As opposed to traditional wireless sensor and identification systems using halfduplex communication in narrowband frequency, impulse-LTWB is applied as an uplink in the proposed system. A novel baseband protocol is devised to improve the system efficiency in the multitag environment while maintaining the power constraint. By utilizing adaptive slotted ALOHA anti-collision algorithm, 1000 tags can be processed within 5OOms. The contributions also include the development of a low-power digital baseband processor for passive tags. The simulation is successful and the FPGA prototype is operational. The chip is implemented for ASIC and it Kill be fabricated and tested Kith the front-end in IP6M UMC 0. 18 mu m process.

This paper presents a digital back-end design for energy detection IR-UWB receivers which can be adopted in RFID and wireless sensor applications. A baseband processor is designed on the basis of a novel synchronization and estimation algorithm. It reduces implementation complexity and energy consumption. A programmable timing circuitry with 1.04 ns phase resolution is also devised in this work. The digital back-end is implemented in UMC 90 nm process, with 222 uW power and 140*220 um2 die area.

This paper presents an energy detection Impulse Radio Ultra-Wideband (IR-UWB) receiver for Radio Frequency Identification (RFID) and Wireless Sensor Networks (WSN) applications. An Application-Specific Integrated Circuit (ASIC) consisting of a 3-5 GHz analog front-end, a timing circuit and a high speed baseband controller is implemented in a 90 nm standard CMOS technology. A Field-Programmable Gate Array (FPGA) is employed as a reconfigurable back-end, enabling adaptive baseband algorithms and ranging estimations. The proposed architecture is featured by high flexibility that adopts a wide range of pulse rate (512 kHz-33 MHz), processing gain (0-18 dB), correlation schemes, synchronization algorithms, and modulation schemes (PPM/OOK). The receiver prototype was fabricated and measured. The power consumption of the ASIC is 16.3 mW at 1 V power supply, which promises a minimal energy consumption of 0.5 nJ/bit. The whole link is evaluated together with a UWB RFID tag. Bit error rate (BER) measurement displays a sensitivity of -79 dBm at 10 Mb/s with 10(-3) BER achieved by the proposed receiver, corresponding to an operation distance over 10 meters under the FCC regulation.

Impulse ultra-wideband radios (IR-UWB) show strong advantages in low power and low cost applications such as RFIDs and wireless sensor networks. This paper presents an IR-UWB receiver based on Energy Detection (ED) with on-off keying (OOK) modulation. A novel synchronization and detection algorithm using the energy offset scheme with adaptive threshold detection is suggested, aiming to reduce energy consumption and simplify hardware complexity. Simulation and FPGA implementation reveal that the proposed method can avoid complex and power consuming synchronization blocks, and reduce the preamble length, whereas maintaining the performance in the target level. Hardware integration issues are discussed, implying that the proposed receiver architecture has the possibility to achieve low complexity and low power implementation with several nJs energy per bit, at a data rate of 10Mb/s.