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  • 51.
    Höijer, Magnus
    KTH, Superseded Departments, Electronic Systems Design.
    Spontaneous emission control1998Doctoral thesis, monograph (Other scientific)
  • 52.
    Isoaho, Jouni
    et al.
    Tampere University of Technology, Signal Processing Laboratory.
    Öberg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    High level synthesis in DSP ASIC optimization1994In:  Proc. of 7th IEEE ASIC Conference and Exhibit, 1994, p. 75-78Conference paper (Refereed)
    Abstract [en]

    In this paper Digital Signal Processing (DSP) system optimization with High Level Synthesis (HLS) environment is presented. To optimize a behavioural VHDL description, commercial SYNT and Synopsys synthesis tools are utilized. The optimization results are improved with a simple rule based preallocator. The coefficient optimization is done in Matlab to provide an efficient implementation of power-of-two and multiply-accumulate based FIR filters. The optimization results are presented using practical filter examples

  • 53.
    Isoaho, Jouni
    et al.
    Tampere University of Technology, Signal Processing Laboratory.
    Öberg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    HLS based DSP optimization with ASIC RTL libraries1994In:  , 1994, p. 218-225Conference paper (Refereed)
    Abstract [en]

    In this paper we show how the High Level Synthesis (HLS) tool can efficiently be used for DSP ASIC development. The performance of general HLS tool is improved with simple transformations and code optimizations, and a direct mapping to technology optimized parameterizable ASIC Register Transfer Level (RTL) library. The library mapping contains three phases: a structure recognition, an architecture selection and a parameter optimization. As an optimization framework SYNT, Synopsys and Matlab design environments are integrated. Lsi10k and Xilinx 4000 series are used as target technologies to demonstrate the performance of the approach

  • 54.
    Jantsch, Axel
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Ellervee, Peeter
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Öberg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Hardware/software partitioning and minimizing memory interface traffic1994In: Proceedings of the conference on European design automation 1994, 1994, p. 226-231Conference paper (Refereed)
  • 55.
    Jantsch, Axel
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Ellervee, Peeter
    ֖berg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    A Case Study on Hardware/Software Partitioning1994In: Proceedings of IEEE Workshop on FPGAs for Custom Computing Machines, IEEE conference proceedings, 1994, p. 111-118Conference paper (Refereed)
    Abstract [en]

    We present an analysis of a fully automatic method to accelerate standard software in C or C++ by use of field programmable gate arrays. Traditional compiler techniques are applied to the hardware/software partitioning problem and a compiler is linked to state of the art hardware synthesis tools. Time critical regions are identified by means of profiling and are automatically implemented in user programmable logic with high level and logic synthesis design tools. The underlying architecture is an add-on board with user programmable logic connected to a Spare based workstation via the system bus. We present an analysis and case study of this method. Eight programs are used as test cases and the data collected by applying this method to programs is used to discuss potentials and limitations of this and similar methods. We discuss architectural parameters, programming language properties, and analysis techniques.

  • 56.
    Jantsch, Axel
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Sander, Ingo
    KTH, Superseded Departments, Electronic Systems Design.
    On the Roles of Functions and Objects in System Specification2000In: Proceedings of the International Workshop on Hardware/Software Codesign, 2000Conference paper (Refereed)
  • 57.
    Jantsch, Axel
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Sander, Ingo
    KTH, Superseded Departments, Electronic Systems Design.
    Wu, Wenbiao
    KTH, Superseded Departments, Electronic Systems Design.
    The Usage of Stochastic Processes in Embedded System Specifications2001In: Proceedings of the Ninth International Symposium on Hardware/Software Codesign, 2001Conference paper (Refereed)
  • 58.
    Jantsch, Axel
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Öberg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    Ellervee, Peeter
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    A software oriented approach to hardware-software co-design1994In: International conference on Compiler Construction, 1994, p. 93-102Conference paper (Refereed)
  • 59.
    Jantsch, Axel
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Öberg, Johnny
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Special Issue on Networks on Chip - guest editor’s introduction2004In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 50, no 2-3, p. 61-63Article in journal (Other academic)
  • 60.
    Jonsson, Bengt
    KTH, Superseded Departments, Electronic Systems Design.
    Switched-current circuits: from building blocks to mixed analog-digital systems1998Doctoral thesis, monograph (Other scientific)
  • 61.
    Jonsson, Per
    KTH, Superseded Departments, Electronic Systems Design.
    Investigation of dye molecules in a microcavity: towards single-photon generation2000Licentiate thesis, monograph (Other scientific)
  • 62.
    Josyula, Lalita
    KTH, Superseded Departments, Electronic Systems Design.
    Stability of point defects in silicon induced by high energy low dose ion implantation1997Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    Ion implantation is a key' process for the introduction ofdopants in semiconductor technology. It involves bombarding thesubstrate material with energetic ions. One of the principleside effects of particle irradiation into crsystallinesemiconductor materials, like Si, is the disruption of theoriginal lattice caused by collisions with incident ionscreating atomic displacements. Point defects mediate dopantdiffusion in semiconductors, at temperatures where ordinarythermal diffusion is negligible. They also introduce energylevels into the forbidden gap of semiconductors.

    These energy levels can serve as recombination centres forelectrons and holes. While recombination centres are unwantedin, for example silicon photo detectors, where carrier lossshould be kept at a minimum, they are deliberately introducedin silicon power devices to control their switching propertiesas they are effective 'lifetime killers'. For this defectengineering in silicon, proton irradiation is widely usedbecause of the fact that localised damage regions are createdand the damage profile can be precisely controlled by justadjusting the incident ion energy.

    Implantation induced damage is a function of variousparameters like the energy of the incident ion, mass, dose,dose rate, substrate temperature among others. In this work anattempt has been made to study the effects of variation of theabove mentioned factors on the resultant damage.Very low dosesof ions have been employed and hence, defects formed constitutea very dilute regime of concentration. Deep level transientspectroscopy (DLTS) has been used for sample characterisationafter implantation. The most common defects observed in allroom temperature implanted silicon samples, irrespective ofmass, are the divacancy (V2) and the vacancy-oxygen(VO) centres in n-type,the divacancy (V2) and the carbon-oxygen (CO centres in p-type. Theconcentration of defects increases linearly with increasingdose, provided doses are not very high where these defectsinteract with each other forming higher order complexes. Doserate studies have revealed that the concentration of pointdefects decreases with increasing dose rate and this isatrributed to the fact that the rapidly diffusing siliconself-interstitials (I's) annihilate vacancies created inadjacent ion tracks, due to overlap of cascades, therebyreducing vacancy concentration and thus preventing theformation of vacancy type defects. The dose rate effect is evenmore pronounced for heavy' ion implantation and occurs at lowerdose rates owing to the larger size of an individual collisioncascade and a high density of I's. Implantation at elevatedsubstrate temperatures have indicated a relaxation of thelattice strain created due to ion bombardment and favoured theproduction of unperturbed V2centres as well as VO centres.

    Implantation induced defects like V2and VO centres which involve broken or danglingbonds are easily passivated at room temperature by hydrogen andcopper. If introduced in a controlled fashion, copper andhydrogen can form. electrically active complexes withdefects.

    Annealing studies show that V2and VO centres are less stable in Czochralskigrown (CZ)ion implanted silicon compared to electron irradiatedfloat zone silicon (FZ). This is because of a largeconcentration of impurities in CZ silicon like oxygen andcarbon and highly disordered regions in ion implanted sampleswhich act as effective traps for migrating point defects.

  • 63.
    Juhola, Tarja A.
    KTH, Superseded Departments, Electronic Systems Design.
    High frequency multichip modules: materials, design and fabrication techniques2000Licentiate thesis, comprehensive summary (Other scientific)
  • 64.
    Kaplan, Wlodek
    KTH, Superseded Departments, Electronic Systems Design.
    The use of self-aligned Ti silicide in integrated Si technology1998Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    The performance and cost efficiency of integrated circuits(IC) are constantly improved by a miniaturization of theindividual device dimensions. As a consequence, the materialand electrical properties of conductors and contacts becomecritical, and fabrication technology development meets newchallenges from the continuous reduction of devicedimensions.

    Thin film refractory metal silicides have been widely usedbecause of their great importance for industrial applicationsin very large scale integration (VLSI) complementarymetal-oxide semiconductor (CMOS) circuits. The use of silicidesallows the formation of low resistance source, gate and draincontacts which can significantly reduce the resistance of aCMOS gate and the source/drain series resistance compared tonon-silicided structures, and hence improves speedperformance.

    Most of the silicide applications are realized using aSelf-ALIgned siliCIDE (SALICIDE) process based on titanium(Ti). Titanium silicide (TiSi2) is one of the most attractive materials among therefractory metal silicides due to its relatively hightemperature stability and low reported resistivity. Thesuccessful application of the Ti SALICIDE process has beenreported for most of the IC fabrication technologies. Atsub-micron dimensions the process window for the formation ofTiSi2is very small and rapid thermal processing (RTP)has been developed and successfully used in many applications.For deep sub-micron linewidths a new technique forenhancingTiSi2formation has to be used because the processwindow for ordinary RTP formation of silicide becomes toonarrow.

    The implementation of the Ti SALICIDE technology in astandard Si technology was investigated. The study focused onsilicide formation in different ambient, etch selectivity,bridging and the Ti - SiO2interaction. Moreover, sheet resistance andcontact resistance measurements were made and yield statisticson fabricated devices were studied in order to fullycharacterize the Ti SALICIDE process. A new etch procedure forself-aligned Ti silicide was proposed. Developed technology wassuccessfully applied in the laboratory scale device fabricationprocesses.

    The realization of sub-micron VLSI circuits operating atlower voltages suffers from the high resistance of dopedpolysilicon. Hence the Ti SALICIDE process is still one of themost important technologies to enhance circuit performance.Observed difficulties with the formation of the low resistiveC54 titanium silicide phase on sub-micron polysilicon linesoutlined and inspired further studies. A novel method toenhance TiSi2formation from Mo/Ti bilayer was investigated. Aone step Ti SALICIDE process to form TiSi2from Mo/Ti/TiN was proposed. Based on the recentliterature, novel silicide concepts to maintain fabrication ofshallow junctions under the silicide; e.g. elevatedsource/drain approach or selective deposition of TiSi2are described. Progress in these fields indicatesthat TiSi2is still one of the strongest candidates forapplications in a future deep sub-micron CMOS technology.

    Key words:very large scale integration, VLSI,self-aligned silicide, SALICIDE, titanium silicide, TiSi2, silicidation, bridging, etch selectivity,sub-micron, Mo/Ti bilayer, TiSi2applications.

  • 65.
    Karlin, Tord E.
    KTH, Superseded Departments, Electronic Systems Design.
    Process integration issues for high-performance bipolar technology1997Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    The work in this thesis has been focused on processintegration issues for high-performance bipolar technologyincluding experimental work on self-aligned silicides,ion-implanted andin situdoped polysilicon emitters, strained silicongermanium for heterojunction bipolar transistors and physicalprocess and device simulation.

    Key issues for the self-aligned silicidation of small devicefeatures such as the influence of dopants, silicon morphologyand line width on titanium disilicide formation, phasetransformation and temperature stability, have been addressed.Pre-amorphization and ion beam mixing by arsenic implantationprior to the suicide formation was shown to extend the use oftitanium silicide into the sub-micron line width range, wheretransformation to the low-resistive phase is otherwise impeded.The temperature stability of cobalt disilicide has also beenstudied.

    An epitaxial silicon germanium base was integrated into adeep trench isolated double polysilicon high-frequency bipolarprocess. The integrity of the boron and germanium profiles inthe silicon germanium base was investigated for processrelevant furnace and rapid thermal annealings. It was shownthat the outdiffusion of boron and germanium can besignificantly lowered by the use ofin situdoping of the polysilicon emitter compared tothe conventional ion implantation.

    Physical process and device simulation was utilized as apowerful tool for device design and the development of a shortturn-around time high-frequency bipolar transistor researchprocess. Simulations were used both for prediction andanalysis. Analysis by simulation revealed that the non-linearforward common emitter current gain, observed for the firsttransistors fabricated in the research process, originated froma high interface charge carrier recombination velocity belowthe emitter oxide spacers. Measurements on fabricated devices,with different ratios between the emitter interface area andoxide spacer area, verified the simulation results. It wasshown that passivation with hydrogen could improve thelinearity and peak value of the forward common emitter currentgain as well as the maximum transition frequency.

    The workhas been carried out within the high-frequencybipolar project at the Department of Electronics at KTH.

    Keywords:process integration, bipolar technology,silicon, silicon germanium, titanium silicide, phasetransformation, pre-amorphization,in situdoping, physical process simulation, physicaldevice simulation.

  • 66.
    Keiper, Dietmar
    KTH, Superseded Departments, Electronic Systems Design.
    New and safe MOVPE processes for InP based devices2000Doctoral thesis, comprehensive summary (Other scientific)
  • 67.
    Kerek, Daniel
    KTH, Superseded Departments, Electronic Systems Design.
    Design of a wideband direct sequence spread spectrum radio transceiver ASIC1999Licentiate thesis, monograph (Other scientific)
  • 68.
    Kerek, Daniel
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Maguire Jr., Gerald Q.
    KTH, Superseded Departments, Teleinformatics.
    Reichert, Frank
    KTH, Superseded Departments, Teleinformatics.
    Direct Sequence CDMA Technology and its Application to Future Portable Multimedia Communication Systems1994In: Proceedings of the 1994 IEEE 3rd International Symposium on Spread Spectrum Techniques & Applications. Part 2 (of 2), IEEE , 1994, Vol. 2, p. 445-449Conference paper (Refereed)
    Abstract [en]

    The design of flexible and efficient future mobile communication systems is a major challenge. The Walkstation Project involves researchers from different areas in order to find a solution via a global system approach. An important task is the investigation of new digital, highly integrated radio interfaces with low cost, small size and low power consumption based on direct sequence CDMA. The simplicity of the design of both the analog and digital parts will allow low power operation and small area in an eventual BiCMOS implementation.

  • 69.
    Kerek, Daniel
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Maguire Jr., Gerald Q.
    KTH, Superseded Departments, Teleinformatics.
    Reichert, Frank
    KTH, Superseded Departments, Teleinformatics.
    The Walkstation transceiver design1994In: Proceedings of the 44th IEEE Vehicular Technology Conference'94,, IEEE , 1994, Vol. 1, p. 462-466Conference paper (Refereed)
    Abstract [en]

    The design of flexible and efficient future mobile communication systems is a major challenge. The Walkstation Project involves researchers from different areas in order to find a solution via a global system approach. An important task is the investigation of new digital, highly integrated radio interfaces with low cost, small size and low power consumption based on direct sequence CDMA. The simplicity of the design of both the analog and digital parts will allow low power operation and small area in a eventual BiCMOS implementation.

  • 70. Khan, Mozammel H.
    et al.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Implementation-Independent Macrolibrary for Telecommunication in VHDL1996In: Proceedings of the Baltic Electronics Conference, 1996, p. 291-294Conference paper (Refereed)
  • 71.
    Kumar, Shashi
    et al.
    Indian Institute of Technology.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Ellervee, Peeter
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Kumar, Anshul
    KTH, Superseded Departments, Electronic Systems Design.
    Internal Representation for Specification and Design of Heterogeneous Systems1997In:  , 1997Conference paper (Refereed)
  • 72.
    Kumar, Shashi
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Soininen, Juha-Pekka
    Forsell, Martti
    Millberg, Mikael
    KTH, Superseded Departments, Electronic Systems Design.
    Öberg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    Tiensyrja, Kari
    Hemani, Ahmed
    A network on chip architecture and design methodology2002In: VLSI 2002: IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI - NEW PARADIGMS FOR VLSI SYSTEMS DESIGN, IEEE conference proceedings, 2002, p. 105-112Conference paper (Refereed)
    Abstract [en]

    We propose a packet switched platform for single chip systems which scales well to an arbitrary number of processor like resources. The platform, which we call Network-on-Chip (NOC), includes both the architecture and the design methodology. The NOC architecture is a m x n mesh of switches and resources are placed on the slots formed by the switches. We assume a direct layout of the 2-D mesh of switches and resources providing physical- architectural level design integration. Each switch is connected to one resource and four neighboring switches, and each resource is connected to one switch. A resource can be a processor core, memory, an FPGA, a custom hardware block or any other intellectual property (LP) block, which fits into the available slot and complies with the interface of the NOC. The NOC architecture essentially is the onchip communication infrastructure comprising the physical layer, the data link layer and the network layer of the OSI protocol stack. We define the concept of a region, which occupies an area of any number of resources and switches. This concept allows the NOC to accommodate large resources such as large memory banks, FPGA areas, or special purpose computation resources such as high performance multiprocessors. The NOC design methodology consists of two phases. In the first phase a concrete architecture is derived from the general NOC template. The concrete architecture defines the number of switches and shape of the network, the kind and shape of regions and the number and kind of resources. The second phase maps the application onto the concrete architecture to form a concrete product.

  • 73.
    Lalic, Nenad
    KTH, Superseded Departments, Electronic Systems Design.
    Light emitting devices based on silicon nanostructures2000Doctoral thesis, comprehensive summary (Other scientific)
    Abstract [en]

    Although silicon is the dominant semiconductor today, lightemitting devices are currently based on compound semiconductorsdue to their direct band-gap, which promotes fast radiativerecombination. However, in nanometer-size silicon structures,carrier confinement enhances the radiative recombination,while, at the same time, suppresses diffusion to non-radiativerecombination centra, resulting in a significant increase inlight emission efficiency. Moreover, the band-gap is wideningas the crystal size is reduced (quantum confinement), enablinglight emission in the visible range. In this work, twodifferent approaches to manufacture a light emitting diode(LED) in silicon have been investigated. The first type ofsilicon LED's is based on porous silicon (PSi) and manufacturedby electrochemical etching of a previously formed pn diodestructure. After optimizing the etching process, PSi LED's wereproduced with an external quantum efficiency of ~0.2% underpulsed excitation, more than an order of magnitude higher thanpreviously reported. Tunability of the emission wavelength inthe range 1.6-2eV was demonstrated by varying the etchingparameters. The EL wavelength is determined by the band-gap ofthe nanocrystals, i. e. their size, as evidenced by a lowerthreshold for longer EL wavelengths, due to lower barriers forinjection into larger crystallites. The EL decay after the biaspulse follows a stretched exponential shape, in agreement witha model involving exciton migration in partially interconnectednanocrystals. Under constant bias, the EL and forward currentare decreasing, due to charging, caused by carrier trapping inthe porous network. After the etching the hydrogen passivatedporous silicon surface is being gradually oxidized, resultingin increased barriers, permanent conductivity reduction and ELdegradation. To improve stability, the second LED approach,based on Si nanocrystals embedded in SiO2, was studied. Nanocrystals were formed by theimplantation of Si into thermally grown SiO2and by subsequent annealing at high temperatures(mostly 1100°C). Photoluminescence investigation showedthat luminescence properties are dependent on nanocrystal sizeand similar to those of PSi. However, decay shapes and timeconstants revealed a stronger isolation of the nanocrystalsthan in PSi. For the EL, good current transport properties werenecessary. That required a thin SiO2layer and efficient injection, realized using anin-situ doped poly-Si cap layer. The Si nanocrystal LED's werestable, although the total light intensity was lower than inPSi, as a consequence of a thin active layer.

    Key words: Electroluminescence, photoluminescence, lightemitting diode, porous materials, nanostructured materials,silicon, etching, anodized layers, ion implantation.

  • 74. Lazraq, T.
    et al.
    Svantesson, Bengt
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Modeling of Operation and Maintenance Functions in the ATM Network1995In: Proceedings of ESM 1995, 1995Conference paper (Refereed)
  • 75.
    Lazraq, Tawfiq
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Öberg, Johnny
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    FPGA Basic ATM Traffic Shaper for Event-Building Networks1995In: Annual IEEE International ASIC Conference and Exhibit, 1995, p. 177-180Conference paper (Refereed)
  • 76.
    Lazraq, Tawfiq
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Östman, Fredrik
    Öberg, Johnny
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    ATM Switching System Performance Analysis via Modelling and Simulation1994In: Proceedings of SIMS, 1994, p. 326-332Conference paper (Refereed)
  • 77.
    Li, B. X.
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    A second order multi-bit Sigma Delta modulator with single-bit feedback2004In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 38, no 1, p. 63-72Article in journal (Refereed)
    Abstract [en]

    Multi-bit Sigma Delta modulators suffer from the DAC non-linearity problem and often need complicated Dynamic Element Matching (DEM) circuits. Combining a multi-bit quantizer and a single-bit DAC eliminates the need of DEM circuits, simplifies the design, and reduces the power consumption. Using a digital circuit to compensate the truncation error caused by cutting the multi-bit feedback to single-bit, the structure can achieve the same noise transfer function as a conventional multi-bit modulator. One drawback is that the signal scaling in such a structure lowers the overall resolution. In this paper the influence of signal scaling is analyzed and a design example given. A second order 3-bit modulator is fabricated in 0.35 mum CMOS process, achieving 82 dB dynamic range at OSR 128 and a peak SNDR of 73.1 dB.

  • 78. Li, B. X.
    et al.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Design of semi-uniform quantizers and their application in sigma delta A/D converters2004In: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 41, no 03-feb, p. 253-267Article in journal (Refereed)
    Abstract [en]

    In this paper a new type of non-uniform quantizer, semi-uniform quantizer, is introduced. A k-bit semi-uniform quantizer uses the thresholds defined by a (k+1)-bit uniform quantizer and arranges them in such a way that small-amplitude inputs will be quantized by small quantization steps and large-amplitude inputs by large quantization steps. Therefore the total quantization error power could be reduced and the modulator's dynamic range could be increased by 1-bit. The condition for a semi-uniform quantizer to achieve a better performance than a uniform quantizer is analyzed and verified using a second order 3-bit sigma delta modulator prototype chip, fabricated in 0.35 mum CMOS process. At 32 x oversampling ratio the modulator achieves 81 dB dynamic range and 63.8 dB peak SNDR with 3-bit semi-uniform quantizer. With 3-bit uniform quantizer the dynamic range is 70 dB and the peak SNDR is 54.1 dB.

  • 79.
    Lindvall, Stefan
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Düring, Morgan
    Öberg, Johnny
    A Pointer-based Output Scheduling Algorithm for the ProGram Com­piler2003In: Proceedings of NORCHIP, 2003, p. 191-195Conference paper (Refereed)
  • 80.
    Liu, Jian
    KTH, Superseded Departments, Electronic Systems Design.
    Configuration of a DTM switch2002Independent thesis Advanced level (degree of Master (Two Years)), 20 credits / 30 HE creditsStudent thesis
    Abstract [en]

    DTM, Dynamic synchronous Transfer Mode is a synchronous network protocol based on fast circuit switching. It provides a service supporting multicast, multirate channels with short setup delay. The time-division-multiplexing scheme implemented in DTM makes it possible to allocate bandwidth to a channel dynamically. DTM is designed for real-time applications but it supports bursty, asynchronous applications as well. Furthermore, non-blocking, time division switches with fully connected input ports and output ports exist today. This document presents a switch architecture designed for DTM networks. The switch is a time-space-time synchronous switch. Whole frames of data are mapped from input buffers to output buffers according to slot map tables. Thus, the slot map tables function as time slot interchangers in traditional time-space-time switches. The required length of the slot map tables for a frame with a given number of time slots is investigated. Some scheduling algorithms for the slot map tables are examined. Unicast and multicast connections are studied separately.

  • 81.
    Liu, Jian
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    A circuit-switched network architecture for network-on-chip2004In: IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, NEW YORK: IEEE , 2004, p. 55-58Conference paper (Refereed)
    Abstract [en]

    This paper presents a circuit-switched network architecture for Network-on-Chip. It uses time-division-multiplexing (TDM) scheme to realize the circuits. The global routing (slot assignment) is done centrally, while the slot mapping is done locally by the switches. The switches support multicast operation, which enables multicast traffic. Furthermore, the delay in the network is predictable before a circuit is established and in-order data delivery is guaranteed.

  • 82.
    Liu, Jian
    et al.
    KTH, Superseded Departments, Electronic Systems Design. KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Global routing for multicast-supporting TDM network-on-chip2004In: 2004 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS / [ed] Nurmi, J; Takala, J; Hamalainen, TD, NEW YORK: IEEE , 2004, p. 17-20Conference paper (Refereed)
    Abstract [en]

    This paper presents a circuit-switched network architecture for Network-on-Chip. It uses the time-division-multiplexing (TDM) scheme to realize the circuits. The global routing (slot assignment at each switch) is done centrally, while the slot mapping is done locally by the switches. The switches support multicast operation, which enables multicast traffic. Furthermore, the delay in the network is predictable before a circuit is established and in-order data delivery is guaranteed

  • 83.
    Liu, Jian
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Interconnect intellectual property for Network-on-Chip (NoC)2004In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 50, no 2-3, p. 65-79Article in journal (Refereed)
    Abstract [en]

    As technology scales down, the interconnect for on-chip global communication becomes the delay bottleneck. In order to provide well-controlled global wire delay and efficient global communication, a Network-on-Chip (NoC) architecture was proposed by different authors [Route packets, not wires: on-chip interconnection networks, in: Design Automation Conference, 2001, Proceedings, p. 684; Network on chip: an architecture for billion transistor era, in: Proceeding of the IEEE NorChip Conference, November 2000; Network on chip, in: Proceedings of the Conference Radio vetenskap och Kommunication, Stockholm, June 2002]. NoC uses Interconnect Intellectual Property (IIP) to connect different resources. Within an IIP, the switch has the central function. Depending on the network core of the NoC, the switch will have different architectures and implementations. This paper first briefly introduces the concept of NoC. It then studies NoC from an interconnect point of view and makes projections on future NoC parameters. At last, the IIP and its components are described, the switch is studied in more detail and a time-space-time (TST) switch designed for a circuit switched time-division multiplexing (TDM) NoC is proposed. This switch supports multicast traffic and is implemented with random access memory at the input and output. The input and output are then connected by a fully connected interconnect network.

  • 84.
    Lu, Zhonghai
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Flit admission in on-chip wormhole-switched networks with virtual channels2004In: 2004 INTERNATIONAL SYMPOSIUM ON SYSTEM-ON-CHIP, PROCEEDINGS, IEEE conference proceedings, 2004, p. 21-24Conference paper (Refereed)
    Abstract [en]

    Flit-admission solutions for wormhole switches must minimize the complexity of the switches in order to achieve cheap implementations. We propose to couple flit-admission buffers with physical channels so that flits from a flit-admission buffer are dedicated to a physical channel. By the coupling strategy, for input-queuing wormhole lane switches, the complexity of the crossbars can be simplified from 2p x p to (p + 1) x p, where p is the number of physical channels; for output-queuing wormhole lane switches, the additional complexity is also minimal. We evaluate the flit-admission solutions derived from the coupling with uniformly distributed random traffic in a 2D mesh network. Experimental results show that these solutions exhibit good performance in terms of latency and throughput.

  • 85.
    Lu, Zhonghai
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Flit ejection in on-chip wormhole-switched networks with virtual channels2004In: 22ND NORCHIP CONFERENCE, PROCEEDINGS, IEEE conference proceedings, 2004, p. 273-276Conference paper (Refereed)
    Abstract [en]

    An ideal it-ejection model is typically assumed in the literature for wormhole switches with virtual channels. With such a model, its are ejected from the network immediately upon reaching their destinations. This achieves optimal performance but is very costly. The required number of sink queues of a switch for absorbing its is p center dot v, where p is the number of physical channels (PCs) of the switch; v the number of lanes per PC To achieve cheap silicon implementations, it-ejection solutions must be cost-effective. We present a novel it-ejection model and a variant of it where the required number of sink queues of a switch is p, i.e., independent of v. We evaluate the it-ejection models with uniformly distributed random traf c in a 2D mesh network. Experimental results show that they exhibit good performance in latency and throughput.

  • 86.
    Lu, Zhonghai
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Network-on-Chip Assembler Language2003Report (Other academic)
  • 87.
    Lu, Zhonghai
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Refinement for Communication-Based Design2003In: Swedish System-on-Chip Conference (SSoCC’03), 2003Conference paper (Other academic)
  • 88.
    Lu, Zhonghai
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Sander, Ingo
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    A case study of hardware and software synthesis in ForSyDe2002In: Proceedings of the 15th International Symposium on System Synthesis, 2002Conference paper (Refereed)
  • 89. Ma, Yutai
    et al.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    A Flexible Register Access Control for Programmable Protocol Processors2001In:  , 2001Conference paper (Refereed)
  • 90. Ma, Yutai
    et al.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    A Group of Subword Instructions and Design Issues for Network Processing RISC Cores2003In:  , 2003Conference paper (Refereed)
  • 91. Ma, Yutai
    et al.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    A Programmable Protocol Processor Architecture for High Speed Internet Protocol Processing2000In:  , 2000Conference paper (Refereed)
  • 92. Ma, Yutai
    et al.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    A Simple Transition Control for FSM Programmable Protocol Processors2000In:  , 2000Conference paper (Refereed)
  • 93. Ma, Yutai
    et al.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Load/Store Unit Design of a Programmable Internet Protocol Processor2002In:  , 2002Conference paper (Refereed)
  • 94. Ma, Yutai
    et al.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Two special register addressing modes for internet protocol processing2002In:  , 2002Conference paper (Refereed)
  • 95.
    Maguire Jr., Gerald Q.
    et al.
    KTH, Superseded Departments, Teleinformatics.
    Ottersten, Björn
    KTH, Superseded Departments, Signals, Sensors and Systems.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Zander, Jens
    KTH, Superseded Departments, Teleinformatics.
    Future Wireless Computing & Communications1994In: NRS-Seminarium Radiokommunikationsnät Konferensdokumentation, 1994, p. 57-61Conference paper (Refereed)
    Abstract [en]

    With the advent of mass produced cellular telephony, wireless communication is about to revolutionize the way we think about information systems. In the near future it is generally believed that entertainment, personal computing and communication industries will merge and that the organizations and consumers will demand their services `on the move´. This paper will address how new technologies will enable future mobile distributed computing and communication systems and discuss what their impact may be on the behavior of users and their organizations. We will focus on some important trends in future mobile[21] and wearable/implantable computing[10]. Some of the limiting factors and key research and engineering problems are outlined. This paper demonstrates that future wireless applications and systems have to cope with a wide variety of heterogenous infrastructures ranging from short range local area high speed (100Mbit/s) systems to low speed long range and wide area satellite based systems.

  • 96.
    Meincke, Thomas
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    Ellervee, Peeter
    Öberg, Johnny
    Kumar, Shashi
    Lindqvist, Dan
    Ericsson AB.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Postula, Adam
    Univ. of Queensland.
    Evaluating benefits of Globally Asynchronous Locally Synchronous VLSI Architecture1998Conference paper (Refereed)
  • 97.
    Meincke, Thomas
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kumar, Shashi
    KTH, School of Information and Communication Technology (ICT).
    Ellervee, Peeter
    KTH, School of Information and Communication Technology (ICT).
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Olsson, Thomas
    Dept. of Applied Electronics, Univ. of Lund.
    Nilsson, Peter
    Dept. of Applied Electronics, Univ. of Lund.
    Lindqvist, Dan
    Dept. of Computer Science, IIT New Delhi.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Globally asynchronous locally synchronous architecture for large high-performance ASICs1999In:  , 1999, Vol. 2, p. 512-515Conference paper (Refereed)
    Abstract [en]

    Clock nets are the major source of power consumption in large, high-performance ASICs and a design bottleneck when it comes to tolerable clock skew. A way to obviate the global clock net is to partition the design into large synchronous blocks each having its own clock. Data with other blocks is exchanged asynchronously using handshake signals. Adopting such a strategy requires a methodology that supports: 1) a partitioning method dividing a design into the number of synchronous blocks such that the gain due to global clock net removal exceeds the communication overhead and 2) synthesis of handshake protocols to implement the data transfer between synchronous blocks. We describe this methodology and present results of applying it to a realistic design done in 0.25 micron, ranging in operating frequencies from 20 MHz to 1 GHz. The results show that the net power savings compared to fully synchronous designs are on an average about 30%

  • 98. Meincke, Thomas
    et al.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ellervee, Peeter
    Hemani, Ahmed
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    A Generic Scheme for Communication Representation and Mapping1999In:  , 1999Conference paper (Refereed)
  • 99.
    Michielsen, Wim
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Shen, Meigen
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Zheng, Li-Rong
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Performance and cost estimations of packaged single band Voltage Controlled Oscillators2004In: PROCEEDINGS OF THE IEEE 6TH CIRCUITS AND SYSTEMS SYMPOSIUM ON EMERGING TECHNOLOGIES: FRONTIERS OF MOBILE AND WIRELESS COMMUNICATION, VOLS 1 AND 2, NEW YORK: IEEE , 2004, p. 53-56Conference paper (Refereed)
    Abstract [en]

    This paper reports the performance and cost estimations in the early stage of a LC tank based Voltage Controlled Oscillator (VCO) design. System-on-Chip (SoC) versus System-on-package (SoP) configurations is compared for electrical performance and cost of a 1.25 GHz voltage controlled oscillator. It is found that a single chip design is not always the best solution. We obtained the best figure of merit for a SoP implementation where only the inductors were put off-chip.

  • 100.
    Millberg, Mikael
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Öberg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    Waldemark, Joakim
    KTH, Superseded Departments, Physics.
    Generic VHDL Implementation of a PCNN with Loadable Coeffi­cients1998In: Proceedings of the Ninth Workshop of Virtual Intelligence/Dynamic Neural Networks: Neural Networks, Fuzzy Systems, Evolutionary Systems and Virtual Reality/Pulse Coupled Neural Networks / [ed] T. Lindblad, M. Padgett, 1998Conference paper (Refereed)
1234 51 - 100 of 196
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