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  • 51.
    Svantesson, Bengt
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Ellervee, Peeter
    KTH, Superseded Departments, Electronic Systems Design.
    Postula, Adam
    Dept. of Electrical and Computer Engineering, University of Queensland.
    Öberg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Tenhunen, Hannu
    KTH, Superseded Departments, Electronic Systems Design.
    Modeling and Synthesis of Operational and Management System (OAM) of ATM Switch Fabrics1995Conference paper (Refereed)
  • 52.
    Uddin, Saif
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    An improved transmission scheme for error-prone inter-chip Network-on-Chip communication links implemented on FPGAs2013In: 10th FPGAworld Conference - Academic Proceedings 2013, FPGAworld 2013, 2013Conference paper (Refereed)
    Abstract [en]

    Network-on-Chip (NoC) is an alternative to traditional busses for faster interconnect mechanism. The aim is to have infinite scalability, and this implies the possibility to extend the on-chip NoC communication protocol off-chip. To gain wholesome advantage of Network-on-Chip (NoC), off-chip extensions should also have similar communication throughput compared to the on-chip network. Faster data-rate is the single most demanded requirement of modern applications. There is a continuous drive to fulfill this escalating demand as much as possible. Two of the most prominent limiting factors in achieving this purpose are 'reduced accuracy' and 'protocol handling', especially in case of systems which do not have synchronous communication. Efficient optimizations are needed in multiple areas to upgrade the speed of data transfer. This paper presents an improved off-chip network solution to a slower and error-prone board-bridge part of a Network-on-Chip (NoC). The new solution increases the accuracy and speed of the plesiochronous off-chip extension to the NoC. The Network-on-Chip has 16 processor-nodes implemented on four interconnected plesiochronous Altera Stratix-II FPGA boards in 4x4 configuration in such a way that each board hosts a Quad-core NoC.

  • 53.
    Uddin, Saif
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Testing of an off-chip NoC protocol using a BIST/Synthesizable Testbench approach2012In: NORCHIP, 2012, IEEE , 2012, p. 6403128-Conference paper (Refereed)
    Abstract [en]

    To make systems infinitely scalable is the holy grail of chip design and crux that needs to be solved in order to invent a sustainable design methodology. Network-on-Chip (NoC) has been suggested as this solution as it replaces the traditional buses for on-chip interconnection purposes. However, to reach infinite scalability, off-chip extensions to the NoC protocols are needed in order to maintain scalability at an affordable cost of manufacturability. Going off-chip introduces more levels of complexity when it comes to testing, not only should the chip testing be speedy, the off-chip connections must also be testable in a fast manner, the fastest way being a set of BISTs testing the whole structure in parallel. In this paper, we present a BIST approach for testing an off-chip NoC protocol used in a 4x4 Network-on-Chip configuration. It has 16 processor-nodes implemented on four interconnected plesiochronous Altera Stratix-II FPGA boards, each board hosting a Quad-core NoC.

  • 54.
    Vasile, Massimiliano
    et al.
    Univ. of Strathclyde.
    Cartmell, Matthew
    Univ. of Glasgow.
    Zerihun Dejene, Firew
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Drysdale, T.
    Alaniz Flores, Monica
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Gulzar, Muhammad
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ismail, N.
    Khalid, Muhammad Usman
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Li, M.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Maddock, C.
    Mallol, Pau
    KTH, School of Engineering Sciences (SCI), Mechanics, Structural Mechanics.
    Mathieson, A.
    McRobb, M.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Purcell, O.
    Reynolds, P.
    Ritterbusch, Rafael
    KTH, School of Engineering Sciences (SCI), Mechanics.
    Sandqvist, William
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Summerer, L.
    Tanveer, Muhammad Usman
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Tibert, Gunnar
    KTH, School of Engineering Sciences (SCI), Mechanics, Structural Mechanics.
    Whyte, G.
    Zafar, W.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zhang, J.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    The Suaineadh Project: a Stepping Stone Towards the Deployment of Large Flexible Structures in Space2010In: Proceedings of the 61st International Astronautical Congress, the International Astronautical Federation , 2010, p. IAC-10-C3.4-Conference paper (Refereed)
    Abstract [en]

    The Suaineadh project aims at testing the controlled deployment and stabilization of space web. The deployment system is based on a simple yet ingenious control of the centrifugal force that will pull each of the four daughters sections apart. The four daughters are attached onto the four corners of a square web, and will be released from their initial stowed configuration attached to a central hub. Enclosed in the central hub is a specifically designed spinning reaction wheel that controls the rotational speed with a closed loop control fed by measurements from an onboard inertial measurement sensor. Five other such sensors located within the web and central hub provide information on the surface curvature of the web, and progression of the deployment. Suaineadh is currently at an advanced stage of development: all the components are manufactured with the subsystems integrated and are presently awaiting full integration and testing. This paper will present the current status of the Suaineadh project and the results of the most recent set of tests. In particular, the paper will cover the overall mechanical design of the system, the electrical and sensor assemblies, the communication and power systems and the spinning wheel with its control system.

  • 55.
    Wosinska, Lena
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Haralson, Joanna
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Thylén, Lars
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Öberg, Johnny
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hessmo, Björn
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Benefit of Implementing Novel Optical Buffers in an Asynchronous Photonic Packet Switch2004In: Proceedings of ECOC-04, 2004Conference paper (Refereed)
  • 56.
    Wosinska, Lena
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Thylén, Lars
    KTH, School of Information and Communication Technology (ICT), Optics and Photonics.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Buffering and control in an all-optical packet switching node2005In: 2005 7th International Conference on Transparent Optical Networks, Vol 1, Proceedings, 2005, p. 205-211Conference paper (Refereed)
    Abstract [en]

    In this paper we study novel types of optical memories in context of their usefulness for optical buffering applications. We describe a new type of photonic packet switch with electrical shared buffering and show that the employment of a few optical buffer positions to complement the electronic ones significantly improves the switch performance. Different admission algorithms are applied in order to provide quality of service support. Furthermore, we propose two designs for the node control block.

  • 57.
    Öberg, Johnny
    KTH, Superseded Departments, Electronic Systems Design.
    An Adaptable Environment for Improved High-Level Synthesis1996Licentiate thesis, monograph (Other academic)
  • 58.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Synthesis of VLIW accelerators from formal descriptions in a real-time multi-core environment2017In: 14th FPGAworld Conference, FPGAworld 2017 - Academic Proceedings 2017, Association for Computing Machinery (ACM), 2017, p. 23-29Conference paper (Refereed)
    Abstract [en]

    Designing, programming and design space exploration of predictable Real-Time systems on Heterogeneous Multi-Core platforms is a very complex task. The increasing validation costs and time-to-market pressure creates a desire to build systems that are correct by construction. Formal description based on Model of Computations (MoCs) is a convenient way to create high-level models of such systems. The MoCs provide abstraction and high level modeling through a clear set of rules based on mathematics, which can be used as input for system synthesis. A formal synthesis flow would then ensure that the resulting real-time system is both predictable and correct by construction, provided that all transformations used in the flow can be verified/trusted. In this paper we show how a Real-Time computation node in an MPSoC system, described using the Synchronous MoC, can be transformed into a VLIW accelerator. The created accelerator is incorporated as a computation node in a heterogeneous multi-core system implemented on an FPGA.

  • 59.
    Öberg, Johnny
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Ellervee, Peeter
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    BABBAGE - A Rule basedtool for synthesis of hardware systems1994In: Proc. of IEEE NORCHIP’94, 1994Conference paper (Refereed)
  • 60.
    Öberg, Johnny
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Ellervee, Peeter
    KTH, Superseded Departments, Electronic Systems Design.
    Kumar, Anshul
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Comparing Conventional HLS with Grammar-Based Hardware Synthesis: A Case Study1997In: Proc. of IEEE NORCHIP, 1997Conference paper (Refereed)
  • 61.
    Öberg, Johnny
    et al.
    KTH, Superseded Departments, Electrical Systems.
    Ellervee, Peeter
    Mokhtari, Mehran
    Jantsch, Axel
    KTH, Superseded Departments, Electrical Systems.
    Hemani, Ahmed
    A 1 GIPS Peak Performance Multi-Threaded Processor Core Using Interleaved Processing And A Revolving register File Targeted for GaAs1995Conference paper (Refereed)
  • 62.
    Öberg, Johnny
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Isoaho, Jouni
    Tampere University of Technology, Signal Processing Laboratory.
    Ellervee, Peeter
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A rule-based approach for improving allocation of filter structures in HLS1996In: Ninth International Conference on VLSI Design, 1996. Proceedings, IEEE conference proceedings, 1996, p. 133-139Conference paper (Refereed)
    Abstract [en]

    A rule based allocator for improving synthesis of filter systems is presented. The principles of the Enhanced AIlocation Rule Language Interpreter (EARLI) are presented. Possible transformations, optimisations and how to express them in EARLI are discussed. Experiments show that relative area gains ranging from 5 to 44%, depending on the chosen target technology, can be achieved using the designers knowledge about the design class. Experiments also indicate that employing direct mapping of CDFG subgraphs onto preoptimised RTL-level macroblocks would have resulted in a relative area gain of 500%. The macroblock had only 16% of the area produced by the HLS-tool

  • 63.
    Öberg, Johnny
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Kumar, A
    Hemani, Ahmed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Grammar-based hardware synthesis from port-size independent specifications2000In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 8, no 2, p. 184-194Article in journal (Refereed)
    Abstract [en]

    A protocol defines how systems communicate, There are two ways of specifying the protocol, the language of communication, One way is to specify the automaton that recognizes the language, and this is the approach taken by SDL, etc. The other more abstract way is to specify the grammar of the language and let a tool synthesize the automaton, Directly specifying the automaton makes the specification implementation dependent in two ways: the time behavior is specified in terms of states, and the width of the inputs and outputs is fixed, By specifying the grammar, the specification is potentially independent of both these implementation details and allows design space exploration in these dimensions. This paper presents a grammar-based language, called ProGram, that supports a port-size independent specifications methodology and its application to parts of the Operation and Maintenance protocol, a typical application from the ATM world. The methodology has also been applied to another test set of example designs and compared to standard RTL synthesis and HLS in order to evaluate the quality of the produced designs.

  • 64.
    Öberg, Johnny
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Kumar, Anshul
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hemani, Ahmed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Grammar-based hardware synthesis from port-size independent specifications2000In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 8, p. 184-194Article in journal (Refereed)
    Abstract [en]

    A protocol defines how systems communicate. There are two ways of specifying the protocol, the language of communication. One way is to specify the automaton that recognizes the language, and this is the approach taken by SDL, etc. The other more abstract way ss to specify the grammar of the language and let a tool synthesize the automaton. Directly specifying the automaton makes the specification implementation dependent in two ways: the time behavior is specified in terms of states, and the width of the inputs and outputs is fixed. By specifying the grammar, the specification is potentially independent of both these implementation details and allows design space exploration in these dimensions. This paper presents a grammar-based language, called Program, that supports a port-size independent specifications methodology and its application to parts of the Operation and Maintenance protocol, a typical application from the ATM world. The methodology has also been applied to another test set of example designs and compared to standard RTL synthesis and HLS in order to evaluate the quality of the produced designs.

  • 65.
    Öberg, Johnny
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Kumar, Anshul
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Grammar-based hardware synthesis of data communication protocols1996In: System Synthesis, 1996. Proceedings., 9th International Symposium on, 1996, p. 14-19Conference paper (Refereed)
    Abstract [en]

    For a synthesis methodology to support implementation independent design specification, a capability for design space exploration is essential. In this paper we present such a methodology for a specific domain: data communication protocols. A natural way to specify various elements of protocols is in terms of a grammar annotated with actions. Our language for protocol specification, called PRO-GRAM, is based on this idea. The hardware specification of the protocol is done by specifying the bit-patterns of the tokens the protocol is supposed to parse together with the actual grammar to parse the input stream. By specifying constraints on the input and output stream ports, the designer is allowed to explore alternative realisations with different widths of the I/O ports. The PRO-GRAM compiler outputs VHDL-code suitable for logic synthesis

  • 66.
    Öberg, Johnny
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kumar, Anshul
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Scheduling of outputs in grammar-based hardware synthesis of data communication protocols1998In: Design, Automation and Test in Europe, 1998., Proceedings, 1998, p. 596-603Conference paper (Refereed)
    Abstract [en]

    We present a grammar based specification method for hardware synthesis of data communication protocols in which the specification is independent of the port size. Instead, it is used during the synthesis process as a constraint. When the width of the output assignments exceed the chosen output port width, the assignments are split and scheduled over the available states. We present a solution to this problem and results of applying it to some relevant problems

  • 67.
    Öberg, Johnny
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Kumar, Anshul
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Hemani, Ahmed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Kumar, Shashi
    Indian Institute of Technology.
    Specification and Synthesis of Exception Handling in Grammar-based Hardware Synthesis1998In: Journal of Electrical Engineering and Information Science, Korea, Vol. 3, no 6, p. 724-735Article in journal (Refereed)
  • 68.
    Öberg, Johnny
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Mellander, Roger
    ABB Research.
    Zahrai, Said
    ABB Research.
    The ABB NoC: A Deflective Routing 2x2 Mesh NoC targeted for Xilinx FPGAs2008In: Proceedings of FPGAWorld 2008, 2008Conference paper (Refereed)
  • 69.
    Öberg, Johnny
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    O'Nils, M
    Jantsch, Axel
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Postula, A
    Hemani, Ahmed
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Grammar-based design of embedded systems2001In: Journal of systems architecture, ISSN 1383-7621, E-ISSN 1873-6165, Vol. 47, no 3-4, p. 225-240Article in journal (Refereed)
    Abstract [en]

    Grammars define syntax of languages and as such have not been commonly considered as methods for design, despite well-known applications in computer science. Only in recent years grammar-based design has become a promising research field and the first commercial tools have appeared on the market. This paper reviews the basic concepts of applying grammars to electronic design - in particular to the device driver synthesis of communication protocols for embedded software, to the design of custom-hardware, and to the virtual prototyping of DSP systems. The paper shows the power of these methods, presents the latest research results and discusses future developments in this field.

  • 70.
    Öberg, Johnny
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Plosila, Juha
    Ellervee, Peeter
    Automatic synthesis of asynchronous circuits from synchronous RTL descriptions2005In: Norchip 2005, Proceedings, 2005, p. 200-205Conference paper (Refereed)
    Abstract [en]

    As the dimensions of ASICs shrink down to the nanometer regime, the variability of the process parameters will increase. This variability threatens to make it extremely difficult to distribute a synchronous clock. all over the chip. Another option would be to replace critical synchronous parts with asynchronous counterparts with the same functionality. The main problems are, first, there is no established tool-flow that makes it easy for a designer to design an asynchronous circuits, and, second, there are no established design automation tools, except a few experimental ones. In addition, most designers today are trained to design synchronous circuits and have to be retrained. In this paper we present a method that solves all three of these problems, i.e., it allows a designer to start in the synchronous domain, and then automatically transform the synchronous representation of the circuit into an asynchronous one.

  • 71.
    Öberg, Johnny
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Robino, Francesco
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A NoC Generator for the Sea-of-Cores Era2011In: Proceedings of FPGAWorld 2011, 2011Conference paper (Refereed)
  • 72.
    Öberg, Johnny
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Robino, Francesco
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A NoC system generator for the Sea-of-Cores era2011In: 8th FPGAworld Conference - Academic Proceedings 2011, 2011, p. 35-40Conference paper (Refereed)
    Abstract [en]

    Multi-core systems are getting bigger. The number of cores is doubling every 18 months, in corollary with the reformulated Moore's law. Soon, the number of cores that can be integrated together in a system will be so large, that it is appropriate to talk about a new SoC design paradigm, the Sea-of-Cores era. This development will not end, even when CMOS cannot be made any smaller. Instead, with the development of Through-Silicon Vias (TSVs), chips will be stacked in 3D, promising continuous scaling for a very long time ahead. As systems grow, programming and debugging of them will become harder. Methods for generating the systems from higher-level specifications will be necessary to manage design complexity. Also, there will be so many processors to be programmed, that the SW also will have to be automatically generated and distributed, much in the same way as a synthesis and place & route tool is doing today for HW. In this paper, we present a NoC generator that can generate an arbitrarily large Multi-core platform from an XML configuration file, targeted for single-chip FPGA platforms. The NoC generator also generates a device driver prototype together with a small test program that can be used as a template for creating larger programs.

12 51 - 72 of 72
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