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  • 51.
    Domeij, Martin
    et al.
    KTH, Superseded Departments, Electronics.
    Breitholtz, Bo
    KTH, Superseded Departments, Electronics.
    Linnros, Jan
    KTH, Superseded Departments, Electronics.
    Östling, Mikael
    KTH, Superseded Departments, Electronics.
    Reverse Recovery and Avalance Injection in High Voltage SiC PIN Diodes1998In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 264-268, p. 1041-Article in journal (Other academic)
  • 52.
    Domeij, Martin
    et al.
    KTH, Superseded Departments, Electronics.
    Breitholtz, Bo
    KTH, Superseded Departments, Electronics.
    Lutz, Josef
    Östling, Mikael
    KTH, Superseded Departments, Electronics.
    Dynamic avalanche in Si power diodes and impact ionization at the nn(+) junction2000In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 44, no 3, p. 477-485Article in journal (Refereed)
    Abstract [en]

    The reverse recovery failure limit was measured with an optical technique for power diodes which sustain high levels of dynamic avalanche. Measurements and simulations indicate that these diodes withstand dynamic avalanche at the pn-junction and eventually fail as a result of a strongly inhomogeneous current distribution caused by the onset of impact ionisation at the diode nn(+) junction - a mechanism similar to the reverse bias second breakdown of bipolar transistors.

  • 53.
    Domeij, Martin
    et al.
    KTH, Superseded Departments, Electronics.
    Breitholtz, Bo
    KTH, Superseded Departments, Electronics.
    Östling, Mikael
    KTH, Superseded Departments, Electronics.
    Lutz, Josef
    Stable dynamic avalanche in Si power diodes1999In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 74, no 21, p. 3170-3172Article in journal (Refereed)
    Abstract [en]

    A stable dynamic avalanche at a maximum power density of about 2.4 MW/cm(2) was measured in small areas of 3.3 kV Si power diodes, using an optical measurement technique, and very good dynamic ruggedness was verified in a conventional turn-off measurement. Device simulations of a diode with a shallow n(+) emitter indicate that impact ionization at the nn(+) junction can result in negative differential resistance (NDR) and current filamentation, whereas a deep n(+) emitter in the experimentally studied diode suppresses NDR. It is, therefore, proposed that the deep n(+) emitter is important for the stable dynamic avalanche.

  • 54.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Danielsson, Erik
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Current gain of 4H-SiC bipolar transistors including the effect of interface states2005In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 483, p. 889-892Article in journal (Refereed)
    Abstract [en]

    The current gain (β) of 4H-SiC BJTs as function of collector current (I-C) has been investigated by DC and pulsed measurements and by device simulations. A measured monotonic increase of β with I-C agrees well with simulations using a constant distribution of interface states at the 4H-SiC/SiO2 interface along the etched side-wall of the base-emitter junction. Simulations using only bulk recombination, on the other hand, are in poor agreement with the measurements. The interface states degrade the simulated current gain by combined effects of localized recombination and trapped charge that influence the surface potential. Additionally, bandgap narrowing has a significant impact by reducing the peak current gain by about 50% in simulations.

  • 55.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Danielsson, Erik
    Liu, W.
    Zimmermann, U.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Measurements and simulations of self-heating and switching with 4H-SIC power BJTs2003In: IEEE International Symposium on Power Semiconductor Devices and ICs (ISPSD), Cambridge, 2003, p. 375-378Conference paper (Refereed)
    Abstract [en]

    Transient measurements and device simulations were performed to investigate self-heating and switching with 4H-SiC BJTs. A current gain decrease was found during self-heating presumably due to reduced electron mobility with increasing temperature. Surface recombination increased the simulated maximum temperature but the current gain decrease during self-heating was similar as for bulk recombination. A fast switching of 0.5 A and 200 V was shown with a voltage rise-time of about 70 ns and fall-time of 50 ns. Turn-off measurements show a noticeable delay time before fall-off of the emitter current, indicating a significant amount of stored carriers in the base.

  • 56.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Danielsson, Erik
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Schöner, Adolf
    Acreo AB, Stockholm .
    Geometrical effects in high current gain 1100-V 4H-SiC BJTs2005In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 26, no 10, p. 743-745Article in journal (Refereed)
    Abstract [en]

    This paper reports the fabrication of epitaxial 4H-SiC bipolar junction transistors (BJTs) with a maximum current gain beta = 64 and a breakdown voltage of 1100 V. The high beta value is attributed to high material quality obtained after a continuous epitaxial growth of the base-emitter junction. The BJTs show a clear emitter-size effect indicating that surface recombination has a significant influence on beta. A minimum distance of 2-3 mu m between the emitter edge and base contact implant was found adequate to avoid a substantial beta reduction.

  • 57.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Analysis of the base current and saturation voltage in 4H-SiC power BJTs2007In: 2007 European Conference On Power Electronics And Applications: Vols 1-10, 2007, p. 2744-2750Conference paper (Refereed)
    Abstract [en]

    Silicon carbide (SiC) power bipolar junction transistors are interesting competitors to Si IGBTs for 1200 V power electronics applications. Advantages of SiC BJTs are low collector-emitter saturation voltages, little stored charge and high temperature capability. In this work, SiC NPN power BJTs with common emitter current gains of 40 have been fabricated and characterized. Electrical measurements for BJTs with different emitter widths indicate that the current gain is limited by surface recombination. A low value of V-CESAT=0.9 V at J(C)=100 A/cm(2) was obtained for small and large area (3.4 mm(2)) BJTs and correlated with the formation of low-resistive ohmic contacts to the base. Large area BJTs were shown to operate with a current gain of 48 in pulsed mode at a collector current of 12 A corresponding to J(C)=360 A/cm(2).

  • 58.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Schoner, A.
    Current gain dependence on emitter width in 4H-SiC BJTs2006In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 527-529, p. 1425-1428Article in journal (Refereed)
    Abstract [en]

    This paper reports the fabrication of epitaxial 4H-SiC bipolar junction transistors (BJTs) with a maximum current gain beta = 64 and a breakdown voltage of 1100 V. The high beta value is attributed to high material quality obtained after a continuous epitaxial growth of the base-emitter junction. The current gain of the BJTs increases with increasing emitter width indicating a significant influence of surface recombination. This "emitter-size" effect is in good agreement with device simulations including recombination in interface states at the etched termination of the base-emitter junction.

  • 59.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Schöner, A.
    SiC power bipolar junction transistors: Modeling and improvement of the current gain2005In: 2005 European Conference on Power Electronics and Applications, Dresden, 2005, Vol. 2005, p. 1665888-Conference paper (Refereed)
    Abstract [en]

    Epitaxial silicon carbide bipolar junction transistors (BJTs) for power switching applications have been designed and fabricated with a maximum breakdown voltage of 1100 V. The BJTs have high common emitter current gains with maximum values exceeding 60, a result that is attributed to design optimization of the base and emitter layers and to a high material quality obtained by a continuous epitaxial growth. Device simulations of the current gain as function of collector current have been compared with measurements. The measurements show a clear emitter-size effect that is in good agreement with simulations including surface recombination in interface states at the etched termination of the base-emitter junction. Simulations indicate an optimum emitter doping around 1-1019 cm-3 in agreement with typical state-of-the-art BJTs.

  • 60.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Schöner, Adolf
    High current gain silicon carbide bipolar power transistors2006In: Proceedings of the 18th International Symposium on Power Semiconductor Devices and ICs, 2006, p. 141-144Conference paper (Refereed)
    Abstract [en]

    Silicon carbide NPN bipolar junction transistors were fabricated and a current gain exceeding 60 was obtained for a BJT with a breakdown voltage BV(CEO)=1100 V. A reduction of the current gain was observed after contact annealing at 950 degrees C and this was attributed to degradation of the oxide passivation. Device simulations with varying emitter doping resulted in a maximum current gain for an emitter doping around 1(.)10(19) cm(-3). Resistive turn-off measurements were performed and a minimum collector-emitter voltage (V(CE)) rise-time of 40 ns was found. The VCE rise-time showed a clear dependence on the on-state base current thus indicating a significant stored charge.

  • 61.
    Domeij, Martin
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zaring, C.
    Konstantinov, A. O.
    Nawaz, M.
    Svedberg, J-O
    Gumaelius, K.
    Keri, I.
    Lindgren, A.
    Hammarlund, B.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Reimark, M.
    2.2 kV SiC BJTs with low V(CESAT) fast switching and short-circuit capability2010In: SILICON CARBIDE AND RELATED MATERIALS 2009, PTS 1 AND 2 / [ed] Bauer, AJ; Friedrichs, P; Krieger, M; Pensl, G; Rupp, R; Seyller, T, 2010, p. 1033-1036Conference paper (Refereed)
    Abstract [en]

    This paper reports large active area (15 mm(2)) 4H-SiC BJTS with a low V(CESAT)=0.6 V at 1(C)=20 A (J(C)=133 A/cm(2)) and an open-base breakdown voltage BV(CEO)=2.3 kV at T=25 degrees C. The corresponding room temperature specific on-resistance R(SP.ON)=4.5 m Omega cm(2) is to the authors knowledge the lowest reported value for a large area SiC BJT blocking more than 2 kV. The onstate and blocking characteristics were analyzed by device simulation and found to be in good agreement with measurements. Fast switching with VcE rise- and fall-times in the range of 20-30 ns was demonstrated for a 6 A 1200 V rated SiC BJT. It was concluded that high dynamic base currents are essential for fast switching to charge the BJT parasitic base-collector capacitance. In addition, 10 mu s short-circuit capability with V(CE)=800 V was shown for the 1200 V BJT.

  • 62. Donetti, L.
    et al.
    Gamiz, F.
    Thomas, S.
    Whall, T. E.
    Leadley, D. R.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hole effective mass in silicon inversion layers with different substrate orientations and channel directions2011In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 110, no 6, p. 063711-Article in journal (Refereed)
    Abstract [en]

    We explore the possibility to define an effective mass parameter to describe hole transport in inversion layers in bulk MOSFETs and silicon-on-insulator devices. To do so, we employ an accurate and computationally efficient self-consistent simulator based on the six-band k . p model. The valence band structure is computed for different substrate orientations and silicon layer thicknesses and is then characterized through the calculation of different effective masses taking account of the channel direction. The effective masses for quantization and density of states are extracted from the computed energy levels and subband populations, respectively. For the transport mass, a weighted averaging procedure is introduced and justified by comparing the results with hole mobility from experiments and simulations.

  • 63. Donetti, L.
    et al.
    Gámiz, F.
    Thomas, S. M.
    Whall, T. E.
    Leadley, D. R.
    Hellström, Per -Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    On the effective mass of holes in inversion layers2011In: International Conference on Ultimate Integration on Silicon, 2011, p. 50-53Conference paper (Refereed)
    Abstract [en]

    We study hole inversion layers in bulk MOSFETs and silicon-on-insulator devices employing a self-consistent simulator based on the six-band kp model. Valence Band structure is computed for different device orientations and silicon layer thicknesses, and then it is characterized through the calculation of different effective masses.

  • 64. Driussi, F.
    et al.
    Esseni, D.
    Selmi, L.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Grasby, T. J.
    Leadley, D. R.
    Mescot, X.
    On the electron mobility enhancement in biaxially strained Si MOSFETs2008In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 52, no 4, p. 498-505Article in journal (Refereed)
    Abstract [en]

    This paper reports a detailed experimental and simulation study of the electron mobility enhancement induced by the biaxial strain in (001) silicon MOSFETs. To this purpose, ad hoc test structures have been fabricated on strained Si films grown on different SiGe virtual substrates and the effective mobility of the electrons has been extracted. To interpret the experimental results, we performed simulations using numerical solutions of Schroedinger-Poisson equations to calculate the charge and the momentum relaxation time approximation to calculate the mobility. The mobility enhancement with respect to the unstrained Si device has been analyzed as a function of the Ge content of SiGe substrates and of the operation temperature.

  • 65.
    Eklund, Anders
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Bonetti, Stefano
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF.
    Sani, Sohrab R.
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF.
    Mohseni, Seyed Majid
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF.
    Persson, Johan
    Chung, Sunjae
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF.
    Banuazizi, S. Amir Hossein
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics.
    Iacocca, Ezio
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Åkerman, Johan
    KTH, School of Information and Communication Technology (ICT), Materials- and Nano Physics, Material Physics, MF.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dependence of the colored frequency noise in spin torque oscillators on current and magnetic field2014In: Applied Physics Letters, ISSN 0003-6951, E-ISSN 1077-3118, Vol. 104, no 9, p. 092405-Article in journal (Refereed)
    Abstract [en]

    The nano-scale spin torque oscillator (STO) is a compelling device for on-chip, highly tunable microwave frequency signal generation. Currently, one of the most important challenges for the STO is to increase its longer-time frequency stability by decreasing the 1/f frequency noise, but its high level makes even its measurement impossible using the phase noise mode of spectrum analyzers. Here, we present a custom made time-domain measurement system with 150MHz measurement bandwidth making possible the investigation of the variation of the 1/f as well as the white frequency noise in a STO over a large set of operating points covering 18-25GHz. The 1/f level is found to be highly dependent on the oscillation amplitude-frequency non-linearity and the vicinity of unexcited oscillation modes. These findings elucidate the need for a quantitative theoretical treatment of the low-frequency, colored frequency noise in STOs. Based on the results, we suggest that the 1/f frequency noise possibly can be decreased by improving the microstructural quality of the metallic thin films.

  • 66.
    Ekström, Mattias
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Hou, Shuoben
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Elahipanah, Hossein
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Low temperature Ni-Al ohmic contacts to p-TYPE 4H-SiC using semi-salicide processing2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, Vol. 924, p. 389-392Conference paper (Refereed)
    Abstract [en]

    Most semiconductor devices require low-resistance ohmic contact to p-type doped regions. In this work, we present a semi-salicide process that forms low-resistance contacts (~10-4 Ω cm2) to epitaxially grown p-type (>5×1018 cm-3) 4H-SiC at temperatures as low as 600 °C using rapid thermal processing (RTP). The first step is to self-align the nickel silicide (Ni2Si) at 600 °C. The second step is to deposit aluminium on top of the silicide, pattern it and then perform a second annealing step in the range 500 °C to 700 °C.

  • 67.
    Ekström, Mattias
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Khartsev, Sergiy
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics.
    Integration and High-Temperature Characterization of Ferroelectric Vanadium-Doped Bismuth Titanate Thin Films on Silicon Carbide2017In: Journal of Electronic Materials, ISSN 0361-5235, E-ISSN 1543-186X, Vol. 46, no 7, p. 4478-4484Article in journal (Refereed)
    Abstract [en]

    4H-SiC electronics can operate at high temperature (HT), e.g., 300A degrees C to 500A degrees C, for extended times. Systems using sensors and amplifiers that operate at HT would benefit from microcontrollers which can also operate at HT. Microcontrollers require nonvolatile memory (NVM) for computer programs. In this work, we demonstrate the possibility of integrating ferroelectric vanadium-doped bismuth titanate (BiTV) thin films on 4H-SiC for HT memory applications, with BiTV ferroelectric capacitors providing memory functionality. Film deposition was achieved by laser ablation on Pt (111)/TiO2/4H-SiC substrates, with magnetron-sputtered Pt used as bottom electrode and thermally evaporated Au as upper contacts. Film characterization by x-ray diffraction analysis revealed predominately (117) orientation. P-E hysteresis loops measured at room temperature showed maximum 2P (r) of 48 mu C/cm(2), large enough for wide read margins. P-E loops were measurable up to 450A degrees C, with losses limiting measurements above 450A degrees C. The phase-transition temperature was determined to be about 660A degrees C from the discontinuity in dielectric permittivity, close to what is achieved for ceramics. These BiTV ferroelectric capacitors demonstrate potential for use in HT NVM applications for SiC digital electronics.

  • 68.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Process variation tolerant 4H-SiC power devices utilizing trench structures2013In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 740-742, p. 809-812Article in journal (Refereed)
    Abstract [en]

    Silicon carbide (SiC) is one of the most attractive semiconductors for high voltage applications. The breakdown voltage of SiC-based devices highly depends on the variation of the fabrication process including doping of the epilayers and the etching steps. In this paper, we show a way to diminish this variability by employing novel trench structures. The influence of the process variations in terms of doping concentration and etching has been studied and compared with conventional devices. The breakdown voltage variation (ΔVBr) of 450 V and 2100 V is obtained for the ±20% variation of doping concentration of the devices with and without the trench structures, respectively. For ±20% variation in etching steps, the maximum ΔVBR of 380 V is obtained for the device with trench structures in comparison to 1800 V for the conventional structure without trench structures. These results show that the breakdown voltage variation is significantly reduced by utilizing the proposed structure.

  • 69.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Calr-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Intertwined Design: A Novel Lithographic Method to Realize Area Efficient High Voltage SiC BJTs and Darlington Transistors2016In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, no 11, p. 4366-4372Article in journal (Refereed)
    Abstract [en]

    A novel lithographic method called intertwined design is demonstrated for high-power SiC devices to improve the area usage and current drive with more uniform current distribution along the device. The higher current drive is achieved by employing the inactive area underneath the base metal contact pads; more uniform current distribution is obtained by the center-base design; whereas the hexagon and square cell geometries result in >15% higher current density at lower on-resistance compared with the conventional finger design. For the first time, we have experimentally presented the intertwined design to marry these advantages and realize a high-efficient SiC power device. Center-base high-voltage 4H–SiC BJTs and Darlington pairs with different square and hexagon cell geometries are fabricated and compared with conventional designs to prove the ability of the intertwined design. The method can widely be used for large-area high-voltage BJTs as well as for integrated devices.

  • 70.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    4.5-kV 20-mΩ. cm2 Implantation-Free 4H-SiC BJT with Trench Structures on the Junction Termination Extension2015In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 821, p. 838-841Article in journal (Refereed)
    Abstract [en]

    A single-mask junction termination extension withtrench structures is formed to realize a 4.5 kV implantation-free 4H-SiCbipolar junction transistor (BJT). The trench structures are formed on the baselayer with dry etching using a single mask. The electric field distributionalong the structure is controlled by the number and dimensions of the trenches.The electric field is distributed by the trench structures and thus the electricfield crowding at the base and mesa edges is diminished. The design isoptimized in terms of the depth, width, spacing, and number of the trenches toachieve a breakdown voltage (VB) of 4.5 kV, which is 85% of thetheoretical value. Higher efficiency is obtainable with finer lithographicresolution leading to smaller pitch, and higher number and narrower trenches.The specific on-resistance (RON) of 20 mΩ.cm2 is measuredfor the small-area BJT with active area of 0.04 mm2. The BV-RONof the fabricated device is very close to the SiC limit and by far exceeds thebest SiC MOSFETs.

  • 71.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    5.8-kV Implantation-Free 4H-SiC BJT With Multiple-Shallow-Trench Junction Termination Extension2015In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 36, no 2, p. 168-170Article in journal (Refereed)
    Abstract [en]

    Implantation-free 4H-SiC bipolar junction transistors with multiple-shallow-trench junction termination extension have been fabricated. The maximum current gain of 40 at a current density of 370 A/cm(2) is obtained for the device with an active area of 0.065 mm(2). A maximum open-base breakdown voltage (BV) of 5.85 kV is measured, which is 93% of the theoretical BV. A specific ON-resistance (R-ON) of 28 m Omega.cm(2) was obtained.

  • 72.
    Elahipanah, Hossein
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Salemi, Arash
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Modification of etched junction termination extension for the high voltage 4H-SiC power devices2016In: Silicon Carbide and Related Materials, Trans Tech Publications, 2016, p. 978-981Conference paper (Refereed)
    Abstract [en]

    High voltage 4H-SiC bipolar junction transistors (BJTs) with modified etched junction termination extension (JTE) were fabricated and optimized in terms of the length (LJTE) and remaining dose (DJTE) of JTEs. It is found that for a given total termination length (Σ LJTEi), a decremental JTE length from the innermost edge to the outermost mesa edge of the device will result in better modification of the electric field. A breakdown voltage (BV) of 4.95 kV is measured for the modified device which shows ~20% improvement of the termination efficiency for no extra cost or extra process step. Equal-size BJTs by interdigitated-emitter with different number of fingers and cell pitches were fabricated. The maximum current gain of 40 is achieved for a single finger device with the emitter width of 40 μm at IC = 0.25 A (JC = 310 A/cm2) which corresponds to RON = 33 mΩ.cm2. It is presented that the current gain decreases by having more fingers while the maximum current gain is achieved at higher current density.

  • 73.
    Erdal, Suvar
    et al.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Haralson, Erik
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Wang, Yong-Bin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Malm, B. Gunnar
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    High frequency performance of SiGeCHBTs with selectively & non-selectively grown collector2004In: Physica Scripta, ISSN 0031-8949, E-ISSN 1402-4896, Vol. T114, p. 138-141Article in journal (Refereed)
    Abstract [en]

    Two high-frequency heterojunction bipolar transistor (HBT) architectures based on SiGeC have been fabricated and characterized. Different collector designs were applied either by using selective epitaxial growth doped with phosphorous or by non-selective epitaxial growth doped with arsenic. Both designs have a non-selectively deposited SiGeC base doped with boron and a poly-crystalline emitter doped with phosphorous. Both HBT designs exhibit similar electrical characteristics with a peak DC current gain of around 1600 and a BVCEO of 1.8V. The cut-off frequency (f(T)) and maximum frequency of oscillation (f(max)) vary from 40-80 GHz and 15-30 GHz, respectively, depending on lateral design relations. Good high frequency performance for a device with a selectively grown collector is demonstrated for the first time.

  • 74.
    Eriksson, K. G. Peter
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    A Simple and Reliable Electrical Method for Measuring the Junction Temperature and Thermal Resistance of 4H-SiC Power Bipolar Junction Transistors2009In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 600-603, p. 1171-1174Article in journal (Refereed)
    Abstract [en]

    To determine the maximum allowed power dissipation in a power transistor, it is important to determine the relationship between junction temperature and power dissipation. This work presents a new method for measuring the junction temperature in a SiC bipolar junction transistor (BJT) that is self-heated during DC forward conduction. The method also enables extraction of the thermal resistance between junction and ambient by measurements of the junction temperature as function of DC power dissipation. The basic principle of the method is to determine the temperature dependent IN characteristics of the transistor under pulsed conditions with negligible self-heating, and compare these results with DC measurements with self-heating. Consistent results were obtained from two independent temperature measurements using the temperature dependence of the current gain, and the temperature dependence of the base-emitter IN characteristics, respectively.

  • 75.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Elgammal, Karim
    KTH, Centres, SeRC - Swedish e-Science Research Centre. KTH, School of Engineering Sciences (SCI), Applied Physics.
    Smith, Anderson D.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits.
    Delin, Anna
    KTH, School of Industrial Engineering and Management (ITM), Materials Science and Engineering. KTH, Centres, SeRC - Swedish e-Science Research Centre. Department of Physics and Astronomy, Materials Theory Division, Uppsala University, Box 516, SE-75120 Uppsala, Sweden.
    Lemme, Max C.
    KTH, School of Information and Communication Technology (ICT), Electronics, Integrated devices and circuits. Department of Electronic Devices, RWTH Aachen University, 52074 Aachen, Germany.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Humidity and CO2 gas sensing properties of double-layer graphene2018In: Carbon, ISSN 0008-6223, E-ISSN 1873-3891, Vol. 127, p. 576-587Article in journal (Refereed)
    Abstract [en]

    Graphene has interesting gas sensing properties with strong responses of the graphene resistance when exposed to gases. However, the resistance response of double-layer graphene when exposed to humidity and gasses has not yet been characterized and understood. In this paper we study the resistance response of double-layer graphene when exposed to humidity and CO2, respectively. The measured response and recovery times of the graphene resistance to humidity are on the order of several hundred milliseconds. For relative humidity levels of less than ~ 3% RH, the resistance of double-layer graphene is not significantly influenced by the humidity variation. We use such a low humidity atmosphere to investigate the resistance response of double-layer graphene that is exposed to pure CO2 gas, showing a consistent response and recovery behaviour. The resistance of the double-layer graphene decreases linearly with increase of the concentration of pure CO2 gas. Density functional theory simulations indicate that double-layer graphene has a weaker gas response compared to single-layer graphene, which is in agreement with our experimental data. Our investigations contribute to improved understanding of the humidity and CO2 gas sensing properties of double-layer graphene which is important for realizing viable graphene-based gas sensors in the future.

  • 76.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Forsberg, Fredrik
    Scania Technical Centre.
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Wagner, Stefan
    AMO GmbH.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Lemme, Max C.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. RWTH Aachen University; AMO GmbH.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Suspended Graphene Membranes with Attached Silicon Proof Masses as Piezoresistive Nanoelectromechanical Systems Accelerometers2019In: Nano letters (Print), ISSN 1530-6984, E-ISSN 1530-6992, no 19, p. 6788-6799Article in journal (Refereed)
    Abstract [en]

    Graphene is an atomically thin material that features unique electrical and mechanical properties, which makes it an extremely promising material for future nanoelectromechanical systems (NEMS). Recently, basic NEMS accelerometer functionality has been demonstrated by utilizing piezoresistive graphene ribbons with suspended silicon proof masses. However, the proposed graphene ribbons have limitations regarding mechanical robustness, manufacturing yield, and the maximum measurement current that can be applied across the ribbons. Here, we report on suspended graphene membranes that are fully clamped at their circumference and have attached silicon proof masses. We demonstrate their utility as piezoresistive NEMS accelerometers, and they are found to be more robust, have longer life span and higher manufacturing yield, can withstand higher measurement currents, and are able to suspend larger silicon proof masses, as compared to the previous graphene ribbon devices. These findings are an important step toward bringing ultraminiaturized piezoresistive graphene NEMS closer toward deployment in emerging applications such as in wearable electronics, biomedical implants, and internet of things (IoT) devices.

  • 77.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Forsberg, Fredrik
    Scania Technical Centre.
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Wagner, Stefan
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Lemme, Max
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Suspended graphenemembranes with attached proof masses as piezoresistive NEMS accelerometersIn: Article in journal (Refereed)
  • 78.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Forsberg, Fredrik
    Scania Technical Centre.
    Smith, Anderson
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Wagner, Stefan
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Rödjegård, Henrik
    Senseair AB .
    Fisher, Andreas
    Silex Microsystems AB.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Lemme, Max
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Graphene beams with suspended masses as electromechanical transducers in ultra-small accelerometersIn: Article in journal (Refereed)
  • 79.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Fredrik, Forsberg
    Scania Technical Centre.
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. Senseair AB.
    Wagner, Stefan
    AMO GmbH.
    Rödjegård, Henrik
    Senseair AB.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. Silex Microsystems AB, Järfälla, Sweden.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Lemme, Max C.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. RWTH Aachen University ; AMO GmbH.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Graphene ribbons with suspended masses as transducers in ultra-small nanoelectromechanical accelerometers2019In: Nature Electronics, ISSN 2520-1131, Vol. 2, no 9, p. 394-404Article in journal (Refereed)
    Abstract [eo]

    Nanoelectromechanical system (NEMS) sensors and actuators could be of use in the development of next-generation mobile, wearable and implantable devices. However, these NEMS devices require transducers that are ultra-small, sensitive and can be fabricated at low cost. Here, we show that suspended double-layer graphene ribbons with attached silicon proof masses can be used as combined spring–mass and piezoresistive transducers. The transducers, which are created using processes that are compatible with large-scale semiconductor manufacturing technologies, can yield NEMS accelerometers that occupy at least two orders of magnitude smaller die area than conventional state-of-the-art silicon accelerometers. With our devices, we also extract the Young’s modulus values of double-layer graphene and show that the graphene ribbons have significant built-in stresses.

  • 80.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Forsberg, Fredrik
    Wagner, Stefan
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Fisher, Andreas
    Silex Microsystems AB.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Lemme, Max
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Manufacturing of Graphene Membranes with Suspended Silicon Proof Masses forMEMS and NEMSIn: Article in journal (Refereed)
  • 81.
    Farese, Luca
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Experimental Study of Degradation in 4H-SiC BJTs by Means of Electrical Characterization and Electroluminescence2010In: SILICON CARBIDE AND RELATED MATERIALS 2009 / [ed] Bauer AJ; Friedrichs P; Krieger M; Pensl G; Rupp R; Seyller T, 2010, Vol. 645-648, p. 1037-1040Conference paper (Refereed)
    Abstract [en]

    SiC power bipolar junction transistors (BJTs), for high voltage applications, have been studied under elevated temperature and electrical stress conditions. Electroluminescence has been used to capture effects of defect motion and growth, in complete transistor structures, leading to a quantifiable degradation in the electrical performance. The observed degradation of current gain (beta) and on-resistance (RON) was relatively modest and saturated after a limited stress time, resulting in stable device performance. The characteristic wavelength (450 nm) of the electroluminescence, or light emission, in the visual and near infrared (NIR) range, coupled to the shape of the defects indicates that basal plane dislocations and stacking faults are involved.

  • 82.
    Fuglesang, Christer
    et al.
    KTH, School of Engineering Sciences (SCI), Physics, Particle and Astroparticle Physics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Working on venus and beyond - SiC electronics for extreme environments2017In: Proceedings of the International Astronautical Congress, IAC, International Astronautical Federation, IAF , 2017, p. 10393-10398Conference paper (Refereed)
    Abstract [en]

    Venus is our closest planet, but we know much less about it than about Mars. The main reason for this is the extreme conditions, with a dense atmosphere of mainly CO2 at 92 bar atmosphere and 460 °C temperature at the surface. Only six spacecraft have succeeded to land on Venus and transmit data back to Earth; however none survived for long due to the high temperature. Venera-13 has the record, with 127 minutes at the surface of Venus in 1982. There are many compelling reasons to learn more about the sister planet of Earth, which requires measurements over months rather than minutes on the surface of Venus. Perhaps the single-most challenging task for long-term data taking on the surface of Venus is to build electronics that can operate at temperatures up to 500 °C without cooling. It seems that such technology must be based on wide bandgap semiconductors, such as GaN, SiC or diamond. At KTH, research with SiC devices and integrated circuits has been done for more than 20 years, demonstrating high voltage devices and digital integrated circuit operation at 600 °C. In 2014 the project Working On Venus launched, with funding from Knut and Alice Wallenberg Foundation. The goal is to demonstrate all the electronics for a complete working lander, with all electronics from sensors through amplifiers and analog-to-digital converters to microcontroller with memory and radio, including power supply. The particular sensors the project has in mind are seismic, gas and image sensors. So far, a 200 device level integration has been demonstrated at 500 °C and a 5000+ device level 4 bit microcontroller is being fabricated in an in-house bipolar technology. As for all devices for space, radiation is another concern. SiC integrated circuits have survived exposure to 3 MeV protons with fluences of 1013 cm-2 and gamma rays with doses of 332 Mrad. The dedicated project SUPERHARD IC will study manufacture methods for radiation hardened instrument components that could go beyond Venus, for example for Jovian system exploration. Members of Working on Venus are discussing with scientists seeking opportunities for a Venus Long-Life Surface Package (lander). In 2016 a response was submitted to ESA's Call for New Scientific Ideas. 

  • 83.
    Garidis, Konstantinos
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Jayakumar, Ganesh
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Asadollahi, Ali
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Dentoni Litta, Eugenio
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Characterization of bonding surface and electrical insulation properties of inter layer dielectrics for 3D monolithic integration2015In: EUROSOI-ULIS 2015 - 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, 2015, p. 165-168Conference paper (Refereed)
    Abstract [en]

    We investigate the bonding and electrical insulation properties of oxide layers for use in 3D monolithic integration via direct wafer bonding. Low surface roughness layers deposited on 100 mm Si wafers by atomic layer deposition (ALD) at 200 °C-350 °C, provide with adequate layer transfer bonding interfaces. Wafer scale IV measurements were performed to investigate the leakage current. We demonstrate that ALD oxide can function as a reliable bonding surface and also exhibit leakage current values below the nA range. Both properties are important pillars for a successful 3D monolithic integration.

  • 84.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Esteve, Romain
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Schöner, Adolf
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Han, Jisheng
    Dimitrijev, Sima
    Reshanov, Sergey A.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Surface-passivation effects on the performance of 4H-SiC BJTs2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, p. 259-265Article in journal (Refereed)
    Abstract [en]

    In this brief, the electrical performance in terms of maximum current gain and breakdown voltage is compared experimentally and by device simulation for 4H-SiC BJTs passivated with different surface-passivation layers. Variation in bipolar junction transistor (BJT) performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for plasma-deposited SiO2 which was annealed in N2O ambient at 1100 °C for 3 h. Variations in breakdown voltage for different surface passivations were also found, and this was attributed to differences in fixed oxide charge that can affect the optimum dose of the high-voltage junction-termination extension (JTE). The dependence of breakdown voltage on the dose was also evaluated through nonimplanted BJTs with etched JTE.

  • 85.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High-Voltage 4H-SiC PiN Diodes With Etched Junction Termination Extension2009In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 11, p. 1170-1172Article in journal (Refereed)
    Abstract [en]

    Implantation-free mesa-etched 4H-SiC PiN diodes with a near-ideal breakdown voltage of 4.3 kV (about 80% of the theoretical value) were fabricated, measured, and analyzed by device simulation and optical imaging measurements at breakdown. The key step in achieving a high breakdown voltage is a controlled etching into the epitaxially grown p-doped anode layer to reach an optimum dopant dose of similar to 1.2 x 10(13) cm(-2) in the junction termination extension (JTE). Electroluminescence revealed a localized avalanche breakdown that is in good agreement with device simulation. A comparison of diodes with single-and double-zone etched JTEs shows a higher breakdown voltage and a less sensitivity to varying processing conditions for diodes with a two-zone JTE.

  • 86.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High Voltage, Low On-resistance 4H-SiC BJTs with Improved Junction Termination Extension2011In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 679-680, p. 706-709Article in journal (Refereed)
    Abstract [en]

    In this work, implantation-free 4H-SiC bipolar transistors with two-zone etched-JTE and improved surface passivation are fabricated. This design provides a stable open-base breakdown voltage of 2.8 kV which is about 75% of the parallel plane breakdown voltage. The small area devices shows a maximum dc current gain of 55 at Ic=0.33 A (J(C)=825 A/cm(2)) and V-CESAT = 1.05 V at Ic = 0.107 A that corresponds to a low ON-resistance of 4 m Omega.cm(2). The large area device shows a maximum dc current gain of 52 at Ic = 9.36 A (J(C)=312 A/cm(2)) and V-CESAT = 1.14 V at Ic = 5 A that corresponds to an ON-resistance of 6.8 m Omega.cm(2). Also these devices demonstrate a negative temperature coefficient of the current gain (beta=26 at 200 degrees C) and positive temperature coefficient of the ON-resistance (R-ON = 10.2 m Omega.cm(2)).

  • 87.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High current-gain implantation-free 4H-SiC Monolithic Darlington Transistor2011In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 32, no 2, p. 188-190Article in journal (Refereed)
    Abstract [en]

    An implantation-free 4H-SiC Darlington transistor with high current gain of 2900 ( JC= \970A/cm2) and VCE) = 6V) at room temperature is reported. The device demonstrates a record maximum current gain of 640 at 200 hC, offering an attractive solution for high-temperature applications. The monolithic Darlington device exhibits an open-base breakdown voltage of 1 kV that is less than the optimum bulk breakdown due to isolation trench between the driver and the output bipolar junction transistor. On the same wafer, a monolithic Darlington pair with a nonisolated base layer was also fabricated. At room temperature, this device shows a maximum current gain of 1000 and an open-base breakdown voltage of 2.8 kV, which is 75% of the parallel-plane breakdown voltage

  • 88.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedotto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Shayestehaminzadeh, Seyedmohammad
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Influence of crystal orientation on the current gain in 4H-SiC BJTs2010In: Device Research Conference - Conference Digest, DRC, 2010, p. 131-132Conference paper (Refereed)
    Abstract [en]

    The 4H-SiC bipolar junction transistors (BJT) are considered as efficient high power switching devices due to the ability of obtaining very low specific on-resistance compared to FET based devices. However, one drawback with the present high voltage BJTs is the relatively low current gain. To reduce the power required by the drive circuit, it is important to increase the common-emitter current gain ( #x03B2;). 4H-SiC (0001) Si-face has become a favorable plane for vertical power BJTs with epitaxial layers that shows higher mobility along the c-axis and provides higher current gain. Furthermore, important progress on improving the current gain focused on the quality of surface passivation at the SiC/SiO2 interface has been reported during previous years. Higher quality of passivation can provide less interface traps and thereby minimizes the surface recombination current. Conventionally, vertical 4H-SiC BJTs are fabricated along the [11_00] direction on (0001) Si-face. However due to anisotropic properties of 4H-SiC, different orientations on Si-face can also affect the base current of the BJT through variation of mobility and interface traps density distribution along each direction. In this work, single-finger small area BJTs are fabricated on (0001) Si-face along [12_10], [011_0], [112_0] and [11_00] directions. This design can provide various orientations of BJTs that corresponds to an angular range between 0 to 180 degrees relative to conventional [11_00] direction. The goal was to find a correlation between different crystallographic orientation, mobility and interface traps density distribution through transistor characteristics and finally comparison with simulation. Fig.1 shows a cross section and top view of fabricated BJTs. The n+ emitter epi-layer is 1.35 #x03BC;m nitrogen doped to 6 #x00D7;1018 cm-3 and capped by 200-nm-thick 2 #x00D7;1019 cm-3 layer. The base epi-layer is 650 nm Al-d- - oped with concentration of 4.3 #x00D7;1017 cm-3. The drift n- epilayer is 20 #x03BC;m thick and doped to 6 #x00D7;1015 cm-3. Inductively coupled plasma (ICP) etching with an oxide mask was used to form emitter and base mesas. Fig.2 is a comparison of the maximum current gain with different orientations normalized to the maximum current gain along [11_00] before surface passivation and contact metallization. The results indicate that the maximum current gain is orientation-dependent and has a maximum for BJTs with the emitter edge aligned to the [112_0] direction. The variation effect of planar mobility and interface traps concentration on the current gain is simulated based on the previous work and is illustrated in Fig.3. The simulation shows that interface oxide charges has more influence on the current gain compared to the mobility and higher current gain is attributed to lower oxide interface charges. The orientation dependence of the transistor parameters such as maximum current gain after passivation and the base resistance will be evaluated and compared with simulation.

  • 89.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedotto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Shayestehaminzadeh, Seyedmohammad
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Removal of Crystal Orientation Effects on the Current Gain of 4H-SiC BJTs Using Surface Passivation2011In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 32, no 5, p. 596-598Article in journal (Refereed)
    Abstract [en]

    In this letter, the dependence of current gain and base resistance on crystal orientations for single-finger 4H-SiC bipolar junction transistors ( BJTs) is analyzed. Statistical evaluation techniques were also applied to study the effect of surface passivation and mobility on the performance of the devices. It is shown that BJTs with an emitter edge aligned to the [1 (2) under bar 10] direction shows a lower current gain before surface passivation and higher base resistance after contact formation compared with other investigated crystal directions. However, the devices show a similar current gain independent of the crystal orientation after surface passivation.

  • 90.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Esteve, R.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Schoner, A.
    Han, J.
    Dimitrijev, S.
    Reshanov, S. A.
    Zetterling, Carl -Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Experimental evaluation of different passivation layers on the performance of 3kV 4H-SiC BJTs2010In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 645-648, no Part 1-2, p. 661-664Article in journal (Refereed)
    Abstract [en]

    In this work, the electrical performance in terms of maximum current gain, ON-resistance and blocking capability has been compared for 4H-SiC BJTs passivated with different surface passivation layers. Variation in BJT performance has been correlated to densities of interface traps and fixed oxide charge, as evaluated through MOS capacitors. Six different methods were used to fabricate SiO2 surface passivation on BJT samples from the same wafer. The highest current gain was obtained for PECVD deposited SiO2 which was annealed in N2O ambient at 1100 degrees C during 3 hours. Variations in breakdown voltage for different surface passivations were also found, and this is attributed to differences in fixed oxide charge that can affect the optimum dose of the high voltage JTE termination.

  • 91.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    High Voltage (2.8 kV) Implantation-free 4H-SiC BJTs with Long-TermStability of the Current Gain2011In: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 58, no 8, p. 2665-2669Article in journal (Refereed)
    Abstract [en]

    In this work, implantation-free 4H-SiC BJTs with high breakdown of 2800 V have been fabricated utilizing acontrolled two-step etched junction termination extension (JTE). The small area devices show a maximum dc current gainof 55 at Ic=0.33 A (JC=825 A/cm2) and VCESAT = 1.05 V at Ic = 0.107 A that corresponds to a low ON-resistance of 4mΩ·cm2. The large area device have a maximum dc current gain of 52 at Ic = 9.36 A (JC=289 A/cm2) and VCESAT = 1.14 Vat Ic = 5 A that corresponds to an ON-resistance of 6.8 mΩ·cm2. Also these devices demonstrate a negative temperaturecoefficient of the current gain (β=26 at 200°C) and a positive temperature coefficient of the ON-resistance (RON = 10.2mΩ·cm2 at 200°C). The small area BJT shows no bipolar degradation and low current gain degradation after 150 Hrs stressof the base-emitter diode with current level of 0.2A (JE=500 A/cm2). Also, large area BJT shows a VCE fall time of 18 nsduring turn-on and a VCE rise time of 10 ns during turn-off for 400 V switching characteristics.

  • 92.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Hållstedt, Julius
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Lu, Jun
    Wise, R.
    Wejtmans, H.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    High boron incorporation in selective epitaxial growth of SiGe layers2007In: Journal of materials science. Materials in electronics, ISSN 0957-4522, E-ISSN 1573-482X, Vol. 18, no 7, p. 747-751Article in journal (Refereed)
    Abstract [en]

    Incorporation of high amount of boron in the range of 1 x 10(20)-1 x 10(21) cm(-3) in selective epitaxial growth (SEG) of Si1-xGex (x = 0.15-0.315) layers for recessed or elevated source/drain junctions in CMOS has been studied. The effect of high boron doping on growth rate, Ge content and appearance of defect in the epi-layers was investigated. In this study, integration issues were oriented towards having high layer quality whereas still high amount of boron is implemented and the selectivity of the epitaxy is preserved.

  • 93.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl - Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Implantation-Free Low on-resistance 4H-SiC BJTs with Common-Emitter Current Gain of 50 and High Blocking Capability2009In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 615-617, p. 833-836Article in journal (Refereed)
    Abstract [en]

    In this study, high voltage blocking (2.7 kV) implantation-free SiC Bipolar Junction Transistors with low on-state resistance (12 m Omega-cm(2)) and high common-emitter current gain of 50 have been fabricated. A graded base doping was implemented to provide a low resistive ohmic contact to the epitaxial base. This design features a fully depleted base layer close to the breakdown voltage providing an efficient epitaxial JTE without ion implantation. Eliminating all ion implantation steps in this approach is beneficial for avoiding high temperature dopant activation annealing and for avoiding generation of life-time killing defects that reduces the current gain. Also in this process large area transistors showed common-emitter current gain of 38 and open-base breakdown voltage of 2 kV.

  • 94.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Buono, Benedetto
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fabrication of 2700-v 12-m Omega center dot cm(2) non ion-implanted 4H-SiC BJTs with common-emitter current gain of 502008In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 29, no 10, p. 1135-1137Article in journal (Refereed)
    Abstract [en]

    High-voltage blocking (2.7-kV) implantation-free SiC bipolar junction transistors with low ON-state resistance (12 m Omega . cm(2)) and high common-emitter current gain of 50 have been fabricated. A graded-base doping was implemented to provide a low-resistive ohmic contact to the epitaxial base. This design features a fully depleted base layer close to the breakdown voltage providing an efficient epitaxial JTE without ion implantation. Eliminating all ion implantation steps in this approach is beneficial for avoiding high-temperature dopant activation annealing and for avoiding generation of lifetime-killing defects that reduce the current gain.

  • 95.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Ostling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Simultaneous study of nickel based ohmic contacts to Si-face and C-face of n-type silicon carbide2007In: 2007 INTERNATIONAL SEMICONDUCTOR DEVICE RESEARCH SYMPOSIUM, VOLS 1 AND 2, NEW YORK: IEEE , 2007, p. 311-311Conference paper (Refereed)
  • 96.
    Ghandi, Reza
    et al.
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Lee, Hyung-Seok
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Domeij, Martin
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Zetterling, Carl-Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Backside Nickel Based Ohmic Contacts to n-type Silicon Carbide2009In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 600-603, p. 635-638Article in journal (Refereed)
    Abstract [en]

    This work focuses on Ni ohmic contacts to the C-face (backside) of n-type 4H-SiC substrates. Low-resistive ohmic contacts to the wafer backside are important especially for vertical power devices. Ni contacts were deposited using E-beam evaporation and annealed at different temperatures (700-1050 degrees C) in RTP to obtain optimum conditions for forming low resistive ohmic contacts. Our results indicate that 1 min annealing at temperatures between 950 and 1000 degrees C provides high quality ohmic contacts with a contact resistivity of 2.3x10(-5) Omega cm(2). Also our XRD results show that different Ni silicide phases appear in this annealing temperature range.

  • 97. Grahn, J. V.
    et al.
    Fosshaug, H.
    Jargelius, M.
    Jonsson, P.
    Linder, M.
    Malm, B. Gunnar
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Mohadjeri, B.
    Pejnefors, J.
    Radamson, Henry H.
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Sanden, M.
    Wang, Yong-Bin
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Landgren, Gunnar
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, Superseded Departments, Microelectronics and Information Technology, IMIT.
    A low-complexity 62-GHz f(T) SiGe heterojunction bipolar transistor process using differential epitaxy and in situ phosphorus-doped poly-Si emitter at very low thermal budget2000In: Solid-State Electronics, ISSN 0038-1101, E-ISSN 1879-2405, Vol. 44, no 3, p. 549-554Article in journal (Refereed)
    Abstract [en]

    A low-complexity SiGe heterojunction bipolar transistor process based on differential epitaxy and in situ phosphorus doped polysilicon emitter technology is described. Silane-based chemical vapor deposition at reduced pressure was used for low-temperature SiGe epitaxy. Following SiGe epitaxy, the process temperature budget was kept very low with 900 degrees C for 10 s as the highest temperature step. A very high current gain of almost 2000 and cut off frequency of 62 GHz were achieved for a uniform 12% Ge profile. The breakdown voltage BVCEO and forward Early voltage were equal to 2.9 and 6.5 V, respectively.

  • 98.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Luo, Jun
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Lu, Jun
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Fully Depleted UTB and Trigate N-Channel MOSFETs Featuring Low-Temperature PtSi Schottky-Barrier Contacts With Dopant Segregation2009In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 30, no 5, p. 541-543Article in journal (Refereed)
    Abstract [en]

    Schottky-barrier source/drain (SB-S/D) presents a promising solution to reducing parasitic resistance for device architectures such as fully depleted UTB, trigate, or FinFET. In this letter, a low-temperature process (<= 700 degrees C) with PtSi-based S/D is examined for the fabrication of n-type UTB and trigate FETs on SOI substrate (t(si) = 30 nm). Dopant segregation with As was used to achieve the n-type behavior at implantation doses of 1 (.) 10(15) and 5. 10(15) cm(-2). Similar results were found for UTB devices with both doses, but trigate devices with the larger dose exhibited higher on currents and smaller process variation than their lower dose counterparts.

  • 99.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Information Technology, IMIT.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Characterization of dopant segregated Schottky barrier source/drain contacts2009In: ULIS 2009: 10TH INTERNATIONAL CONFERENCE ON ULTIMATE INTEGRATION OF SILICON / [ed] Mantl S, Lemme M, Schubert J, Albrecht W, NEW YORK: IEEE , 2009, p. 73-76Conference paper (Refereed)
    Abstract [en]

    In this paper, the gate-voltage dependent source/drain (S/D) resistance (R-SD) in dopant segregated (DS) Schottky barrier (SB) junctions is examined by experiment and simulation. The focus is placed on fully depleted UTB-SOI MOSFETs featuring PtSi S/D with As-DS realized at low temperatures. When modeling SB-S/D with DS, it is challenging to determine if the performance enhancement observed is induced by a highly doped shallow layer in Si or by an interfacial dipole causing SB height lowering. The simulation reveals that the gate-voltage dependence of R-SD is stronger for the dipole effect. For the SB-MOSFETs with DS-S/D examined in this work, the simulation gives an excellent fit to the measured data when SBH lowering is combined with high concentration shallow doping.

  • 100.
    Gudmundsson, Valur
    et al.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Hellström, Per-Erik
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Zhang, Shi-Li
    KTH, School of Information and Communication Technology (ICT), Microelectronics and Applied Physics, MAP.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Direct measurement of sidewall roughness on Si, poly-Si and poly-SiGe by AFM2008In: PROCEEDINGS OF THE 17TH INTERNATIONAL VACUUM CONGRESS/13TH INTERNATIONAL CONFERENCE ON SURFACE SCIENCE/INTERNATIONAL CONFERENCE ON NANOSCIENCE AND TECHNOLOGY / [ed] Johansson LSO, Andersen JN, Gothelid M, Helmersson U, Montelius L, Rubel M, Setina J, Wernersson LE, Bristol: IOP PUBLISHING LTD , 2008, Vol. 100Conference paper (Refereed)
    Abstract [en]

    In this paper the effect of the commonly used HBr/Cl-2 chemistry for dry etching on the line-edge roughness (LER) of photoresist patterned single crystalline Si (sc-Si), polycrystalline Si (poly-Si) and poly-Si0.2Ge0.8 sidewalls was characterized. Measurements were done by means of atomic force microscopy in combination with an elaborated sample preparation technique that allowed the LER at different depths of the sidewall to be measured. Samples were patterned by I-line lithography and etching was performed at an RF power of 200 W using HBr/Cl-2 (30/10 sccm) plasma. For sc-Si the photoresist and Si sidewalls had an LER of 0.8-1.4 nm and 1.5-2 nm, respectively. For poly-Si and poly-SiGe the photoresist sidewall roughness was, respectively, increased to 1.5-3 nm and 2-3.5 nm due to light scattering from the rough surface of the polycrystalline materials. The poly-Si film had a sidewall roughness of 3-4 nm. Poly-SiGe sidewall exhibited larger roughness with an LER of 5-12 nm which was not transferred from the photoresist. The results show that for sc-Si and poly-Si the sidewall roughness mainly originates from the photoresist process and little additional roughening is caused by the HBr/Cl-2 etching. However, for poly-Si0.2Ge0.8 the LER is considerably increased from that of the photoresist indicating that the HBr/Cl-2 etching is the main contributor to the LER.

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