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  • 51. Tian, K.
    et al.
    Hallén, Anders
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik, Integrerade komponenter och kretsar.
    Qi, J.
    Ma, S.
    Fei, X.
    Zhang, A.
    Liu, W.
    An Improved 4H-SiC Trench-Gate MOSFET With Low ON-Resistance and Switching Loss2019Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 66, nr 5, s. 2307-2313, artikkel-id 8681267Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In this paper, an improved 4H-SiC U-shaped trench-gate metal-oxide-semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (R ON ) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (V BR ). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM = V BR 2 /R ON ) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (T ON ) and turn-off time (T OFF ) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (E SW ). © 2019 IEEE.

  • 52. Tian, Kai
    et al.
    Hallén, Anders
    KTH, Tidigare Institutioner (före 2005), Elektronik. KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik, Integrerade komponenter och kretsar.
    Qi, Jinwei
    Ma, Shenhui
    Fei, Xinxing
    Zhang, Anping
    Liu, Weihua
    An Improved 4H-SiC Trench-Gate MOSFET With Low ON-Resistance and Switching Loss2019Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 66, nr 5, s. 2307-2313Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In this paper, an improved 4H-SiC U-shaped trench-gate metal-oxide-semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (R-ON) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (V-BR). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM = V-BR(2)/R-ON) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (T-ON) and turn-off time (T-OFF) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (E-SW).

  • 53.
    Tian, Ye
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Hedayati, Raheleh
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Zetterling, Carl-Mikael
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    SiC BJT Compact DC Model With Continuous- Temperature Scalability From 300 to 773 K2017Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, nr 9, s. 3588-3594Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The first vertical bipolar intercompany (VBIC)-based compact dc model has been developed and verified for a low-voltage 4H-SiC bipolar junction transistor to continuously map a wide temperature range from 300 to 773 K. Temperature and doping dependent physical models for bandgap, incomplete ionization, carrier mobility, and lifetime have been taken into account to give physically meaningful fitting parameters for the compact model. Isothermal simulations using the default VBIC model are performed to extract key parameter sets from measured data at seven different temperature points. Then new temperature dependent equations for the key parameters are proposed and embedded in the default VBIC model. Consequently, a single set of model parameters at 300 K is used to achieve fitting over a wide temperature range from 300 to 773 K. This new model can be used for simulating circuits that require continuous description of device dc performance over a wide temperature range.

  • 54.
    Tian, Ye
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Lanni, Luigia
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Rusu, Ana
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Zetterling, Carl-Mikael
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Silicon Carbide fully differential amplifier characterized up to 500 °C2016Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, nr 6, s. 2242-2247, artikkel-id 7451254Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper presents a monolithic fully differential amplifier implemented in a low-voltage 4H-silicon carbide bipolar junction transistor technology. The circuit has been designed, considering the variation of device parameters over a large temperature range. A base-current compensation technique has been applied to overcome the low input resistance of the amplifier. The bare chip of the amplifier has been measured from 27 °C to 500 °C using a hot-chuck probe station. Its openloop gain is 58 dB at 27 °C, and monotonically decreases to 37 dB at 500 °C. Its closed-loop gain reduction is ∼5 dB over the investigated temperature range. The gain-bandwidth product drops from 2.8 MHz at 27 °C to 1.3 MHz at 500 °C with 470 pF off-chip compensation capacitors. A low total-harmonicdistortion of −58.4 dB at 27 °C and −46.9 dB at 500 °C is achieved due to the fully differential implementation. A low input offset voltage of 0.5 mV at 27 °C and 6.9 mV at 500 °C is achieved without calibration. The relative high linearity and the low offset demonstrate the potential of this technology to be further investigated for the front-end sensor circuits in high-temperature applications.

  • 55.
    Tian, Ye
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Zetterling, Carl-Mikael
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    A Fully Integrated Silicon-Carbide Sigma–Delta Modulator Operating up to 500 °C2017Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, nr 7, s. 2782-2788Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper presents the first fully integrated sigma-delta modulator implemented in an in-house silicon carbide (SiC) bipolar technology for high-temperature applications. A second-order 1-b continuous-time architecture is adopted. Dual-loop compensation technique is employed to accommodate one clock period comparator delay. The circuits are designed to have enoughmargins without degrading the modulator's performance, considering the variation of device parameters over a large temperature range. The measurement results show that from room temperature to 500 degrees C, themodulator's peak SNDR is constant around 30 dB at a clock speed of 512 kHz. The chip area of the modulator is 6.9 mm x 2.8 mm with one metal layer. It consumes around 1 W from a 15 V power supply. This paper demonstrates the feasibility to further develop highly integrated SiC bipolar junction transistor integrated circuits for extremely high-temperature sensing applications.

  • 56. Usman, M.
    et al.
    Nawaz, M.
    Hallén, Anders
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Position-dependent bulk traps and carrier compensation in 4H-SiC bipolar junction transistors2013Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 60, nr 1, s. 178-185Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The influence of bulk traps in different regions of 4H-SiC bipolar junction transistors (BJTs) is investigated. The investigation is based on experimental results obtained by implanting up to 1011cm-2 fluences of helium ions in the collector region. The results indicate that implantations, creating point defect concentrations in the range of the doping level, produce a sufficiently high concentration of traps to reduce the carrier concentration in this specific region. These traps degrade the device characteristics and are irrecoverable up to 500°C annealing. The experimental results are qualitatively analyzed by device simulations using a 2D numerical computer-aided design tool (TCAD). Systematic simulations are then performed by introducing traps at different locations in the BJT (i.e., emitter, base, and collector regions). The results indicate that the device performance is highly dependent on the defect concentration in the base region. The defects at different levels inside the collector also influence the device by producing a compensated layer in the material. However, the same concentration of defects (i.e., ∼10 15cm-3) has less influence in the emitter region.

  • 57.
    Usman, Muhammad
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Buono, Benedetto
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Hallén, Anders
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Impact of Ionizing Radiation on the SiO2/SiC Interface in 4H-SiC BJTs2012Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 59, nr 12, s. 3371-3376Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Degradation of SiO2 surface passivation for 4H-SiC power bipolar junction transistors (BJTs) as a result of ion irradiation has been studied to assess the radiation hardness of these devices. Fully functional BJTs with 2700 V breakdown voltage are implanted with 600 keV helium ions at fluences ranging from 1 x 10(12) to 1 x 10(16) cm(-2) at room temperature. These ions are estimated to reach the SiO2/SiC interface. The current-voltage characteristics before and after irradiation show that the current gain of the devices starts degrading after a helium fluence of 1 x 10(14) cm(-2) and decreases up to 20% for the highest fluence of ions. Simulations show that the helium ions induce ionization inside the SiO2, which increases the interface charge and leads to a degradation of the BJT performance. Thermal annealing of the irradiated devices at 300 degrees C, 420 degrees C, and 500 degrees C further increases the amount of charge at the interface, resulting in increased base current in the low-voltage range.

  • 58.
    Usman, Muhammad
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Nawaz, M.
    Hallén, Anders
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Position dependent traps and carrier compensation in 4H-SiC bipolar junction transistorsInngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646Artikkel i tidsskrift (Annet vitenskapelig)
  • 59. Venica, Stefano
    et al.
    Driussi, Francesco
    Palestri, Pierpaolo
    Esseni, David
    Vaziri, Sam
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Selmi, Luca
    Simulation of DC and RF Performance of the Graphene Base Transistor2014Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 61, nr 7, s. 2570-2576Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    We examined the DC and RF performance of the graphene base transistor (GBT) in the ideal limit of unity common base current gain. To this purpose, we developed a model to calculate the current-voltage characteristics of GBTs with semiconductor or metal emitter taking into account space charge effects in the emitter-base and base-collector dielectrics that distort the potential profile and limit the upper value of f(T). Model predictions are compared with available experiments. We show that, in spite of space charge high current effects, optimized GBT designs still hold the promise to achieve intrinsic cutoff frequency in the terahertz region, provided that an appropriate set of dielectric and emitter materials is chosen.

  • 60. Venica, Stefano
    et al.
    Driussi, Francesco
    Vaziri, Sam
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Palestri, Pierpaolo
    Selmi, Luca
    Graphene Base Transistors With Bilayer Tunnel Barriers: Performance Evaluation and Design Guidelines2017Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, nr 2, s. 593-598Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Graphene-based capacitors and Graphene base transistors (GBTs) featuring innovative engineered tunnel barriers are characterized in DC and the data are thoroughly analyzed by means of an electrical model and a Monte Carlo transport simulator. Followingmodel calibra-tion on experiments, we then propose strategies to improve the DC common-base current gain and the cutoff frequency of GBTs. The DC and RF performance of optimized GBT structures based on realistic technology data are analyzed in detail to highlight advantages and potential limits of this device concept.

  • 61.
    Visciarelli, Michele
    et al.
    KTH, Skolan för teknikvetenskap (SCI), Tillämpad fysik.
    Gnani, Elena
    Gnudi, Antonio
    Reggiani, Susanna
    Baccarani, Giorgio
    Impact of Traps and Strain on Optimized n- and p-Type TFETs Integrated on the Same InAs/AlGaSb Technology Platform2017Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, nr 8, s. 3108-3113Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    A simulation study on the impact of interface traps and strain on the I -V characteristics of co-optimized p-and n-type tunnel FETs (TFETs) realized on the same InAs/Al0.05Ga0.95Sb technology platform is carried out, using a full-quantum ballistic simulator. In order to capture the effect of interface/border traps on the device electrostatics consistently with carrier degeneracy and ballistic transport, the classical Shockley-Read-Hall theory has been properly generalized. The effect of an experimental Dit distribution of a high-k gate stacks on InAs has been investigated. Unfortunately, traps induce a significant reduction of the ON-state current. However, it turns out that localized strain at the source/channel heterojunction caused by lattice mismatch is able to induce for the n-type TFET, a performance enhancement with respect to the ideal device even in the presence of traps. On the contrary, for the p-type one, a current degradation similar or equal to 18% is observed.

  • 62.
    von Haartman, Martin
    et al.
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Lindgren, Ann-Cathrin
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Hellström, Per-Erik
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Malm, Gunnar
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Zhang, Shi-Li
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Östling, Mikael
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    1/f noise in Si and Si0.7Ge0.3 pMOSFETs2003Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 50, s. 2513-2519Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Strained layer Si0.7Ge0.3 pMOSFETs were fabricated and shown to exhibit enhanced hole mobility, up to 35% higher for a SiGe device with 3-nm-thick Si-cap, and lower 1/f noise compared to Si surface channel pMOSFETs. The 1/f noise in the investigated devices was dominated by mobility fluctuation noise and found to be lower in the SiGe devices. The source of the mobility fluctuations was determined by investigating the electric field dependence of the 1/f noise. It was found that the SiO2/Si interface roughness scattering plays an important role for the mobility fluctuation noise, although not dominating the effective mobility. The physical separation of the carriers from the SiO2/Si interface in the buried SiGe channel pMOSFETs resulted in lower SiO2/Si interface roughness scattering, which explains the reduction of 1/f noise in these devices. The 1/f noise mechanism was experimentally verified by studying 1/f noise in SiGe devices with various thicknesses of the Si-cap. A too large Si-cap thickness led to a deteriorated carrier confinement in the SiGe channel resulting in that considerable 1/f noise was generated in the parasitic current in the Si-cap. In our experiments, the SiGe devices with a Si-cap thickness in the middle of the interval 3-7 nm exhibited the lowest 1/f noise.

  • 63.
    von Haartman, Martin
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Malm, Gunnar
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Östling, Mikael
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Comprehensive study on low-frequency noise and mobility in Si and SiGe pMOSFETs with high-κ gate dielectrics and TiN gate2006Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 53, nr 4, s. 836-846Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Low-frequency noise and hole mobility are studied in Si and SiGe surface channel pMOSFETs with various types of high-kappa dielectric stacks (Al2O3, Al2O3/HfAlOx/Al2O3 and Al2O3/HfO2/Al2O3) and TiN as gate electrode material. Comparisons are made with poly-SiGe-gated pMOSFETs as well as P0lY-Si/SiO2/Si references. The choice of channel material (strained SiGe or Si), gate material (TiN or poly-SiGe), and high-kappa material (Al2O3, HfO2, HfAlOx) is discussed in terms of mobility and low-frequency noise. A TiN gate in combination with a surface SiGe channel is advantageous both for enhanced mobility and low 1/f noise. The dominant sources of carrier scattering are identified by analyzing the mobility measured at elevated temperatures. The 1/f noise is studied from subthreshold to strong inversion conditions and at different substrate biases. The mobility fluctuation noise model and the number fluctuation noise model are both used to investigate the 1/f-noise origin.

  • 64. Wang, A Z H
    et al.
    Zhao, B
    Hutchby, J A
    Östling, Mikael
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Sun, S C
    Special issue on integrated circuits technologies for RF circuit applications2005Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 52, nr 7, s. 1231-1234Artikkel i tidsskrift (Annet vitenskapelig)
  • 65. Wang, Jian
    et al.
    Chen, Zhe
    Guo, Jinhong
    Li, Yubai
    Lu, Zhonghai
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System.
    ACO-Based Thermal-Aware Thread-to-Core Mapping for Dark-Silicon-Constrained CMPs2017Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, nr 3, s. 930-937Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The limitation on thermal budget in chip multiprocessor (CMP) results in a fraction of inactive silicon regions called dark silicon, which significantly impacts the system performance. In this paper, we propose a thread-to-core mapping method for dark-silicon-constrainedCMPs to address their thermal issue. We first propose a thermal predictionmodel to forecast CMP temperature after the CMP executes a forthcoming application. Then, we develop an ant colony optimization-based algorithm to conduct the thread-to- core mapping process, such that the CMP peak temperature is minimized and, consequently, the probability of triggering CMP dynamic thermal management is decreased. Finally, we evaluate our method and compare it with the baseline (a standard Linux scheduler) and other existing methods (NoC-Sprinting, DaSiM mapping, and TP mapping). The simulation results show that our method gains good thermal profile and computational performance, and performs well with chip scaling. Specifically, it eliminates all thermal emergency time, outperforming all other methods, and gains million instructions per second improvement up to 12.9% against the baseline.

  • 66. Wang, Jian
    et al.
    Lu, Zhonghai
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System.
    Li, Yubai
    Fu, Yusheng
    Guo, Jinhong
    A High-Level Thermal Model-Based Task Mapping for CMPs in Dark-Silicon Era2016Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 63, nr 9, s. 3406-3412Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The chip multiprocessor (CMP) thermal issue impacting the system reliability and cooling cost has become a limiting factor for chip scaling and attracted growing attentions in the dark-silicon era. We propose a thermal-aware thread-to-core mapping method for CMPs under the dark-silicon constraint. We first propose a high-level spatial-temporal information-based thermal model to capture the relationship between the mapping result and the system thermal distribution. Then, we develop a thermal-aware mapping algorithm, which can automatically assign threads to proper cores based on the proposed model. Finally, we evaluate our method through simulations. Compared with three other mapping methods, namely, random, network-on-chip (NoC)-sprinting and round-robin, our thermal-priority design decreases the peak temperature by up to 4.31 K while showing good communication performance (34.7% of improvement against random and 50.3% against NoC sprinting, and only 6.3% of degradation against round robin); and our latency-priority design achieves the best communication performance with an improvement up to 62.6% and a satisfactory thermal profile.

  • 67. Wang, Xiaolei
    et al.
    Xiang, Jinjuan
    Han, Kai
    Wang, Shengkai
    Luo, Jun
    Zhao, Chao
    Ye, Tianchun
    Radamson, Henry H.
    KTH.
    Simoen, Eddy
    Wang, Wenwu
    Physically Based Evaluation of Effect of Buried Oxide on Surface Roughness Scattering Limited Hole Mobility in Ultrathin GeOI MOSFETs2017Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 64, nr 6, s. 2611-2616Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper presents a numerical simulation study investigating the effect of buried oxide on surface roughness scattering limited hole mobility (mu(SR)) in ultrathin germanium-on-insulator (GeOI) MOSFETs, for the first time. The simulation considers wave function penetration at channel/oxide interface and nonlinear dependence of scattering matrix element on surface fluctuation. Three types of buried oxide materials are compared (GeO2, SiO2, and Si3N4). The mu(SR) increases in the order of SiO2 < GeO2 < Si3N4. This dependence of mu(SR) on buried oxide material is due to surface fluctuation scattering from backside Ge/buried oxide interface. Our simulation results show that Si3N4 and GeO2 are beneficial as buried oxide for mobility enhancement in GeOI MOSFETs, compared with conventional SiO2 as buried oxide. Our findings provide an insight into further improving mobility characteristic.

  • 68.
    Yang, Kunlong
    et al.
    KTH, Skolan för kemi, bioteknologi och hälsa (CBH). KTH, Skolan för elektroteknik och datavetenskap (EECS).
    Yuan, Sijian
    Fudan University, SIST, State Key Laboratory of ASIC and System.
    Zhan, Yiqiang
    Fudan University, SIST, State Key Laboratory of ASIC and System.
    Zheng, Lirong
    KTH, Skolan för elektroteknik och datavetenskap (EECS). Fudan University, SIST, State Key Laboratory of ASIC and System.
    Seoane, Fernando
    KTH, Skolan för kemi, bioteknologi och hälsa (CBH). Karolinska Institutet, Department for Clinical Science, Intervention and Technology .
    Voltage dependency of photoelectrical memory in photoelectrical artificial synapseInngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646Artikkel i tidsskrift (Annet vitenskapelig)
    Abstract [en]

    Recently, the newly reported photoelectrical artificial synapses have attracted a lot of intentions because of their light-memory function provided them great potential in using as a building block of new neuromorphic systems. By now, most of those devices were achieved based on the photoelectrical field effect transistors with persistent photoconductivity (PPC) effect. But the real application of these devices needs comprehensive understanding of their mechanism and the influence factors, which was rare. We here focused on the relationship of the photoelectrical response and the gate voltage, and did both experimental and theoretical investigations. A model based on indirect recombination was proposed to explain the observed phenomenon. Simulations using this model got consistent results as the experiments. Moreover, the voltage influence on specific performance metrics of the photoelectrical artificial synapses was discussed to provide direction in the practical applications.

  • 69. Zhang, Min
    et al.
    Knoch, Joachim
    Zhang, Shi-Li
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Integrerade komponenter och kretsar.
    Feste, Sebastian
    Schroeter, Michael
    Mantl, Siegfried
    Threshold voltage variation in SOI Schottky-barrier MOSFETs2008Inngår i: IEEE Transactions on Electron Devices, ISSN 0018-9383, E-ISSN 1557-9646, Vol. 55, nr 3, s. 858-865Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    The inhomogeneity of Schottky-barrier (SB) height Phi(B) is found to strongly affect the threshold voltage V-th Of SB-MOSFETs fabricated in ultrathin body silicon-on-insulator (SOI). The magnitude of this influence is dependent on gate oxide thickness t(ox) and SOI body thickness t(si); the contribution of inhomogeneity to the V-th variation becomes less pronounced with smaller t(ox) and/or larger t(si). Moreover, an enhanced V-th variation is observed for devices with dopant segregation used for reduction of the effective Phi(B). Furthermore, a multigate structure is found to help suppress the V-th variation by improving carrier injection through reduction of its sensitivity to the Phi(B) inhomogeneity. A new method for extraction of Phi(B) from room temperature transfer characteristics is also presented.

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