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  • 51.
    Baghaei Nejad, Majid
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Zou, Zhuo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    A novel passive tag with asymmetric wireless link for RFID and WSN applications2007Inngår i: 2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS: VOLS 1-11, 2007, s. 1593-1596Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, we present a radio-powered module with asymmetric wireless link utilizing ultra wideband radio system for RFID and wireless sensor applications. Our contribution includes using two different standards in uplink and downlink. Such as conventional RFIDs, incoming RF signal transmitted by reader is used to power the internal circuitry and receive the data. However, in upstream link, an IR-UWB transmitter is utilized. Unlike traditional RFID systems, due to great advantages of UWB communication, this tag is very robust to multi-path fading and collision problem and it is more secure against eavesdropping or jamming. The module consists of a power scavenging unit, a RF receiver, an IR-UWB transmitter, digital baseband controller, and an embedded UWB antenna are designed for integration on Liquid-Crystal Polymer (LCP) substrate, using 0.18um CMOS process technology.

  • 52.
    Baghaei-Nejad, Majid
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Power management and clock generator for a novel passive UWB tag2007Inngår i: 2007 International Symposium On System-On-Chip Proceedings / [ed] Nurmi, J; Takala, J; Vainio, O, 2007, s. 82-85Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper we present a power management and a clock generator for a novel passive UWB tag. It can be used in many applications such as Radio Frequency Identification (RFID), and ubiquitous wireless sensing. As same as conventional RFID, the tag captures the power from the incoming RF signal, converts to DC and stores it in a relatively big capacitor. A voltage sensor and a regulator provide stable voltage for the whole circuitry during operation mode. A clock circuitry generates a low jitter and low skew clock for ultra wideband transmitter to transmit data. In such passive system the power consumption of each block should be as low as possible. On the other hand, performance degradation across process, voltage, and temperature variation (PVT) is another problematic challenge in low power and low cost circuit implementation. In this work, the power management unit including of an RF power scavenging, a voltage sensor, a low drop out regulator and a clock generator are designed and their performance across PVT variation are analyzed. The module is designed and is fabricated in CMOS 0.18 mu m technology.

  • 53. Bao, D.
    et al.
    Zou, Zhuo
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Huan, Y.
    Zhai, Chuanying
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Bagaian, T.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Källbäck, B.
    Zheng, Lirong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. State Key Laboratory of ASIC and System, Fudan University, Shanghai, China .
    A smart catheter system for minimally invasive brain monitoring2015Inngår i: Proceedings of the International Conference on Biomedical Electronics and Devices, SciTePress, 2015, s. 198-203Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper demonstrates a smart catheter system with intracranial pressure (ICP) and temperature sensing capability which is designed for real-time monitoring in traumatic brain injury (TBI) therapy. It uses a single flexible catheter with a 1 mm (3 Fr) diameter that integrates electrodes and sophisticated silicon chip on flexible substrates, enabling multimodality monitoring of physiological signals. A micro-electromechanical-system (MEMS) catheter pressure sensor is mounted on the distal end. It can be used for detecting both pressure and temperature by different switch configurations, which minimizes the size of catheter and reduces the cost. The interconnects (signalling conductors) are printed on a bio-compatible flexible substrate, and the sensor is interfaced with an embedded electronic system at the far-end. The electronic system consists of analog front end with analog-to-digital converter (ADC), a microcontroller, and data interface to the hospital infrastructure with a graphical user interface (GUI). The overall smart catheter system achieves a pressure sensing root mean square error (RMSE) of ±1.5 mmHg measured from 20 mmHg to 300 mmHg above 1 atm and a temperature sensing RMSE of ±0.08°C measured from 32°C to 42°C. The sampling rate can be up to 10S/s. The in vivo performance is demonstrated in laboratory animals.

  • 54. Ben Dhaou, I.
    et al.
    Gia, T. N.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Low-latency hardware architecture for cipher-based message authentication code2017Inngår i: 2017 IEEE International Symposium on Circuits and Systems (ISCAS), Institute of Electrical and Electronics Engineers (IEEE), 2017, artikkel-id 8050840Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Cipher-based message authentication code, CMAC, is a NIST approved standard for checking message integrity and authentication. This work presents a low-latency AES architecture for CMAC. The architecture uses intensive parallel processing per round and takes advantage of the BRAM present in modern FPGA. Experimental results show that for typical IoT application, the proposed architecture has a latency of 10 clock cycles, consumes 1355 slices, 2 BRAMs and achieves a throughput of 3.8Gbps.

  • 55. Ben Dhaou, I.
    et al.
    Ismail, Mohammed
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Current mode, low-power, on-chip signaling in deep-submicron CMOS technology2003Inngår i: IEEE Transactions on Circuits And Systems Part I: Fundamental Theory and Applications, ISSN 1057-7122, E-ISSN 1558-1268, Vol. 50, nr 3, s. 397-406Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    qThis paper reports an analogy between on-chip signaling and digital communication over a band-limited channel. This analogy has been used to design a scheme for low-power, on-chip signaling, robustly resistant to power-supply noise. The technique uses multilevel, current-mode signaling as its core. The number of levels is determined by estimating the bandwidth of the wire. A closed-form expression has been presented here describing the bandwidth of a wire modeled as a first-order RLC circuit. An algorithm is presented for computing the levels of the current given target bit rate, bit-error rate, and wire characteristics. Simulation results using HSPICE from Avant! show that the algorithm for computing the wire bandwidth presented here has an average error of less than 10% Experimental results on a set of benchmark signaling problems implemented in a 0.25-mum 2.5-V CMOS process, show that using four levels of current instead of the standard two levels allows a twofold reduction in the power and a reduction of 1.4 times the area.

  • 56. Ben Dhaou, I.
    et al.
    Kondoro, Aron
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik. University of Dar es Salaam, Tanzania.
    Kelati, Amleset
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik, Elektronik och inbyggda system. University of Turku, Finland.
    Rwegasira, Diana
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik. University of Turku, Finland.
    Naiman, S.
    Mvungi, N. H.
    Tenhunen, Hannu
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik.
    Communication and security technologies for smart grid2018Inngår i: Fog Computing: Breakthroughs in Research and Practice, IGI Global , 2018, s. 305-331Kapittel i bok, del av antologi (Annet vitenskapelig)
    Abstract [en]

    The smart grid is a new paradigm that aims to modernize the legacy power grid. It is based on the integration of ICT technologies, embedded system, sensors, renewable energy and advanced algorithms for management and optimization. The smart grid is a system of systems in which communication technology plays a vital role. Safe operations of the smart grid need a careful design of the communication protocols, cryptographic schemes, and computing technology. In this article, the authors describe current communication technologies, recently proposed algorithms, protocols, and architectures for securing smart grid communication network. They analyzed in a unifying approach the three principles pillars of smart-gird: Sensors, communication technologies, and security. Finally, the authors elaborate open issues in the smart-grid communication network.

  • 57. Ben Dhaou, I.
    et al.
    Parhi, K. K.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Energy efficient signaling in deep-submicron technology2002Inngår i: VLSI design (Print), ISSN 1065-514X, E-ISSN 1563-5171, Vol. 15, nr 3, s. 563-586Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In deep-submicron technology, global interconnect capacitances have started reaching several orders of magnitude greater than the intrinsic capacitances of the CMOS gates. The dynamic power consumption of a CMOS gate driving a global wire is the sum of the power dissipated due to (dis)charging (i) the intrinsic capacitance of the gate, and (ii) the wire capacitance. The latter is referred to as on-chip signaling power consumption. In this paper, a scheme has been proposed for combating crosstalk noise and reducing power consumption while driving the global wire at an optimal delay. This scheme is based on reduced voltage-swing signaling combined with buffer-insertion and resizing. The buffers are inserted and resized to compensate for the speed degradation caused by scaling the supply voltage and eradicating the crosstalk noise. A new buffer insertion algorithm called VIJIM has been described here, along with accurate delay and crosstalk-noise estimation algorithms for distributed RLC wires. The experimental results show that the VIJIM algorithm inserts fewer buffers into non-critical nets than does the existing buffer-insertion algorithms. In a 0.25 mm CMOS process, the experimental results show that energy savings of over 60% can be achived if the supply voltage is reduced from 2.5 to 1.5 V.

  • 58. Ben Dhaou, I.
    et al.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Efficient library characterization for high-level power estimation2004Inngår i: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 12, nr 6, s. 657-661Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    This paper describes LP-DSM, which is an algorithm used for efficient library characterization in high-level power estimation. LP-DSM characterizes the power consumption of building blocks using the entropy of primary inputs and primary outputs. The experimental results showed that over a wide range of benchmark circuits implemented using full custom design in 0.35-mum 3.3 V CMOS process the statistical performance (mean and maximum error) of LP-DSM is comparable or sometimes better than most of the published algorithms. Moreover, it was found that LP-DSM has the lowest prediction sum of squares, which makes it an efficient tool for power prediction. Furthermore, the complexity of the LP-DSM is linear in relation to the number of primary inputs (O(NI)), whereas state of the art published library characterization algorithms have a complexity of O(NI2).

  • 59.
    Ben Dhaou, Imed
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Comparison of OFDM and WPM for fourth generation broadband WLAN2000Inngår i: European Signal Processing Conference, 2000, nr MarchKonferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, we propose a qualitative comparison between OFDM (Orthogonal Frequency Division Multiplexing), and WPM (Wavelet Packet Modulation). The comparison is done for two separate cases. Firstly, the efficiency of the two signaling systems will be compared. Secondly, the requirements for hardware implementation will be performed. From the performance and the VLSI implementation viewpoint, we found that WPM outperforms OFDM. However, the out-of-band radiation and peak-to-average-power for the case of OFDM is better compared to the WPM. The extensive simulation results, show that the average increase of peak-to-average-power is approximately 0.98dB compared to the OFDM. The increase of the adjacent channel power ratio channel is approximately 12.41dBc compared to the OFDM.

  • 60.
    Chen, Jian
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Zhou, Dian
    Fudan University.
    Sizing of MOS device in LC-tank oscillators2007Inngår i: 2007 Norchip, 2007, s. 90-95Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Since previous publications show conflicting results about sizing device, relationship between device size and 1/f(2) phase noise is studied and closed-form equations are derived in order to help designers to size devices in LC-tank oscillators for good phase noise performance. The analysis is divided into two steps. Firstly, periodic noise transfer functions of each VCO noise source to the output of switch FETs are derived, and the impact of sizing on these functions is discussed. Secondly, phase noise equations are derived with these functions. Experiments show that phase noise predicted by the equations agrees with that from simulations.

  • 61.
    Daneshtalab, M.
    et al.
    University of Turku, Finland.
    Ebrahimi, M.
    University of Turku, Finland.
    Liljeberg, P.
    University of Turku, Finland.
    Plosila, J.
    University of Turku, Finland.
    Tenhunen, Hannu
    University of Turku, Finland.
    A Low-Latency and Memory-Efficient On-chip Network2010Inngår i: NOCS 2010: The 4th ACM/IEEE International Symposium on Networks-on-Chip, 2010, s. 99-106, artikkel-id 5507556Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Using multiple SDRAMs in MPSoCs and NoCs to increase memory parallelism is very common nowadays. In-order delivery, resource utilization, and latency are the most critical issues in such architectures. In this paper, we present a novel network interface architecture to cope with these issues efficiently. The proposed network interface exploits a resourceful reordering mechanism to handle the in-order delivery and to increase the resource utilization. A brilliant memory controller is efficiently integrated into this network interface to improve the memory utilization and reduce both memory and network latencies. In addition, to bring compatibility with existing IP cores the proposed network interface utilizes AXI transaction based protocol. Experimental results with synthetic test cases demonstrate that the proposed architecture gives significant improvements in average network latency (12%), average memory access latency (19%), and average memory utilization (22%).

  • 62. Daneshtalab, M.
    et al.
    Ebrahimi, M.
    Liljeberg, P.
    Plosila, J.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    CMIT: A novel cluster-based topology for 3D stacked architectures2010Inngår i: IEEE 3D System Integration Conference 2010, 3DIC 2010, 2010Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Combining the benefits of 3D IC and Network-on-Chip (NoC) schemes, provides a significant performance gain for 3D stacked architectures. In recent years, Through-Silicon-Via (TSV), employed for inter-layer connectivity (vertical channel), has attracted a lot of interest since it enables faster and more power efficient inter-layer communication across multiple stacked layers. However, the area overhead of TSVs reduces wafer utilization and yield which impact design of 3D architectures using a large number of TSVs. In this paper, we propose a novel stacked topology, named CMIT (Cluster Mesh Inter-layer Topology) for 3D architectures to reduce the area overhead of TSVs and power dissipation on each layer with minimal performance penalty. Experimental results with synthetic test cases demonstrate that the presented topology can save more than 75% of TSV area footprint and reduces more than 10% of power consumption with a negligible performance overhead.

  • 63. Daneshtalab, M.
    et al.
    Ebrahimi, M.
    Liljeberg, P.
    Plosila, J.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. University of Turku, Finland.
    High-performance on-chip network platform for memory-on-processor architectures2011Inngår i: 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2011 - Proceedings, 2011, artikkel-id 5981509Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Three Dimensional Integrated Circuits (3D ICs) are emerging to improve existing Two Dimensional (2D) designs by providing smaller chip areas, higher performance and lower power consumption. Stacking memory layers on top of a multiprocessor layer (logic layer) is a potential solution to reduce wire delay and increase the bandwidth. To fully employ this capability, an efficient on-chip communication platform is required to be integrated in the logic layer. In this paper, we present an on-chip network platform for the logic layer utilizing an efficient network interface to exploit the potential bandwidth of stacked memory-on-processor architectures. Experimental results demonstrate that the platform equipped with the presented network interface increases the performance considerably.

  • 64. Daneshtalab, M.
    et al.
    Ebrahimi, M.
    Liljeberg, P.
    Plosila, J.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. University of Turku, Finland.
    High-Performance TSV Architecture for 3-D ICs2010Inngår i: Proceedings - IEEE Annual Symposium on VLSI, ISVLSI 2010, 2010, s. 467-468, artikkel-id 5572813Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Three-dimensional integrated circuits (3-D ICs) outperform traditional planar ICs in terms of performance, packaging density, interconnection power consumption, and functionality. Since the performance of 3-D ICs employing Through Silicon Vias (TSVs) depends on vertical interlayer interconnects, in this paper we present a high-performance bus architecture for TSVs.

  • 65. Daneshtalab, M.
    et al.
    Ebrahimi, M.
    Liljeberg, P.
    Plosila, J.
    Tenhunen, Hannu
    Turku Centre for Computer Science (TUCS), Finland.
    Input-Output Selection Based Router for Networks-on-Chip2010Inngår i: IEEE Annual Symposium on VLSI, ISVLSI 2010, 2010, s. 92-97Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, we propose a novel on-chip router architecture for avoiding congested areas in regular twodimensional on-chip networks. This architecture takes advantage of an efficient adaptive routing model based on the Hamiltonian path for both the multicast and unicast traffic. The output selection of the proposed architecture is based on the congestion condition of neighboring routers and the input selection is based on the Weighted Round Robin mechanism which allows packets to be serviced from each input port according to its congestion level The simulation results show that in multicast, unicast, and mixed traffic profiles the proposed model has lower average delays and lower average and peak power compared to previously proposed models.

  • 66. Daneshtalab, M.
    et al.
    Ebrahimi, M.
    Liljeberg, P.
    Plosila, J.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Memory-Efficient On-Chip Network With Adaptive Interfaces2012Inngår i: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, ISSN 0278-0070, E-ISSN 1937-4151, Vol. 31, nr 1, s. 146-159Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    To achieve higher memory bandwidth in network-based multiprocessor architectures, multiple dynamic random access memories can be accessed simultaneously. In such architectures, not only resource utilization and latency are the critical issues but also a reordering mechanism is required to deliver the response transactions of concurrent memory accesses in-order. In this paper, we present a memory-efficient on-chip network architecture to cope with these issues efficiently. Each node of the network is equipped with a novel network interface (NI) to deal with out-of-order delivery, and a priority-based router to decrease the network latency. The proposed NI exploits a streamlined reordering mechanism to handle the in-order delivery and utilizes the advance extensible interface transaction-based protocol to maintain compatibility with existing intellectual property cores. To improve the memory utilization and reduce the memory latency, an optimized memory controller is integrated in the presented NI. Experimental results with synthetic test cases demonstrate that the proposed on-chip network architecture provides significant improvements in average network latency (16%), average memory access latency (19%), and average memory utilization (22%).

  • 67. Daneshtalab, M.
    et al.
    Ebrahimi, M.
    Liljeberg, P.
    Plosila, J.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. University of Turku, Finland.
    Pipeline-based interlayer bus structure for 3D networks-on-chip2010Inngår i: Proceedings - 15th CSI International Symposium on Computer Architecture and Digital Systems, CADS 2010, 2010, s. 35-41, artikkel-id 5623524Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The structure of direct vertical interconnections, called Through Silicon Vias (TSVs), is an important issue in the realm of 3D ICs. The bus-based and network-based structures are the two dominant architectures for implementing TSVs as interlayer connection in 3D ICs. Both implementations have some disadvantages. The former suffers from poor scalability and deteriorates the performance at high injection rates, and the latter consumes more area and power dissipation. In this paper, we propose a novel pipeline bus structure for TSVs to improve the performance of the prior bus-based architecture. The presented structure can utilize bi-synchronous FIFO for synchronization between stacked layers if each layer is fabricated by different technologies. Experimental results with synthetic test cases demonstrate that the proposed architecture gives significant improvements in average network latency. Also, the hardware area and power consumption of the presented bus structure are 9% and 11% less than the typical bus structure of TSVs, respectively.

  • 68.
    Daneshtalab, Masoud
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System.
    Mehdipour, Farhad
    Yu, Zhiyi
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    Special Issue on Emerging Many-Core Systems for Exascale Computing2015Inngår i: ACM Journal on Emerging Technologies in Computing Systems, ISSN 1550-4832, Vol. 11, nr 4, artikkel-id 39Artikkel i tidsskrift (Annet vitenskapelig)
  • 69. Dhaou, I. B.
    et al.
    Skhiri, H.
    Tenhunen, Hannu
    KTH, Skolan för elektroteknik och datavetenskap (EECS), Elektronik, Integrerade komponenter och kretsar.
    Study and implementation of a secure random number generator for DSRC devices2018Inngår i: 2017 9th IEEE-GCC Conference and Exhibition, GCCCE 2017, Institute of Electrical and Electronics Engineers Inc. , 2018Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This work presents an algorithm to select a low-cost modulus for the implementation of Blum Blum Shub pseudorandom number generator in an FPGA device. Additionally, it elaborates a low-latency architecture for the BBS algorithm suitable for the security service of the IEEE 1609.2 standard. The architecture uses diminished-1 arithmetic and is log2($N$) faster than previously reported implementation using Montgomery multiplier. The architecture is able to implement 224-bit and 256-bit BBS sequences. Synthesis results show that the latencies for the 224-bit and 256-bit BBS are, respectively, 1.12μs and 1.28μs.

  • 70. Dhaou, I. B.
    et al.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik, Integrerade komponenter och kretsar.
    Design techniques of 5G mobile devices in the dark silicon era2016Inngår i: 5G Mobile Communications, Springer International Publishing , 2016, s. 381-400Kapittel i bok, del av antologi (Annet vitenskapelig)
    Abstract [en]

    In the internet of things age, future communication technologies should provide the necessary bandwidth and latency for the connection of billion devices and the development of ubiquitous applications to improve the quality of life. The design of the prospected mobile communication system needs wide skills in wireless communication, analog circuit design, embedded system, microwave technology, and so forth. System level analyses, design space exploration, performance tradeoffs are some key steps that enable the design of low-cost, energy efficient, ubiquitous and flexible transceiver. This chapter provides comprehensive design techniques for 5G mobile communication in the dark silicon era and using More than Moore technology (MtM). 

  • 71.
    Dhaou, I. Ben
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Dubrova, Elena
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Power Efficient Inter-Mode Communication for Digit-Serial DSP Architectures in Deep-Submicron Technology2001Inngår i:  , 2001, s. 61-66Konferansepaper (Fagfellevurdert)
  • 72. Dielacher, Franz
    et al.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Special issue on the 2002 European Solid State Circuits Conference (Esscirc): Guest editorial2003Inngår i: IEEE Journal of Solid-State Circuits, ISSN 0018-9200, E-ISSN 1558-173X, Vol. 38, nr 7, s. 1095-1097Artikkel i tidsskrift (Fagfellevurdert)
  • 73.
    Dubrova, Elena
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    A Computational Scheme Based on Random Boolean Networks on the Critical Line2006Inngår i: International Symposium on Applied Computing (IADIS’2006), 2006, s. 273-281Konferansepaper (Fagfellevurdert)
  • 74.
    Dubrova, Elena
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Teslenko, Maxim
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    A Computational Model Based on Random Boolean Networks2007Inngår i: 2007 2ND BIO-INSPIRED MODELS OF NETWORKS, INFORMATION AND COMPUTING SYSTEMS (BIONETICS), NEW YORK: IEEE , 2007, s. 24-31Konferansepaper (Fagfellevurdert)
    Abstract [en]

    For decades, the size of silicon CMOS transistors has decreased steadily while their performance has improved. As the devices approach their physical limits, the need for alternative materials, structures and computation schemes becomes evident. This paper considers a computation scheme based on an abstract model of gene regulatory networks called Random Boolean Networks. Our interest in Random Boolean Networks is due to their attractive fault-tolerant features. The parameters of a network can be tuned so that it exhibits a robust behavior in which minimal changes in network's connections, values of state variables, or associated functions, typically cause no variation in the network's dynamics. A computation scheme based on random networks also seems to be appealing for emerging technologies in which it is difficult to control the growth direction or precise alignment, e.g. carbon nanotubes.

  • 75.
    Dubrova, Elena
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Teslenko, Maxim
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    A Computational Scheme Based on Random Boolean Networks2008Inngår i: TRANSACTIONS ON COMPUTATIONAL SYSTEMS BIOLOGY X / [ed] Priami C; Akan OB; Dressler F; Ngom A, 2008, Vol. 5410, s. 41-58Konferansepaper (Fagfellevurdert)
    Abstract [en]

    For decades, the size of silicon CMOS transistors has decreased steadily while their performance has improved. As the devices approach their physical limits, the need for alternative materials, structures and computational schemes becomes evident. This paper considers a computational scheme based oil ail abstract model of the gene regulatory network called Random Boolean Network (RBN). On one hand, our interest in RBNs is due to their attractive fault-tolerant features. The parameters of an RBN can be tuned so that it exhibits a robust behavior in which minimal changes in network's connections, values of state variables, or associated functions, typically cause no variation in the network's dynamics. On the other hand, a computational scheme based on RBNs seems appealing for emerging technologies in which it is difficult to control the growth direction or precise alignment, e.g, carbon nanotubes.

  • 76.
    Dubrova, Elena
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Teslenko, Maxim
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Computing attractors in complex dynamic networks2005Konferansepaper (Fagfellevurdert)
  • 77.
    Dubrova, Elena
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Teslenko, Maxim
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    On analysis and synthesis of (n, k)-Non-Linear Feedback Shift Registers2008Inngår i: 2008 Design, Automation And Test In Europe: Vols 1-3, 2008, s. 1128-1133Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Non-Linear Feedback Shift Registers (NLFSRs) have been proposed as an alternative to Linear Feedback Shift Registers (LFSRs) for generating pseudo-random sequences for stream ciphers. In this paper, we introduce (n, k)-NLFSRs which can be considered a generalization of the Galois type of LFSR. In an (n, k)-NLFSR, the feedback can be taken from any of the n bits, and the next state functions can be any Boolean function of up to k variables. Our motivation for considering this type NLFSRs is that their Galois configuration makes it possible to compute each next state function in parallel, thus increasing the speed of output sequence generation. Thus, for stream cipher application where the encryption speed is important, (n,k)-NLFSRs may be a better alternative than the traditional Fibonacci ones. We derive a number of properties of (n,k)NLFSRs. First, we demonstrate that they are capable of generating output sequences with good statistical properties which cannot be generated by the Fibonacci type of NLFSRs. Second, we show that the period of the output sequence of an (n, k)-NLFSR is not necessarily equal to the length of the largest cycle of its states. Third, we compute the period of an (n,k)-NLFSR constructed from several parallel NLFSRs whose outputs are XOR-ed and show how to maximize this period. We also present an algorithm for estimating the length of cycles of states of (n, k)-NLFSRs which uses Binary Decision Diagrams for representing the set of states and the transition relation on this set.

  • 78.
    Duo, Xinzhong
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Torikka, Tommi
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Zheng, Li-Rong
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Ismail, Mohammed
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    On-chip versus off-chip passives in multi-band radio design2004Inngår i: ESSCIRC 2004: PROCEEDINGS OF THE 30TH EUROPEAN SOLID-STATE CIRCUITS CONFERENCE / [ed] Steyaert, M; Claeys, CL, NEW YORK: IEEE , 2004, s. 327-330Konferansepaper (Fagfellevurdert)
    Abstract [en]

    This paper presents on-chip versus off-chip passives in multi-band radio design. The analysis is demonstrated through several multi-band low noise amplifiers designs in SiGe BiCMOS and GaAs PHEMT. Cost-performance trade-off analysis shows that when on-chip passives are moved off chip, performance of RF circuits is always improved. However, simple RF circuits do not show obvious cost-benefits, whereas complex RF circuits such as multi-band radio can have significant cost savings by using off-chip passives.

  • 79.
    Duo, Xinzhong
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Torikka, Tommi
    Zheng, Li-Rong
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Ismail, Muhammed
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tjukanoff, Esa
    A DC-13GHz LNA for UWB RFID applications2004Inngår i: 22ND NORCHIP CONFERENCE, PROCEEDINGS, 2004, s. 241-244Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, we present a 4-stage traveling wave lownoise amplifier for UWB RFID (ultra-wideband radiofrequency identification). This LNA covers a frequencyrange of DC - 13 CHz. The circuit is implemented with0.I5pm GaAs PHEMT chips embedded in flexible LCP(liquid crystal polymer) substrate. In the frequency range,the gain of the LNA is better than IO dB, fluctuation of thegain is less than 3dB, its noise figure is less than 4dB, SI 1and S22 are around -10 dB.

  • 80.
    Duo, Xinzhong
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Zheng, Li-Rong
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Ismail, Mohammed
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    On-chip versus off-chip passives analysis in radio and mixed-signal system-on-package design2004Inngår i: PROCEEDINGS OF THE SIXTH IEEE CPMT CONFERENCE ON HIGH DENSITY MICROSYSTEM DESIGN AND PACKAGING AND COMPONENT FAILURE ANALYSIS (HDP'04), NEW YORK: IEEE , 2004, s. 109-116Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Advances of VLSI and packaging technologies enable condensed integration of system level functions in a single module, known as SoC and SoP. In order to find a better solution between SoC and SoP, and eliminate constraints between chip and package, a complete solution is needed to co-design and co-optimize chip and package in a total design plan with precise trade-offs of on-chip versus off-chip passives. In this paper, we present a complete and systematic design methodology for RF SoP/SoC. This methodology includes early analysis and design implementation. This early analysis is to estimate the performance and cost of each solution quickly and quantitively. Then, the best solution is found and implemented. For a better presentation, the method and design techniques are demonstrated through the design of a common emitter low noise amplifier (LNA) for 5GHz wireless LAN (local area network). Analytical equations of noise figure and transducer gain for the LNA with lossy package are also developed.

  • 81.
    Duo, Xinzhong
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Zheng, Li-Rong
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Ismail, Muhammad
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    On-chip versus Off-chip Passives Trade-offs in Radio and Mixed-Signal System-on- PackageManuskript (preprint) (Annet vitenskapelig)
  • 82.
    Duo, Xinzhong
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Ismail, Muhammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik- och datorsystem, ECS.
    A concurrent multi-band LNA for multi-standard radios2005Inngår i: 2005 IEEE International Symposium On Circuits And Systems (ISCAS), Conference Proceedings, IEEE , 2005, s. 3982-3985Konferansepaper (Fagfellevurdert)
    Abstract [en]

    A source-degenerated cascade LNA, which works at 2.4GHz and 5.8GHz simultaneously, is designed for Bluetooth and IEEE wireless LAN 802.11 a/b/g receivers. In this design, 0.15 mu m GaAs PHEMT technology and embedded passives in MCM-D substrate are implemented. At 2.4GHz and 5.8GHz, this LNA provides 12.2dB and 15.3dB gain, respectively. Noise figures of the LNA are 0.53dB and 1.43dB, respectively. Good input matching and output matching are also achieved-S11 and S22 at both frequencies are less than -10dB.

  • 83.
    Duo, Xinzhong
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Zheng, Li-Rong
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Ismail, Muhammed
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Analysis of lossy packaging parasitics for common emitter LNA in system-on-package2004Inngår i: ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, NEW YORK: IEEE , 2004, s. 75-78Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Advances of VLSI and packaging technologies enable condensed integration of an RF system in a single module, known as SoC and SoP. In order to find a better solution between SoC and SoP for RF systems and their sub-systems, it is needed to predict and estimate performance of each solution. In this paper, analytical equations for noise figure and gain of inductively degenerated common-emitter low-noise amplifiers in SoP/SoC are deduced as functions of passives and packaging parasitics. They hence enable designers to evaluate overall performance of each solution quantitatively. As well, influence of lossy packaging parasitics on LNA is also analyzed.

  • 84.
    Duo, Xinzhong
    et al.
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Zheng, Li-Rong
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Ismail, Muhammed
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Mikroelektronik och Informationsteknik, IMIT.
    Broadband CMOS LNAs for IR-UWB receiver2005Inngår i: Norchip 2005, Proceedings, New York: IEEE , 2005, s. 273-276Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Two single-ended wideband LNAs for Ultrawide-band receiver have been designed and implemented in 0.18 mu m CMOS technology. The first one, a feed-back LNA, is a two-stage amplifier with a improved feedback loop, which provides high gain and enables the input port to match with 500 in a wide frequency range from 500MHz to 8GHz. The second one, an LC low-pass-filter matched LNA, employs a third-order low pass filter in the input port to match a frequency range from 3GHz to 8GHz. In both of the LNAs, the input stage is a common source amplifier. Inductive shunt peaking is used for maximizing the bandwidth and flatting the gain. In the feed-back LNA, measurements show that the maximum gain is 11.5dB, the 3-dB; bandwidth is from 500MHz to 7GHz, IIP3 is -2.2dBm at 4GHz, the minimum noise figure is around 5.7dB, S11 is less than 8.2dB, and the power consumption is 14mW. In the LC filter matched LNA, the 3-dB bandwidth is from 3GHz to 7.3GHz. The maximum gain is 9.6dB, IIP3 is 0dBm at 4 GHz, the minimum noise figure is 7.6dB, S11 is less than -13.4dB and the power consumption is 23mW.

  • 85.
    Duo, Xinzhong
    et al.
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Zheng, Li-Rong
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    Tenhunen, Hannu
    KTH, Tidigare Institutioner, Elektroniksystemkonstruktion.
    RF robustness enhancement through statistical analysis of chip-package co-design2004Inngår i: 2004 IEEE International Symposium on Cirquits and Systems - Proceedings, IEEE , 2004, s. 988-991Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In order to enhance robustness of RF circuits, a flow of statistical analysis for chip-package co-design of RF system-on-package (SoP) is presented in this work. Methods for improving the yield of RF modules are developed. On-chip passive components versus off-chip passive components trade-offs in SoP module were also analyzed in terms of performance and yield. The design methods were demonstrated through case studies of LNA (low noise amplifier) in SoP.

  • 86.
    Duo, Xinzhong
    et al.
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Zheng, Li-Rong
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Tenhunen, Hannu R.
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    A study of packaging Requirements Multi-Band/Multi-Standard Wireless Chips2002Inngår i: Proc. IEEE 20th Norship Conference, 2002, s. 285-290Konferansepaper (Fagfellevurdert)
  • 87.
    Duo, Xinzhong
    et al.
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Zheng, Li-Rong
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Tenhunen, Hannu R.
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Chip-package co-design of common emitter LNA in system-on-package with on-chip versus off-chip passive component analysis2003Inngår i: ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, NEW YORK: IEEE , 2003, s. 55-58Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, we present common emitter LNAs (low noise amplifiers) in system-on-package for 5GHz WLAN application. Innovation of this module is that it is chip-package co-designed and co-simulated with performance trade-offs for on-chip versus off-chip passive component integration. It thus provides an optimal total solution for embedded RF electronics in system-level integration. Analytical equations for key performance parameters, noise figure and gain, of these LNAs are developed as functions of quality factors of passive components and the package parasitics. They hence provide designers a quantitative trade-off for on-chip versus off-chip passive components integration in SoP design. The final module is composed of on-chip active components in 0.5mum SiGe BiCMOS technology and off-chip passive components integrated in MCM-D substrate. Significant improvement in performance is found in these co-designed LNAs than those in single-chip LNAs.

  • 88.
    Duo, Xinzhong
    et al.
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Zheng, Li-Rong
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Tenhunen, Hannu R.
    KTH, Tidigare Institutioner, Mikroelektronik och informationsteknik, IMIT.
    Modeling and simulation of spiral inductors in wafer level packaged RF/wireless chips2003Inngår i: Analog Integrated Circuits and Signal Processing, ISSN 0925-1030, E-ISSN 1573-1979, Vol. 34, nr 1, s. 39-47Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    In this paper, embedded rectangular spiral inductors on Wafer-Level Packaged (WLP) RF/wireless chips were studied with 3D (three-dimensional) EM (electromagnetic) simulations. The performance of spiral inductors fabricated with various geometrical and technological parameters was analyzed. It is shown that Q (the quality factor) and f(res) (the self-resonance frequency) could be improved by using the thick insulator layer and thick/wide metal line, which are fabricated by WLP technology. The value of Q could be over 60 at 20 GHz for such embedded components, attesting a significant improvement compared to the conventional on-chip counterparts in CMOS. Through this study, optimal structures for such components are identified and guidelines for design and fabrications are derived. Finally, a method to estimate the inductance of rectangle spiral inductors is developed. It is useful to determine the approximate structure of an inductor quickly before detailed 3D EM simulation, which may cost a long time.

  • 89.
    Duo, Xinzhong
    et al.
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Zheng, Li-Rong
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Tenhunen, Hannu R.
    KTH, Tidigare Institutioner                               , Mikroelektronik och informationsteknik, IMIT.
    Chen, Liu
    Zou, Gang
    Liu, Johan
    Design and implementation of a 5GHz RF receiver front-end in LCP based system-on-package module with embedded chip technology2003Inngår i: ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 2003, s. 51-54Konferansepaper (Fagfellevurdert)
    Abstract [en]

    In this paper, we present a receiver front-end for 5 GHz wireless LAN in novel LCP (liquid crystal polymer) based system-on-package module. The module is based on embedded chip technologies for system-on-package, which eliminates the constraints of off-chip pad drive capability and hence improves electrical performance. Furthermore, the novel LCP material shows excellent RF and microwave performance. The quality factors of key passive components such as inductors integrated in LCP substrate with thin film technologies is as high as 60. The insertion loss of the bandpass filter is 3dB. The conversion gain of the receiver front-end is 20 dB and occupies 8.7mm by 3.6mm area.

  • 90. Dytckov, S.
    et al.
    Purohit, S. S.
    Daneshtalab, Masoud
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System.
    Plosila, J.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik.
    Exploring NoC jitter effect on simulation of spiking neural networks2014Inngår i: Proceedings of the 2014 International Conference on High Performance Computing and Simulation, HPCS 2014, 2014, s. 693-696Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The major bottleneck in simulation of large-scale neural networks is the communication problem due to one-to-many neuron connectivity. Network-on-Chip concept has been proposed to address the problem. This work explores the drawback that is introduced by interconnection networks - a delay jitter. The preliminary experiment is held in the spiking neural network simulator introducing variable communicational delay to the simulation. The performance degradation is reported.

  • 91.
    Dytckov, Sergei
    et al.
    University of Turku, Finland.
    Daneshtalab, Masoud
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektronik och Inbyggda System. University of Turku, Finland.
    Ebrahimi, Masoumeh
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. University of Turku, Finland.
    Anwar, Hassan
    Ecole Polytechnique Montreal, Canada.
    Plosila, Juha
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Industriell och Medicinsk Elektronik. University of Turku, Finland.
    Efficient STDP Micro-Architecture for Silicon Spiking Neural Networks2014Inngår i: 2014 17TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD), 2014, s. 496-503Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Spiking neural networks (SNNs) are the closest approach to biological neurons in comparison with conventional artificial neural networks (ANN). SNNs are composed of neurons and synapses which are interconnected with a complex pattern. As communication in such massively parallel computational systems is getting critical, the network-on-chip (NoC) becomes a promising solution to provide a scalable and robust interconnection fabric. However, using NoC for large-scale SNNs arises a trade-off between scalability, throughput, neuron/router ratio (cluster size), and area overhead. In this paper, we tackle the trade-off using a clustering approach and try to optimize the synaptic resource utilization. An optimal cluster size can provide the lowest area overhead and power consumption. For the learning purposes, a phenomenon known as spike-timing-dependent plasticity (STDP) is utilized. The micro-architectures of the network, clusters, and the computational neurons are also described. The presented approach suggests a promising solution of integrating NoCs and STDP-based SNNs for the optimal performance based on the underlying application.

  • 92.
    Ebrahimi, M.
    et al.
    Turku Centre for Computer Science (TUCS).
    Daneshtalab, M.
    Turku Centre for Computer Science (TUCS).
    Farahnakian, F.
    Turku Centre for Computer Science (TUCS).
    Plosila, J.
    Turku Centre for Computer Science (TUCS).
    Liljeberg, P.
    Turku Centre for Computer Science (TUCS).
    Palesi, M.
    University of Kore.
    Tenhunen, Hannu
    HARAQ: Congestion-Aware Learning Model for Highly Adaptive Routing Algorithm in On-Chip Networks2012Inngår i: Proceedings of the 2012 6th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2012, 2012, s. 19-26Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The occurrence of congestion in on-chip networks can severely degrade the performance due to increased message latency. In mesh topology, minimal methods can propagate messages over two directions at each switch. When shortest paths are congested, sending more messages through them can deteriorate the congestion condition considerably. In this paper, we present an adaptive routing algorithm for on-chip networks that provide a wide range of alternative paths between each pair of source and destination switches. Initially, the algorithm determines all permitted turns in the network including 180-degree turns on a single channel without creating cycles. The implementation of the algorithm provides the best usage of all allowable turns to route messages more adaptively in the network. On top of that, for selecting a less congested path, an optimized and scalable learning method is utilized. The learning method is based on local and global congestion information and can estimate the latency from each output channel to the destination region.

  • 93.
    Ebrahimi, M.
    et al.
    Turku Centre for Computer Science (TUCS).
    Daneshtalab, M.
    Turku Centre for Computer Science (TUCS).
    Liljeberg, P.
    Turku Centre for Computer Science (TUCS).
    Plosila, J.
    Turku Centre for Computer Science (TUCS).
    Flich, J.
    Turku Centre for Computer Science (TUCS).
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem. KTH, Skolan för informations- och kommunikationsteknik (ICT), Centra, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Path-based Partitioning Methods for 3D Networks-on-Chip with Minimal Adaptive Routing2012Inngår i: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 99, s. 1-16Artikkel i tidsskrift (Fagfellevurdert)
    Abstract [en]

    Combining the benefits of 3D ICs and Networks-on-Chip (NoCs) schemes provides a significant performance gain for 3D architectures. Since multicast communication is commonly used in cache coherence protocols for CMPs and in various parallel applications, the performance in these systems can be significantly improved if multicast operations are supported at hardware level. In this paper, we present several partitioning methods for the path-based multicast approach in 3D mesh-based NoCs, each with different levels of efficiency. In addition, we develop novel analytical models for unicast and multicast traffic to explore the efficiency of each approach. In order to distribute the unicast and multicast traffic more efficiently over the network, we propose Minimal Adaptive Routing (MAR) algorithm for the presented partitioning methods. The analytical and experimental results show that an advantageous method named Recursive Partitioning (RP) outperforms the other approaches. RP recursively partitions the network until all partitions contain a comparable number of switches and the multicast traffic is equally distributed among several subsets. The simulation results reveal that the RP method can achieve performance improvement across all workloads while the performance can be further improved by utilizing MAR, 19% average and 42% maximum latency reduction, on SPLASH-2 and PARSEC benchmarks.

  • 94. Ebrahimi, M.
    et al.
    Daneshtalab, M.
    Liljeberg, P.
    Plosila, J.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    A High-Performance Network Interface Architecture for NoCs Using Reorder Buffer Sharing2010Inngår i: 18th Euromicro Conference on Parallel, Distributed and Network-Based Processing, PDP 2010, 2010, s. 546-550Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Increasing memory parallelism in MPSoCs to provide higher memory bandwidth is achieved by accessing multiple memories simultaneously. Inasmuch as the response transactions of concurrent memory accesses must be in-order, a reordering mechanism is required. To our knowledge the resource utilization of conventional reordering mechanisms is low. In this paper, we present a novel network interface architecture for on-chip networks to increase the resource utilization and to improve overall performance. Also, based on the proposed architecture, a hybrid network interface is presented to integrate both memory and processor in a tile. The proposed architecture exploits AXI transaction based protocol to be compatible with existing IP cores. Experimental results with synthetic test cases demonstrate that the proposed architecture outperforms the conventional architecture in terms of latency. Also, the cost of the presented architecture is evaluated with UMC 0.09μm technology.

  • 95. Ebrahimi, M.
    et al.
    Daneshtalab, M.
    Liljeberg, P.
    Plosila, J.
    Tenhunen, Hannu
    University of Turku, Finland.
    Agent-based on-chip network using efficient selection method2011Inngår i: 2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, VLSI-SoC 2011, IEEE , 2011, s. 284-289Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Congestion in on-chip networks may cause many drawbacks in multiprocessor systems including throughput reduction, increase in latency, and additional power consumption. Furthermore, conventional congestion control methods, employed for on-chip networks, cannot efficiently collect congestion information and distribute them over the on-chip network. In this paper, we present a novel structure for on-chip networks, named Agent-based Network-on-Chip (ANoC), to diagnose the congested areas. In addition to the presented structure, an efficient Congestion-Aware Selection (CAS) method is proposed to reduce overall network latency. CAS is capable of selecting an appropriate output channel to route packets along a less congested path. 29% average and 35% maximum latency reduction are achieved on SPLASH-2 and PARSEC benchmarks running on a 36-core Chip Multi-Processor.

  • 96. Ebrahimi, M.
    et al.
    Daneshtalab, M.
    Liljeberg, P.
    Plosila, J.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Efficient congestion-aware selection method for on-chip networks2011Inngår i: 6th International Workshop on Reconfigurable Communication-Centric Systems-on-Chip, ReCoSoC 2011 - Proceedings, 2011Konferansepaper (Fagfellevurdert)
    Abstract [en]

    The choice of routing algorithm can have a large impact on the performance of on-chip networks. As adaptive routing algorithms may return a set of output channels, a selection method (routing policy) is employed to choose the appropriate output channel from the given set. In this paper, we present a novel on-chip network structure to detect the local and non-local congested areas. Based on the presented structure, an efficient congestion-aware selection method is proposed to choose an output channel that allows a packet to be routed through a less congested area.

  • 97. Ebrahimi, M.
    et al.
    Daneshtalab, M.
    Liljeberg, P.
    Plosila, J.
    Tenhunen, Hannu
    Department of Information Technology, University of Turku, Finland.
    Exploring partitioning methods for 3D Networks-on-Chip utilizing adaptive routing model2011Inngår i: 5th ACM/IEEE International Symposium on Networks-on-Chip, NOCS 2011, 2011, s. 73-80Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Three-Dimensional (3D) integration is a solution to the interconnect bottleneck in Two-Dimensional (2D) MultiProcessor System on Chip (MPSoC). 3D IC design improves performance and decreases power consumption by replacing long horizontal interconnects with shorter vertical ones. As the multicast communication is utilized commonly in various parallel applications, the performance can be significantly improved by supporting of multicast operations at the hardware level. In this paper, we propose a set of partitioning approaches each with a different level of efficiency. In addition, we present an advantageous method named Recursive Partitioning (RP) in which the network is recursively partitioned until all partitions contain comparable number of nodes. By this approach, the multicast traffic is distributed among several subsets and the network latency is considerably decreased. We also present Minimal Adaptive Routing (MAR) algorithm for the unicast and multicast traffic in 3D-mesh Networks-on-Chip (NoCs). The idea behind the MAR algorithm is utilizing the Hamiltonian path to provide a set of alternative paths.

  • 98. Ebrahimi, M.
    et al.
    Daneshtalab, M.
    Liljeberg, P.
    Tenhunen, Hannu
    University of Turku, Finland.
    An Adaptive Unicast/Multicast Routing Algorithm for MPSoCs2009Inngår i: PROCEEDINGS OF THE 2009 12TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN, ARCHITECTURES, METHODS AND TOOLS, 2009, s. 203-206Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Several parallel applications in MPSoCs take advantage of multicast communication. Path-based multicast scheme has been proven to be more efficient than the others multicast schemes in on-chip interconnection network. We present a new adaptive path based model for both the multicast and unicast wormhole routing protocols. The proposed model under mixed traffic models has lower latency than the previous path-based methods with negligible hardware overhead.

  • 99. Ebrahimi, M.
    et al.
    Daneshtalab, M.
    Liljeberg, P.
    Tenhunen, Hannu
    University of Turku, Finland.
    HAMUM - A Novel Routing Protocol for Unicast and Multicast Traffic in MPSoCs2010Inngår i: Proceedings of the 18th Euromicro Conference on Parallel, Distributed and Network-Based Processing, PDP 2010, 2010, s. 525-532Konferansepaper (Fagfellevurdert)
    Abstract [en]

    Many parallel applications in MPSoCs take advantage of multicast communication. Several multicast schemes such as path-based, tree-based, and unicast-based have been proposed in interconnection networks. Path-based multicast scheme has been proven to be more efficient than the other schemes in on-chip interconnection network. A new adaptive routing model based on Hamiltonian path for both the multicast and unicast traffics, called Hamiltonian Adaptive Multicast and Unicast Model (HAMUM), is presented. Results obtained in both multicast and mixed traffic models show that the proposed adaptive algorithm for multicast aspect has lower latency and power dissipation compared to previously proposed path-based multicasting algorithms with less than 0.5% hardware overhead. Additionally, for the unicast aspect the proposed adaptive model outperforms the other unicast turn models.

  • 100. Ebrahimi, M.
    et al.
    Daneshtalab, M.
    Liljeberg, P.
    Tenhunen, Hannu
    KTH, Skolan för informations- och kommunikationsteknik (ICT), Elektroniksystem.
    Partitioning methods for unicast/multicast traffic in 3D NoC architecture2010Inngår i: Proceedings of the 13th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2010, 2010, s. 127-132Konferansepaper (Fagfellevurdert)
    Abstract [en]

    As the scale of integration grows, the interconnection problem becomes one of the major design considerations of Multi Processor System on Chip (MPSoC). In recent years, many researchers have conducted studies on 3D IC designs stacking multiple layers on top of each other. In order to decrease the transmission delay of unicast/multicast messages in a network based multicore system, the network is divided into several partitions. In this paper, we first introduce a novel idea of balanced partitioning that allows the network to be partitioned effectively. Then, we propose a set of partitioning approaches each with a different level of efficiency. In addition, we present an advantageous method based on the idea of balanced partitioning to provide a high degree of parallelism with a considerable reduction of packet delay in unicast/multicast traffic. Simulations are provided to evaluate and compare the performance of proposed methods.

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