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  • 601. Zhang, J.
    et al.
    Yu, Z.
    Zhang, K.
    Lu, Z.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Efficient distributed memory management in a multi-core H.264 decoder on FPGA2013In: 2013 International Symposium on System-on-Chip, SoC 2013 - Proceedings, IEEE Computer Society, 2013, p. 6675256-Conference paper (Refereed)
    Abstract [en]

    Memory management is a challenging issue of multicore architecture. With growing core numbers, Distributed Shared Memory (DSM) is becoming a general trend. In this paper, a DSM based multi-core architecture is explored and evaluated via an H.264 decoder application. The memory access and communication over Network-on-Chips is managed by the Data Management Engine (DME). Experimental results realized on an Altera Strati x VI show that 9-node distributed memory system increases performance by 1.5x compared to centralized memory. Moreover, the performance of proposed DSM architecture grows linearly with the number of cores deployed.

  • 602.
    Zhang, Yuang
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Li, L.
    Jantsch, A.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
    Gao, M.
    Fu, Y.
    Pan, H.
    Exploring stacked main memory architecture for 3D GPGPUs2015In: Proceedings - 2015 IEEE 11th International Conference on ASIC, ASICON 2015, IEEE conference proceedings, 2015Conference paper (Refereed)
    Abstract [en]

    The tremendous number of threads on general purpose graphic processing units (GPGPUs) poses significant challenges on memory architecture design. 3D stacked main memory architecture atop GPGPU is a potential approach to provide high data communication bandwidth and low access latency to meet the requirement of GPGPUs. In this paper, we explore the performance of 3D GPGPUs with stacked main memory. The experimental results show that the 3D stacked GPGPU can provide up to 124.1% and on average 55.8% performance improvement compared to a 2D GPGPU scheme.

  • 603.
    Zhang, Zhi
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Networked RFID Systems for the Internet of Things2013Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The Internet of Things (IoT) utilizes trillions of uniquely identifiable smart objects to connect anything at anytime and anywhere. Radio frequency identification (RFID) techniques are a powerful promising enabler for realizing the IoT. Around how to build hierarchical networked RFID systems for the IoT, this dissertation formulates and addresses problems in three key areas, i.e., communication protocols, simulation approaches, and RFID applications.

    Communication protocols are essential for designing high-performance networked RFID systems. First, we propose to use time hopping pulse-position modulation (TH-PPM) impulse radio ultra wideband (IR-UWB) for the tag-to-reader link. We analyze different parts of the system delay and propose relevant strategies to shorten the delay. Second, we give the concept of code division multiple access (CDMA) UWB RFID systems. We analyze the asynchronous matched filter receiver and decorrelating receiver for multi-tag detection, and propose a new communication process that fully exploits the multiple-access capability of the two detection schemes.

    Simulations are widely used to evaluate the performance of wireless networks. We propose a new approach for simulating networked RFID systems with multiple wireless standards within one case in OMNeT++. It is realized by partitioning and modeling the protocol stacks of different standards and designing a multi-radio module. Moreover, we propose a CO-Simulation framework with MATLAB and OMNeT++ (COSMO). COSMO has the ability of self-validation. It combines the strengths of MATLAB and OMNeT++ by compiling prebuilt models in MATLAB to header files and shared libraries and integrating them into OMNeT++.

    RFID technology gains popularity because it can be used to track and monitor objects in real time. We implement two typical networked RFID applications, i.e., wide area RFID sensor network and item-level indoor RFID localization. We design a two-layered wide area RFID sensor network for fresh food tracking. It adopts GSM/GPRS for the communication between the server and master nodes, and semi IR-UWB for the communication between master nodes and slave nodes. We develop the control platform and implement the all-in-one sensor nodes. For indoor RFID localization, we give insights about the influence of tag interaction on tag antenna radiation pattern and localization accuracy. Two examples, i.e., the k-NN algorithm and the Simplex algorithm, are taken to show how to utilize tag interaction analysis to improve the design of localization algorithms.

  • 604.
    Zhang, Zhi
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Yan, Xiaolang
    Design and Optimization of a CDMA-based Multi-Reader Passive UHF RFID System for Dense Scenarios2012In: IEICE transactions on communications, ISSN 0916-8516, E-ISSN 1745-1345, Vol. E95B, no 1, p. 206-216Article in journal (Refereed)
    Abstract [en]

    In dense passive radio frequency identification (RFID) systems, code division multiple access (CDMA) techniques can be used to alleviate severe collisions and thus enhance the system performance. However, conventional CDMA techniques are challenging to implement, especially for passive tags due to cost and power constraints. In this paper, we design a CDMA-based multi-reader passive ultra high frequency (UHF) RFID system in which a reader detects only the strongest tag signal and a tag uses Gold codes only on the preamble and the data bits of RN16 without increasing its clock frequency. We present a new communication procedure based on dynamic framed slotted ALOHA (DFSA). In order to optimize the system, we theoretically analyze the system performance in terms of slot capacity and identification rate, and formally show how the code length and the number of readers affect the identification rate. Furthermore, we propose an effective method for tag estimation and frame size adjustment, and validate it via simulations. Through an example, we demonstrate how the analysis-based technique can be used to optimize the system configurations with respect to the number of readers and the number and length of Gold codes.

  • 605.
    Zhang, Zhi
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Yan, Xiaolang
    Institute of VLSI Design, Zhejiang University, Hangzhou, China.
    Zheng, Li-Rong
    A high performance multi-reader passive RFID system for Internet-of-ThingsIn: IEEE Transactions on Wireless Communications, ISSN 1536-1276, E-ISSN 1558-2248Article in journal (Other academic)
  • 606.
    Zhang, Zhi
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Yan, Xiaolang
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Code division multiple access/pulse position modulation ultra-wideband radio frequency identification for Internet of Things: concept and analysis2012In: International Journal of Communication Systems, ISSN 1074-5351, E-ISSN 1099-1131, Vol. 25, no 9, p. 1103-1121Article in journal (Refereed)
    Abstract [en]

    Radio frequency identification (RFID) is a compelling technology for Internet of Things (IoT). Ultra-wideband (UWB) technology is one promising wireless technique for future RFID, especially for high-throughput sensing applications. On-off keying UWB RFID system provides high pulse rate but suffers severe collisions that limit the system throughput. This paper proposes to utilize low pulse rate code division multiple access/pulse position modulation UWB in the tag-to-reader link to provide multiple tag access capability and build a high-throughput RFID system for IoT. We analyze asynchronous matched filter receiver and decorrelating receiver for multi-tag detection and design an effective medium access control scheme to optimize the network throughput. We propose an effective dynamic frame size adjustment algorithm on the basis of theoretical analysis and determine the preferable length of Gold codes. With a similar data rate, the throughput of the proposed system using the decorrelating receiver is 8.6 times higher than that of the electronic product code class 1 generation 2 system. Only using 1/10 pulse rate and 1/15 data rate, the proposed system outperforms the on-off keying UWB RFID system 1.4 times in terms of throughput.

  • 607.
    Zhang, Zhi
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Yan, Xiaolang
    Institute of VLSI Design, Zhejiang University, Hangzhou, China.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    COSMO: CO-simulation with MATLAB and OMNeT++ for indoor wireless networks2010In: 2010 IEEE GLOBAL TELECOMMUNICATIONS CONFERENCE GLOBECOM 2010, 2010Conference paper (Refereed)
    Abstract [en]

    Simulations are widely used to design and evaluate new protocols and applications of indoor wireless networks. However, the available network simulation tools face the challenges of providing accurate indoor channel models, three-dimensional (3-D) models, model portability, and effective validation. In order to overcome these challenges, this paper presents a new CO-Simulation framework based on MATLAB and OMNeT++ (COSMO) to rapidly build credible simulations for indoor wireless networks. A hierarchical ad hoc passive RFID network for indoor tag locating is described as a case study, demonstrating the significance and efficiency of COSMO compared with other network simulators. COSMO surpasses other network simulators in terms of workload and validity.

  • 608.
    Zhang, Zhi
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Saakian, Vardan
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Yan, Xiaolang
    Institute of VLSI Design, Zhejiang University.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Item-Level Indoor Localization With Passive UHF RFID Based on Tag Interaction Analysis2013In: IEEE transactions on industrial electronics (1982. Print), ISSN 0278-0046, E-ISSN 1557-9948, Vol. 61, no 4, p. 2122-2135Article in journal (Refereed)
    Abstract [en]

    Radio-frequency identification (RFID) with a received signal strength indicator (RSSI) is a low-cost and low-complexity approach for item-level indoor localization. Although RSSI-based algorithms suffer from multipath effect and other environmental factors, reference tags and RSSI changes can be utilized to further improve the localization accuracy. However, the current algorithms lack deep analysis of the influence of tag interaction on localization accuracy and faces the challenge of simultaneously locating multiple close targets. In this paper, we propose an analysis method about how tag interaction affects a tag antenna radiation pattern and an RSSI change. The tag interaction analysis guides us to improve the design of RSSI-based localization algorithms. We take the k-nearest neighbor (k-NN) algorithm and the Simplex algorithm as two examples. The experimental results show that the revised k-NN and the revised Simplex algorithms are robust to different numbers, spacing, and materials of target objects, and they are superior to other RFID localization schemes, considering cost, capability of simultaneous localization of multiple targets, and location estimation errors.

  • 609.
    Zhao, Xueqian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Empowering study of delay bound tightness with simulated annealing2014In: Proceedings -Design, Automation and Test in Europe, DATE, 2014Conference paper (Refereed)
    Abstract [en]

    Studying the delay bound tightness typically takes a practical approach by comparing simulated results against analytic results. However, this is often a manual process whereas many simulation parameters have to be configured before the simulations run. This is a tedious and time-consuming process. We propose a technique to automate this process by using a simulated annealing approach. We formulate the problem as an online optimization problem, and embed a simulated annealing algorithm in the simulation environment to guide the search of configuration parameters which give good tightness results. This is a fully automated procedure and thus provide a promising path to automatic design space exploration in similar contexts. Experiment results of an all-to-one communication network with large searching space and complicated constraints illustrate the effectiveness of our method.

  • 610.
    Zhao, Xueqian
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Per-flow delay bound analysis based on a formalized microarchitectural model2013In: 2013 7th IEEE/ACM International Symposium on Networks-on-Chip, NoCS 2013, IEEE , 2013, p. 6558411-Conference paper (Refereed)
    Abstract [en]

    System design starting from high level models can facilitate formal verification of system properties, such as safety and deadlock freedom. Yet, analyzing their QoS property, in our context, per-flow delay bound, is an open challenge. Based on xMAS (eXecutable Micro-Architectural Specification), a formal framework modeling communication fabrics, we present a QoS analysis procedure using network calculus. Given network and flow knowledge, we first create a well-defined xMAS model for a specific application on a concrete on-chip network. Then the specific xMAS model can be mapped to its network calculus analysis model for which existing QoS analysis techniques can be applied to compute end-to-end delay bound per flow. We give an example to show the step-by-step analysis procedure and discuss the tightness of the results.

  • 611.
    Zhou, Qin
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mao, Jia
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zou, Zhuo
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A mixed-signal timing circuit in 90nm CMOS for energy detection IR-UWB receivers2010In: 23rd IEEE International SOC Conference, SOCC 2010, 2010, p. 413-416Conference paper (Other academic)
    Abstract [en]

    This paper presents a flexible timing circuit with 1.1ns delay resolution for energy detection IR-UWB receivers. Referenced at 900MHz input clock, the circuit generates multi-phased integration windows and reset signals that enable/disable the operation of analog blocks. The design is highly programmable, adapting the receiver to pulse level synchronization, symbol level synchronization, different data rates and various channel environments. Mixed-signal design flow is adopted to avoid the complexity of full custom design and the large power consumption of full synthesized digital design. The timing circuit is implemented in UMC 90nm CMOS process, with 219 #x03BC;W power consumption and 190*295 #x03BC;m2 die area.

  • 612.
    Zhou, Qin
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zou, Zhuo
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A Flexible Back-end with Optimum Threshold Estimation for OOK Based Energy Detection IR-UWB Receivers2011In: 2011 IEEE International Conference on Ultra-Wideband (ICUWB), 2011, p. 130-134Conference paper (Other academic)
    Abstract [en]

    Impulse Radio Ultra-Wideband (IR-UWB) exhibits strong advantages in low power and low cost applications such as RFID and Wireless Sensor Networks. This paper presents an on-off keying (OOK) based energy detection IR-UWB receiver with focus on the back-end design. In order to optimize the receiver performance according to different multi-path environment, variable integration interval and adaptive threshold optimization are considered in the proposed back-end which is composed by a programmable timing circuit and a reconfigurable baseband processor. The timing circuit is able to generate multi-phased integration windows with wide-range variable integration interval and is implemented in 90 nm CMOS process. Novel schemes on synchronization and optimum threshold estimation are suggested for baseband processing. The proposed synchronization scheme is based on maximum energy variance (between symbol `0' and `1') detection, covering both the pulse level and symbol level synchronization. And the scheme for optimum threshold estimation is based on look up table, enabling low complexity implementation. System simulation with IEEE 802.15.4a channel models shows an appreciable improvement on the bit error rate (BER) performance compared with the conventional scheme.

  • 613.
    Zhou, Qin
    et al.
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zou, Zhuo
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mao, Jia
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A flexible energy detection IR-UWB receiver for RFID and WSN2010Other (Other academic)
    Abstract [en]

    This paper presents an energy detection impulse radio ultra-wideband (IR-UWB) receiver for radio frequency identification (RFID) and wireless sensor networks (WSN) applications. As opposed to coherent receivers, it uses simple square-integrate samplers, that allows low complexity and low power implementations. This prototype is composed by an analog front-end and timing-critical digital blocks in UMC 90nm CMOS process, and an Altera Cyclone III FPGA development kit for back-end processing, connected by a high speed mezzanine card (HSMC). Thanks to the flexible back-end on FPGA, the receiver is featured by high programmability and multi-mode operation which adopts a wide range of pulse rates and data rates, different modulation and synchronization schemes, and various channel environments.

  • 614.
    Zhou, Qin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zou, Zhuo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Adaptive synchronization and integration region optimization for energy detection IR-UWB receivers2012In: Ultra-Wideband (ICUWB), 2012 IEEE International Conference on, IEEE , 2012, p. 62-66Conference paper (Refereed)
    Abstract [en]

    Non-coherent energy detection (ED) IR-UWB receivers exhibit strong advantages in low data rate, low power and low cost applications such as RFID and Wireless Sensor Networks. However, the performance of ED receivers is usually suffered from the noise enhancement due to the large time-bandwidth product. The integration region of the receiver integrator significantly affects the bit error rate (BER) performance. This paper presents a method of synchronization and estimating the optimal integration region (i.e., the starting point and the length of the integration window), which is based on the analysis of received signal energy capture and combined with a time of arrival (TOA) estimation. The proposed scheme is based on the symbol rate sampling and does not require a priori information about the channel delay profile. Besides, it can adapt to various indoor channel environments. The algorithm has a moderate accuracy but a very low complexity and fast synchronization speed. The validity of the proposed approach is demonstrated by numerical results using IEEE 802.15.4a channel models.

  • 615.
    Zhou, Qin
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zou, Zhuo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Exploration and performance evaluation of a compressed sensing based IR-UWB receiver2013In: 2013 IEEE International Conference on Ultra-Wideband (ICUWB), IEEE , 2013, p. 226-230Conference paper (Refereed)
    Abstract [en]

    Compressed sensing (CS) is an emerging technique which enables sub-Nyquist sampling of sparse or compressible signals. The application of CS theory in the impulse radio ultrawideband (IR-UWB) receiver design has recently attracted much attention. This paper provides an exploration of the CS-based IR-UWB receiver from different aspects: front-end hardware architectures, back-end signal processing algorithms as well as application scenarios. And the performance of the CS receiver regarding the number of CS measurement and different CS recovery algorithms is evaluated and compared against the conventional sub-Nyquist sampling receiver based on energy detection (ED) scheme. Moreover, a strategy to improve the CS receiver performance in handling UWB signals with heavy noise and multipath propagation is proposed.

  • 616.
    Zhu, Jun
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Performance Analysis and Implementationof Predictable Streaming Applications onMultiprocessor Systems-on-Chip2010Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Driven by the increasing capacity of integrated circuits, multiprocessorsystems-on-chip (MPSoCs) are widely used in modern consumer electron-ics devices. In this thesis, the performance analysis and implementationmethodologies are explored to design predictable streaming applications onMPSoCs computing platforms. The application functionality and concur-rency are described in synchronous data flow (SDF) computational models,and two state-of-the-art architecture templates are adopted as multiproces-sor architectures, i.e., network-on-chip (NoC) based MPSoC and hybrid re-configurable CPU/FPGA platforms. Based on the author’s contributions onsimulation and formal analytical methods, performance analysis and designspace exploration for embedded MPSoCs architectures have been addressed.

    An energy efficient design space exploration flow is proposed for stream-ing applications with guaranteed throughput on NoC based MPSoCs, in whichboth application throughput analysis and system energy calculation are car-ried out by simulation on a multi-clocked synchronous modelling frame-work. On the other hand, based on event models of data streams, a formalanalytical scheduling framework for real-time streaming applications withminimal buffer requirement on hybrid CPU/FPGA architectures is exploited.The scheduling problem has been formalized declaratively by constraint basetechniques, and solved by a public domain constraint solver. Consecutively,the constraint based method has been extended to solve problems rangingfrom global computation/communication scheduling and reconfiguration anal-ysis to Pareto efficient design. Finally, a prototype of stream processing sys-tem on FPGA based MPSoC is built to substantiate the results from theoreti-cal studies in this thesis.

  • 617.
    Zhu, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Constrained Global Scheduling of Streaming Applications on MPSoCs2010In: 2010 15TH ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC 2010), 2010, p. 223-228Conference paper (Refereed)
    Abstract [en]

    We present a global scheduling framework for synchronous data flow (SDF) streaming applications on MPSoCs, based on optimized computation and contention-free routing. The global scheduling of processors computing and communication transactions are formulated as constraint based problem, to avoid the scheduling overhead in TDMA-like heuristic schemes. A public domain constraint solver is exploited to solve the NP-complete scheduling efficiently, together with problem specific constraint modeling techniques. Experimental results show that the proposed framework can achieve a high predictable application throughput with minimized buffer cost. For instance, for applications in communication domain, higher throughput (up to 87%) has been observed with less buffer cost, compared to scenarios considering the heuristic scheduling overhead.

  • 618.
    Zhu, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    HetMoC: Heterogeneous Modeling in SystemC2010In: Proceedings of the Forum on Design Langauges (FDL), 2010, p. 117-122Conference paper (Refereed)
    Abstract [en]

    We propose a novel heterogeneous model-of-computation (HetMoC) framework in SystemC for embedded computing systems. As the main contribution, we formally define the computation and communication in multiple domains (continuous-time, discrete-event, synchronous/reactive, and untimed) as polymorphic processes and signals, and present domain interfaces to integrate different domains together for heterogeneous process networks. Especially, the continuous-time signals are defined with time continuum, which are distinguished from existing approaches. For implementation, a functional modeling style has been adopted to construct HetMoC. A solver with error estimation has been exploited in numerical approximation, and the time-varying functionalities in adaptive systems have been captured in HetMoC as well. In experiments, based on an adaptive transceiver system case study, HetMoC shows promising capabilities compared with a reference model in SystemC-AMS.

  • 619.
    Zhu, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Pareto Efficient Design for Reconfigurable Streaming Applications on CPU/FPGAs2010In: Proceedings of Design Automation and Test in Europe (DATE ’10), 2010, p. 1035-1040Conference paper (Refereed)
    Abstract [en]

    We present a Pareto efficient design method for multi-dimensional optimization of run-time reconfigurable streaming applications on CPU/FPGA platforms, which automatically allocates applications with optimized buffer requirement and software/hardware implementation cost. At the same time, application performance is guaranteed with sustainable throughput during run-time reconfigurations. As the main contribution, we formulate the constraint based application allocation, scheduling, and reconfiguration analysis, and propose a design Pareto-point calculation flow. A public domain solver - Gecode is used in solutions finding. The capability of our method has been exemplified by two cases studies on applications from media and communication domains.

  • 620.
    Zhu, Jun
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Sander, Ingo
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Jantsch, Axel
    KTH, School of Information and Communication Technology (ICT), Electronic, Computer and Software Systems, ECS.
    Performance Analysis of Reconfigurations in Adaptive Real-Time Streaming Applications2012In: ACM Transactions on Embedded Computing Systems, ISSN 1539-9087, E-ISSN 1558-3465, Vol. 11, no 1, p. 12-Article in journal (Refereed)
    Abstract [en]

    We propose a performance analysis framework for adaptive real-time synchronous data flow streaming applications on runtime reconfigurable FPGAs. As the main contribution, we present a constraint based approach to capture both streaming application execution semantics and the varying design concerns during reconfigurations. With our event models constructed as cumulative functions on data streams, we exploit a novel compile-time analysis framework based on iterative timing phases. Finally, we implement our framework on a public domain constraint solver, and illustrate its capabilities in the analysis of design trade-offs due to reconfigurations with experiments.

  • 621.
    Zou, Zhuo
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Impulse Radio UWB for the Internet-of-Things: A Study on UHF/UWB Hybrid Solution2011Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    This dissertation investigates Ultra-Wideband (UWB) techniques for the next generation Radio Frequency Identification (RFID) towards the Internet-of-Things (IoT). In particular, an ultra-high frequency (UHF) wireless-powered UWB radio (UHF/UWB hybrid) with asymmetric links is explored from system architecture to circuit implementation.

    Context-aware, location-aware, and energy-aware computing for the IoT demands future micro-devices (e.g., RFID tags) with capabilities of sensing, processing, communication, and positioning, which can be integrated into everyday objects including paper documents, as well as food and pharmaceutical packages. To this end, reliable-operating and maintenance-free wireless networks with low-power and low-cost radio transceivers are essential. In this context, state-of-the-art passive RFID technologies provide limited data rate and positioning accuracy, whereas active radios suffer from high complexity and power-hungry transceivers. Impulse Radio UWB (IR-UWB) exhibits significant advantages that are expected to overcome these limitations. Wideband signals offer robust communications and high-precision positioning; duty-cycled operations allow link scalability; and baseband-like architecture facilitates extremely simple and low-power transmitters. However, the implementation of the IR-UWB receiver is still power-hungry and complex, and thus is unacceptable for self-powered or passive tags.

    To cope with μW level power budget in wireless-powered systems, this dissertation proposes an UHF/UWB hybrid radio architecture with asymmetric links. It combines the passive UHF RFID and the IR-UWB transmitter. In the downlink (reader-tag), the tag is powered and controlled by UHF signals as conventional passive UHF tags, whereas it uses an IR-UWB transmitter to send data for a short time at a high rate in the uplink (tag-reader). Such an innovative architecture takes advantage of UWB transmissions, while the tag avoids the complex UWB receiver by shifting the burden to the reader. A wireless-powered tag providing -18.5 dBm sensitivity UHF downlink and 10 Mb/s UWB uplink is implemented in 180 nm CMOS. At the reader side, a non-coherent energy detection IR-UWB receiver is designed to pair the tag. The receiver is featured by high energy-efficiency and flexibility that supports multi-mode operations. A novel synchronization scheme based on the energy offset is suggested. It allows fast synchronization between the reader and tags, without increasing the hardware complexity. Time-of-Arrival (TOA) estimation schemes are analyzed and developed for the reader, which enables tag localization. The receiver prototype is fabricated in 90 nm CMOS with 16.3 mW power consumption and -79 dBm sensitivity at 10 Mb/s data rate. The system concept is verified by the link measurement between the tag and the reader. Compared with current passive UHF RFID systems, the UHF/UWB hybrid solution provides an order of magnitude improvement in terms of the data rate and positioning accuracy brought by the IR-UWB uplink.

  • 622.
    Zou, Zhuo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qing
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Uysal, Ismail
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Radio frequency identification enabled wireless sensing for intelligent food logistics2014In: Philosophical Transactions. Series A: Mathematical, physical, and engineering science, ISSN 1364-503X, E-ISSN 1471-2962, Vol. 372, no 2017, p. 20130313-Article, review/survey (Refereed)
    Abstract [en]

    Future technologies and applications for the Internet of Things (IoT) will evolve the process of the food supply chain and create added value of business. Radio frequency identifications (RFIDs) and wireless sensor networks (WSNs) have been considered as the key technological enablers. Intelligent tags, powered by autonomous energy, are attached on objects, networked by short-range wireless links, allowing the physical parameters such as temperatures and humidities as well as the location information to seamlessly integrate with the enterprise information system over the Internet. In this paper, challenges, considerations and design examples are reviewed from system, implementation and application perspectives, particularly with focus on intelligent packaging and logistics for the fresh food tracking and monitoring service. An IoT platform with a two-layer network architecture is introduced consisting of an asymmetric tag-reader link (RFID layer) and an ad-hoc link between readers (WSN layer), which are further connected to the Internet via cellular or Wi-Fi. Then, we provide insights into the enabling technology of RFID with sensing capabilities. Passive, semi-passive and active RFID solutions are discussed. In particular, we describe ultra-wideband radio RFID which has been considered as one of the most promising techniques for ultra-low-power and low-cost wireless sensing. Finally, an example is provided in the form of an application in fresh food tracking services and corresponding field testing results.

  • 623.
    Zou, Zhuo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mendoza, David Sarmiento
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Wang, Peng
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. Fudan University, China.
    Zhou, Qin
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Mao, Jia
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Jonsson, Fredrik
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Tenhunen, Hannu
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Li-Rong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. Fudan University, China.
    A Low-Power and Flexible Energy Detection IR-UWB Receiver for RFID and Wireless Sensor Networks2011In: IEEE Transactions on Circuits and Systems I: Regular Papers, ISSN 1549-8328, Vol. 58, no 7, p. 1470-1482Article in journal (Refereed)
    Abstract [en]

    This paper presents an energy detection Impulse Radio Ultra-Wideband (IR-UWB) receiver for Radio Frequency Identification (RFID) and Wireless Sensor Networks (WSN) applications. An Application-Specific Integrated Circuit (ASIC) consisting of a 3-5 GHz analog front-end, a timing circuit and a high speed baseband controller is implemented in a 90 nm standard CMOS technology. A Field-Programmable Gate Array (FPGA) is employed as a reconfigurable back-end, enabling adaptive baseband algorithms and ranging estimations. The proposed architecture is featured by high flexibility that adopts a wide range of pulse rate (512 kHz-33 MHz), processing gain (0-18 dB), correlation schemes, synchronization algorithms, and modulation schemes (PPM/OOK). The receiver prototype was fabricated and measured. The power consumption of the ASIC is 16.3 mW at 1 V power supply, which promises a minimal energy consumption of 0.5 nJ/bit. The whole link is evaluated together with a UWB RFID tag. Bit error rate (BER) measurement displays a sensitivity of -79 dBm at 10 Mb/s with 10(-3) BER achieved by the proposed receiver, corresponding to an operation distance over 10 meters under the FCC regulation.

  • 624.
    Zou, Zhuo
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Shao, Botao
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zhou, Qin
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zhai, Chuanying
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Mao, Jia
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Baghaei-Nejad, Majid
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Chen, Qiang
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Zheng, Lirong
    KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
    Design and demonstration of passive UWB RFIDs: Chipless versus chip solutions2012In: RFID-Technologies and Applications (RFID-TA), 2012 IEEE International Conference on, IEEE , 2012, p. 6-11Conference paper (Refereed)
    Abstract [en]

    This paper reviews recent research on Ultra-Wideband (UWB) techniques for the next generation Radio Frequency IDentification (RFID) towards the Internet-of-Things (IoT), conducted by Vinn iPack Center at KTH, Sweden. First, we introduce an inkjet printed chipless UWB RFID for ultra-low cost applications such as item-level tracking. The identification number is coded by variations of the impedance over the transmission line, resulting in the OOK modulated data by means of pulse reflections in time domain. Prototypes were fabricated and measured for 4-bit tag and 8-bit tag, respectively. Thanks to the employment of fully printing process and paper substrates, the tag is potentially ultra-low cost in volume production. Second, a wirelessly powered RFID tag with an active UWB transmitter is studied for advanced applications such as wireless positioning and sensing. The tag is powered by UHF continuous waves, whereas it uses an UWB pulse generator to transmit data to the reader. It ensures the improved coverage and accurate positioning over traditional backscattering UHF tags. UWB readers, positioning, and sensing are also discussed in a system perspective. The two solutions reveal that UWB is a viable alternative to existing passive RFIDs adapting both low-cost applications and high-performance sensing and positioning applications.

  • 625. Öberg, J.
    et al.
    Ellervee, P.
    Mokhtari, M.
    Jantsch, A.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Design of a 1 GIPS Peak Performance Processor using GaAs Technology1994In: Proceedings of the IEEE NORCHIP Conference, 1994Conference paper (Refereed)
  • 626. Öberg, J.
    et al.
    Isoaho, J.
    Ellervee, P.
    Jantsch, A.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, A.
    BABBAGE - A Rule based Tool for Synthesis of Hardware Systems1994In: Proceedings of the IEEE NORCHIP Conference, 1994Conference paper (Refereed)
  • 627.
    Öberg, Johnny
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Ellervee, Peeter
    Kumar, Anshul
    Hemani, Ahmed
    Comparing Conventional HLS with Grammar-Based Hardware Synthesis: A Case Study1997Conference paper (Refereed)
  • 628.
    Öberg, Johnny
    et al.
    KTH, Superseded Departments, Electronic Systems Design.
    Isoaho, Jouni
    Tampere University of Technology, Signal Processing Laboratory.
    Ellervee, Peeter
    KTH, Superseded Departments, Electronic Systems Design.
    Jantsch, Axel
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A rule-based approach for improving allocation of filter structures in HLS1996In: Ninth International Conference on VLSI Design, 1996. Proceedings, IEEE conference proceedings, 1996, p. 133-139Conference paper (Refereed)
    Abstract [en]

    A rule based allocator for improving synthesis of filter systems is presented. The principles of the Enhanced AIlocation Rule Language Interpreter (EARLI) are presented. Possible transformations, optimisations and how to express them in EARLI are discussed. Experiments show that relative area gains ranging from 5 to 44%, depending on the chosen target technology, can be achieved using the designers knowledge about the design class. Experiments also indicate that employing direct mapping of CDFG subgraphs onto preoptimised RTL-level macroblocks would have resulted in a relative area gain of 500%. The macroblock had only 16% of the area produced by the HLS-tool

  • 629.
    Öberg, Johnny
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kumar, Anshul
    KTH, Superseded Departments, Electronic Systems Design.
    Hemani, Ahmed
    KTH, Superseded Departments, Electronic Systems Design.
    Scheduling of outputs in grammar-based hardware synthesis of data communication protocols1998In: Design, Automation and Test in Europe, 1998., Proceedings, 1998, p. 596-603Conference paper (Refereed)
    Abstract [en]

    We present a grammar based specification method for hardware synthesis of data communication protocols in which the specification is independent of the port size. Instead, it is used during the synthesis process as a constraint. When the width of the output assignments exceed the chosen output port width, the assignments are split and scheduled over the available states. We present a solution to this problem and results of applying it to some relevant problems

  • 630.
    Öberg, Johnny
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Kumar, Anshul
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Hemani, Ahmed
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Specification of exception handling in grammar-based hardware synthesis1998In: Euromicro Conference, 1998. Proceedings. 24th, 1998, Vol. 1, p. 38-41Conference paper (Refereed)
    Abstract [en]

    ProGram is our in-house grammar based specification language targeted to specification of protocols, interfaces and control dominated functionality. The Program compiler implements such specifications in hardware. Specification of exception handling functionality and its automatic implementation are key requirements for a robust design methodology. In this paper, we present extensions to the ProGram language for specification of a wide range of exception handling functionality: reset to deal with exception handling needs of global nature, interrupt for representing exception handling on a hierarchical basis and error sequences to handle situations when inputs are not according to the specified grammar

  • 631.
    Öberg, Johnny
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Robino, Francesco
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A NoC Generator for the Sea-of-Cores Era2011In: Proceedings of FPGAWorld 2011, 2011Conference paper (Refereed)
  • 632.
    Öberg, Johnny
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Robino, Francesco
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    A NoC system generator for the Sea-of-Cores era2011In: 8th FPGAworld Conference - Academic Proceedings 2011, 2011, p. 35-40Conference paper (Refereed)
    Abstract [en]

    Multi-core systems are getting bigger. The number of cores is doubling every 18 months, in corollary with the reformulated Moore's law. Soon, the number of cores that can be integrated together in a system will be so large, that it is appropriate to talk about a new SoC design paradigm, the Sea-of-Cores era. This development will not end, even when CMOS cannot be made any smaller. Instead, with the development of Through-Silicon Vias (TSVs), chips will be stacked in 3D, promising continuous scaling for a very long time ahead. As systems grow, programming and debugging of them will become harder. Methods for generating the systems from higher-level specifications will be necessary to manage design complexity. Also, there will be so many processors to be programmed, that the SW also will have to be automatically generated and distributed, much in the same way as a synthesis and place & route tool is doing today for HW. In this paper, we present a NoC generator that can generate an arbitrarily large Multi-core platform from an XML configuration file, targeted for single-chip FPGA platforms. The NoC generator also generates a device driver prototype together with a small test program that can be used as a template for creating larger programs.

  • 633.
    Šimbelis, Vygandas
    et al.
    KTH, School of Computer Science and Communication (CSC), Media Technology and Interaction Design, MID.
    Lundström, Anders
    KTH, School of Computer Science and Communication (CSC), Media Technology and Interaction Design, MID.
    Höök, Kristina
    KTH, School of Computer Science and Communication (CSC), Media Technology and Interaction Design, MID.
    Solsona, Jordi
    KTH, School of Information and Communication Technology (ICT), Electronic Systems.
    Lewandowski, Vincent
    KTH, School of Computer Science and Communication (CSC), Media Technology and Interaction Design, MID.
    Metaphone: Machine aesthetics meets interaction design2014In: CHI '14 Proceedings of the SIGCHI Conference on Human Factors in Computing Systems, Association for Computing Machinery (ACM), 2014, p. 1-10Conference paper (Refereed)
    Abstract [en]

    Through our art project, Metaphone, we explored a particular form of aesthetics referred to in the arts tradition as machine aesthetics. The Metaphone machine collects the participant's bio-data, Galvanic Skin Response (GSR) and Heart Rate (HR), creating a process of movement, painting and sound. The machine behaves in machine-like, aesthetically evocative ways: A shaft on two large wheels rotates on the floor, carrying paint that is dripped onto a large sheet of aquarelle paper on the floor according to bio-sensor data. A soundscape rhythmically follows the bio-sensor data, but also has its own machine-like sounds. Six commentators were invited to interact with the machine. They reported a strangely relaxing atmosphere induced by the machine. Based on these experiences we discuss how different art styles can help to describe aesthetics in interaction design generally, and how machine aesthetics in particular can be used to create interesting, sustained, stylistically coherent interactions.

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