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• 1. Anurag,
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Pervasive health monitoring based on internet of things: Two case studies2015In: Proceedings of the 2014 4th International Conference on Wireless Mobile Communication and Healthcare - "Transforming Healthcare Through Innovations in Mobile and Wireless Technologies", MOBIHEALTH 2014, 2015, p. 275-278Conference paper (Refereed)

With the continuous evolution of wireless sensor networks and Internet of Things (IoT) various aspects of life will benefit. IoT based pervasive healthcare system has potential to provide error free medical data and alerting system in critical conditions with continuous monitoring. The system will minimize the need of dedicated medical personnel for patient monitoring and help the patients to lead a normal life besides providing them with high quality medical service. In this paper, we provide the implementation of IoT-based architectures for remote health monitoring based on two popular wireless technologies, Wi-Fi and ZigBee. We analyse the two architectures with the aim of identifying their pros and cons and discuss suitability of mentioned wireless communication technologies for different healthcare application domains.

• 2. Anzanpour, A.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland.
Context-aware early warning system for in-home healthcare using internet-of-things2016In: 2nd International Summit on Internet of Things, IoT 360° 2015, Springer, 2016, p. 517-522Conference paper (Refereed)

Early warning score (EWS) is a prediction method to notify caregivers at a hospital about the deterioration of a patient. Deterioration can be identified by detecting abnormalities in patient’s vital signs several hours prior the condition of the patient gets life-threatening. In the existing EWS systems, monitoring of patient’s vital signs and the determining the score is mostly performed in a paper and pen based way. Furthermore, currently it is done solely in a hospital environment. In this paper, we propose to import this system to patients’ home to provide an automated platform which not only monitors patents’ vital signs but also looks over his/her activities and the surrounding environment. Thanks to the Internet-of-Things technology, we present an intelligent early warning method to remotely monitor in-home patients and generate alerts in case of different medical emergencies or radical changes in condition of the patient. We also demonstrate an early warning score analysis system which continuously performs sensing, transferring, and recording vital signs, activity-related data, and environmental parameters.

• 3. Aslam, Bilal
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. Univ Engn & Technol, Pakistan. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. University of Turku, Finland.
Frequency signature chipless RFID tag with enhanced data capacity2015In: IEICE Electronics Express, ISSN 1349-2543, E-ISSN 1349-2543, Vol. 12, no 17, article id 20150623Article in journal (Refereed)

Frequency signature chipless RFID tag based on spurline resonator is presented in this letter. Resonant response of spurline is explained by analyzing the surface current distribution. Chipless tag consists of a data encoding circuit and two cross polarised monopole antennas. The tag has a data capacity of 16 bits in the range 2.13 to 4.1 GHz. Data capacity of data encoding circuit is enhanced by repositioning the spurlines. The prototype of the tag is fabricated on FR4 substrate. Developed tag can be used for cost effective identification of items in the industry.

• 4. Azimi, I.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Self-aware early warning score system for IoT-based personalized healthcare2017In: International Summit on eHealth 360°, 2016, Springer, 2017, p. 49-55Conference paper (Refereed)

Early Warning Score (EWS) system is specified to detect and predict patient deterioration in hospitals. This is achievable via monitoring patient's vital signs continuously and is often manually done with paper and pen. However, because of the constraints in healthcare resources and the high hospital costs, the patient might not be hospitalized for the whole period of the treatments, which has lead to a demand for in-home or portable EWS systems. Such a personalized EWS system needs to monitor the patient at anytime and anywhere even when the patient is carrying out daily activities. In this paper, we propose a self-aware EWS system which is the reinforced version of the existing EWS systems by using the Internet of Things technologies and the self-awareness concept. Our self-aware approach provides (i) system adaptivity with respect to various situations and (ii) system personalization by paying attention to critical parameters. We evaluate the proposed EWS system using a full system demonstration. © ICST Institute for Computer Sciences, Social Informatics and Telecommunications Engineering 2017.

• 5. Azimi, Iman
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Internet of things for remote elderly monitoring: a study from user-centered perspective2017In: Journal of Ambient Intelligence and Humanized Computing, ISSN 1868-5137, E-ISSN 1868-5145, Vol. 8, no 2, p. 273-289Article in journal (Refereed)

Improvements in life expectancy achieved by technological advancements in the recent decades have increased the proportion of elderly people. Frailty of old age, susceptibility to diseases, and impairments are inevitable issues that these senior adults need to deal with in daily life. Recently, there has been an increasing demand on developing elderly care services utilizing novel technologies, with the aim of providing independent living. Internet of things (IoT), as an advanced paradigm to connect physical and virtual things for enhanced services, has been introduced that can provide significant improvements in remote elderly monitoring. Several efforts have been recently devoted to address elderly care requirements utilizing IoT-based systems. Nevertheless, there still exists a lack of user-centered study from an all-inclusive perspective for investigating the daily needs of senior adults. In this paper, we study the IoT-enabled systems tackling elderly monitoring to categorize the existing approaches from a new perspective and to introduce a hierarchical model for elderly-centered monitoring. We investigate the existing approaches by considering the elderly requirements at the center of the attention. In addition, we evaluate the main objectives and trends in IoT-based elderly monitoring systems in order to pave the way for future systems to improve the quality of elderly's life.

• 6. Bao, D.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. State Key Laboratory of ASIC and System, Fudan University, Shanghai, China .
A smart catheter system for minimally invasive brain monitoring2015In: Proceedings of the International Conference on Biomedical Electronics and Devices, SciTePress, 2015, p. 198-203Conference paper (Refereed)

This paper demonstrates a smart catheter system with intracranial pressure (ICP) and temperature sensing capability which is designed for real-time monitoring in traumatic brain injury (TBI) therapy. It uses a single flexible catheter with a 1 mm (3 Fr) diameter that integrates electrodes and sophisticated silicon chip on flexible substrates, enabling multimodality monitoring of physiological signals. A micro-electromechanical-system (MEMS) catheter pressure sensor is mounted on the distal end. It can be used for detecting both pressure and temperature by different switch configurations, which minimizes the size of catheter and reduces the cost. The interconnects (signalling conductors) are printed on a bio-compatible flexible substrate, and the sensor is interfaced with an embedded electronic system at the far-end. The electronic system consists of analog front end with analog-to-digital converter (ADC), a microcontroller, and data interface to the hospital infrastructure with a graphical user interface (GUI). The overall smart catheter system achieves a pressure sensing root mean square error (RMSE) of ±1.5 mmHg measured from 20 mmHg to 300 mmHg above 1 atm and a temperature sensing RMSE of ±0.08°C measured from 32°C to 42°C. The sampling rate can be up to 10S/s. The in vivo performance is demonstrated in laboratory animals.

• 7. Bao, D.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. Fudan University, China.
A wirelessly-powered UWB sensor tag with time-domain sensor interface2014In: Proceedings - IEEE International Symposium on Circuits and Systems, 2014, p. 2503-2506Conference paper (Refereed)

This paper presents a wirelessly-powered sensor tag with a time-domain sensor interface for wireless sensing applications. The tag is remotely powered by RF wave. Instead of traditional approaches employing conventional ADCs for quantization and transmitter for data communication, in this work, a Pulse Position Modulator incorporating simple impulse radio UWB (IR-UWB) transmitter is proposed to convert and transmit the analog sensing information in time domain. The analog signal is compared with an adjustable triangular wave for analog to time conversion in signal-varying environments. Then a UWB transmitter converts the PPM signal to very short pulses and sends it back to the reader. The time interval of UWB pulses represents the original input signal in time domain which can be measured on the reader side by a time-to-digital conversion. This approach not only simplifies the ADC design but also relaxes the number of bits transmitted on the tag side. The sensor tag is designed in 180nm CMOS process. Simulation results demonstrate that the proposed approach reduce transmission power consumption by nearly 3 orders of magnitude over traditional approaches, while consuming only 85 μW for 1.5 MS/s sampling rate.

• 8.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Special Issue on Emerging Many-Core Systems for Exascale Computing2015In: ACM Journal on Emerging Technologies in Computing Systems, ISSN 1550-4832, Vol. 11, no 4, article id 39Article in journal (Other academic)
• 9. Dytckov, S.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Exploring NoC jitter effect on simulation of spiking neural networks2014In: Proceedings of the 2014 International Conference on High Performance Computing and Simulation, HPCS 2014, 2014, p. 693-696Conference paper (Refereed)

The major bottleneck in simulation of large-scale neural networks is the communication problem due to one-to-many neuron connectivity. Network-on-Chip concept has been proposed to address the problem. This work explores the drawback that is introduced by interconnection networks - a delay jitter. The preliminary experiment is held in the spiking neural network simulator introducing variable communicational delay to the simulation. The performance degradation is reported.

• 10.
University of Turku, Finland.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku, Finland. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland. Ecole Polytechnique Montreal, Canada. University of Turku, Finland. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland.
Efficient STDP Micro-Architecture for Silicon Spiking Neural Networks2014In: 2014 17TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD), 2014, p. 496-503Conference paper (Refereed)

Spiking neural networks (SNNs) are the closest approach to biological neurons in comparison with conventional artificial neural networks (ANN). SNNs are composed of neurons and synapses which are interconnected with a complex pattern. As communication in such massively parallel computational systems is getting critical, the network-on-chip (NoC) becomes a promising solution to provide a scalable and robust interconnection fabric. However, using NoC for large-scale SNNs arises a trade-off between scalability, throughput, neuron/router ratio (cluster size), and area overhead. In this paper, we tackle the trade-off using a clustering approach and try to optimize the synaptic resource utilization. An optimal cluster size can provide the lowest area overhead and power consumption. For the learning purposes, a phenomenon known as spike-timing-dependent plasticity (STDP) is utilized. The micro-architectures of the network, clusters, and the computational neurons are also described. The presented approach suggests a promising solution of integrating NoCs and STDP-based SNNs for the optimal performance based on the underlying application.

• 11.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland .
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku, Finland . KTH, School of Information and Communication Technology (ICT), Electronic Systems.
Rescuing healthy cores against disabled routers2014Conference paper (Refereed)

A router may be temporarily or permanently disabled in NoCs for several reasons such as saving power, occurring faults or testing. Disabling a router, however, may have a severe impact on the performance or functionality of the entire system if it results in disconnecting the core from the network. In this paper, we propose a deadlock-free routing algorithm which allows the core to stay connected to the system and continue its normal operation when its connected router is disabled. Our analysis and experiments show that the proposed technique has 100%, 93.60%, and 87.19% network availability by 100% packet delivery when 1, 2 and 3 routers are defunct or intentionally disabled. The algorithm provides adaptivity and it is lightweight, requiring one and two virtual channels along the X and Y dimension, respectively.

• 12.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
Printed RFID Humidity Sensor Tags for Flexible Smart Systems2015Doctoral thesis, comprehensive summary (Other academic)

Radio frequency identification (RFID) and sensing are two key technologies enabling the Internet of Things (IoT). Development of RFID tags augmented with sensing capabilities (RFID sensor tags) would allow a variety of new applications, leading to a new paradigm of the IoT. Chipless RFID sensor technology offers a low-cost solution by eliminating the need of an integrated circuit (IC) chip, and is hence highly desired for many applications. On the other hand, printing technologies have revolutionized the world of electronics, enabling cost-effective manufacturing of large-area and flexible electronics. By means of printing technologies, chipless RFID sensor tags could be made flexible and lightweight at a very low cost, lending themselves to the realization of ubiquitous intelligence in the IoT era.

This thesis investigated three construction methods of printable chipless RFID humidity sensor tags, with focus on the incorporation of the sensing function. In the first method, wireless sensing based on backscatter modulation was separately realized by loading an antenna with a humidity-sensing resistor. An RFID sensor tag could then be constructed by combining the wireless sensor with a chipless RFID tag. In the second method, a chipless RFID sensor tag was built up by introducing a delay line between the antenna and the resistor. Based on time-domain reflectometry (TDR), the tag encoded ID in the delay time between its structural-mode and antenna-mode scattering pulse, and performed the sensing function by modulating the amplitude of the antenna-mode pulse.

In both of the above methods, a resistive-type humidity-sensing material was required. Multi-walled carbon nanotubes (MWCNTs) presented themselves as promising candidate due to their outstanding electrical, structural and mechanical properties. MWCNTs functionalized (f-MWCNTs) by acid treatment demonstrated high sensitivity and fast response to relative humidity (RH), owing to the presence of carboxylic acid groups. The f-MWCNTs also exhibited superior mechanical flexibility, as their resistance and sensitivity remained almost stable under either tensile or compressive stress. Moreover, an inkjet printing process was developed for the f-MWCNTs starting from ink formulation to device fabrication. By applying the f-MWCNTs, a flexible humidity sensor based on backscatter modulation was thereby presented. The operating frequency range of the sensor was significantly enhanced by adjusting the parasitic capacitance in the f-MWCNTs resistor. A fully-printed time-coded chipless RFID humidity sensor tag was also demonstrated. In addition, a multi-parameter sensor based on TDR was proposed.The sensor concept was verified by theoretical analysis and circuit simulation.

In the third method, frequency-spectrum signature was utilized considering its advantages such as coding capacity, miniaturization, and immunity to noise. As signal collision problem is inherently challenging in chipless RFID sensor systems, short-range identification and sensing applications are believed to embody the core values of the chipless RFID sensor technology. Therefore a chipless RFID humidity sensor tag based on near-field inductive coupling was proposed. The tag was composed of two planar inductor-capacitor (LC) resonators, one for identification, and the other one for sensing. Moreover, paper was proposed to serve as humidity-sensing substrate for the sensor resonator on accounts of its porous and absorptive features.

Both inkjet paper and ordinary packaging paper were studied. A commercial UV-coated packaging paper was proven to be a viable and more robust alternative to expensive inkjet paper as substrate for inkjet-printed metal conductors. The LC resonators printed on paper substrates showed excellent sensitivity and reasonable response time to humidity in terms of resonant frequency. Particularly, the resonator printed on the UV-coated packaging paper exhibited the largest sensitivity from 20% to 70% RH, demonstrating the possibilities of directly printing the sensor tag on traditional packages to realize intelligent packaging at an ultra-low cost.

• 13.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
Low Cost Printed Chipless RFID Humidity Sensor Tag for Intelligent Packaging2015In: IEEE Sensors Journal, ISSN 1530-437X, E-ISSN 1558-1748, Vol. 15, no 6, p. 3201-3208Article in journal (Refereed)

This paper presents a fully-printed chipless radio frequency identification sensor tag for short-range item identification and humidity monitoring applications. The tag consists of two planar inductor-capacitor resonators operating wirelessly through inductive coupling. One resonator is used to encode ID data based on frequency spectrum signature, and another one works as a humidity sensor, utilizing a paper substrate as a sensing material. The sensing performances of three paper substrates, including commercial packaging paper, are investigated. The use of paper provides excellent sensitivity and reasonable response time to humidity. The cheap and robust packaging paper, particularly, exhibits the largest sensitivity over the relative humidity range from 20% to 70%, which offers the possibility of directly printing the sensor tag on traditional packages to make the package intelligent at ultralow cost.

• 14. Gia, T. N.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland.
Fog computing in healthcare Internet of Things: A case study on ECG feature extraction2015In: Proceedings - 15th IEEE International Conference on Computer and Information Technology, CIT 2015, 14th IEEE International Conference on Ubiquitous Computing and Communications, IUCC 2015, 13th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2015 and 13th IEEE International Conference on Pervasive Intelligence and Computing, PICom 2015, Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 356-363, article id 7363093Conference paper (Refereed)

Internet of Things technology provides a competent and structured approach to improve health and wellbeing of mankind. One of the feasible ways to offer healthcare services based on IoT is to monitor humans health in real-time using ubiquitous health monitoring systems which have the ability to acquire bio-signals from sensor nodes and send the data to the gateway via a particular wireless communication protocol. The real-time data is then transmitted to a remote cloud server for real-time processing, visualization, and diagnosis. In this paper, we enhance such a health monitoring system by exploiting the concept of fog computing at smart gateways providing advanced techniques and services such as embedded data mining, distributed storage, and notification service at the edge of network. Particularly, we choose Electrocardiogram (ECG) feature extraction as the case study as it plays an important role in diagnosis of many cardiac diseases. ECG signals are analyzed in smart gateways with features extracted including heart rate, P wave and T wave via a flexible template based on a lightweight wavelet transform mechanism. Our experimental results reveal that fog computing helps achieving more than 90% bandwidth efficiency and offering low-latency real time response at the edge of the network.

• 15. Gia, T. N.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland.
Fault tolerant and scalable IoT-based architecture for health monitoring2015In: SAS 2015 - 2015 IEEE Sensors Applications Symposium, Proceedings, IEEE conference proceedings, 2015, p. 334-339Conference paper (Refereed)

A novel Internet of Things based architecture supporting scalability and fault tolerance for healthcare is presented in this paper. The wireless system is constructed on top of 6LoWPAN energy efficient communication infrastructure to maximize the operation time. Fault tolerance is achieved via backup routing between nodes and advanced service mechanisms to maintain connectivity in case of failing connections between system nodes. The presented fault tolerance approach covers many fault situations such as malfunction of sink node hardware and traffic bottleneck at a node due to a high receiving data rate. A method for extending the number of medical sensing nodes at a single gateway is presented. A complete system architecture providing a quantity of features from bio-signal acquisition such as Electrocardiogram (ECG), Electroencephalography (EEG), and Electromyography (EMG) to the representation of graphical waveforms of these gathered bio-signals for remote real-time monitoring is proposed.

• 16. Gia, Tuan Nguyen
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
IoT-Based Fall Detection System with Energy Efficient Sensor Nodes2016In: 2016 2ND IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS), IEEE conference proceedings, 2016Conference paper (Refereed)

Fall needs to be attentively considered due to its highly frequent occurrence especially with old people - up to one third of 65 and above year-old people around the world are risk of being injured due to falling. Furthermore, fall is a direct or indirect factor causing severe traumas such as brain injuries or bone fractures. However, timely medical attention might help to avoid serious consequences from a fall. A viable solution to solve this is an IoT-based system which takes advantage of wireless sensor networks, wearable devices, Fog and Cloud computing. To deliver sufficient degree of reliability, wearable devices working at the core of a fall detection system, are required to work for prolonged period of time. In this paper we investigate energy consumption of sensor nodes in an IoT-based fall detection system and present a design of a customized sensor node. In addition, we compare the customized sensor node with other sensor nodes, built on general purpose development boards. The results show that sensor nodes based on delicate customized devices are more energy efficient than the others based on general purpose devices while considering identical specification of micro-controller and memory capacity. Furthermore, our customized sensor node with energy efficiency selections can operate continuously up to 35 hours.

• 17. Guang, L.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Positioning antifragility for clouds on public infrastructures2014In: Procedia Computer Science, 2014, p. 856-861Conference paper (Refereed)

Cloud computing scalably and sustainably utilizes computing and communication resources. One segment of the cloud ecosystem is the services built upon public infrastructures to address general benefits. This segment itself is an open system, involving many contributors and stakeholders, and its growth and development is an unpredictable process influenced by economical, societal and technological factors.This paper argues the antifragility as an indispensable feature for cloud computing, and proposes a development process for the open system to maintain, improve and prosper under contradicting interests of users, companies and governments. The proposal emphasizes multi-player's roles and interaction, and the temporal and spatial interleaving of development stages of different application domains.

• 18. Guang, L.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Self-adaptive SoCs for dependability: Review and prospects2014In: Advancing Embedded Systems and Real-Time Communications with Emerging Technologies, IGI Global, 2014, p. 1-21Chapter in book (Other academic)

Dependability is a primary concern for emerging billion-transistor SoCs (Systems-on-Chip), especially when the constant technology scaling introduces an increasing rate of faults and errors. Considering the time-dependent device degradation (e.g. caused by aging and run-time voltage and temperature variations), self-adaptive circuits and architectures to improve dependability is promising and very likely inevitable. This chapter extensively surveys existing works on monitoring, decision-making, and reconfiguration addressing different dependability threats to Very Large Scale Integration (VLSI) chips. Centralized, distributed, and hierarchical fault management, utilizing various redundancy schemes and exploiting logical or physical reconfiguration methods, are all examined. As future research directions, the challenge of integrating different error management schemes to account for multifold threats and the great promise of error resilient computing are identified. This chapter provides, for chip designers, much needed insights on applying a self-adaptive computing paradigm to approach dependability on error-prone, cost-sensitive SoCs.

• 19. Haghbayan, M. -H
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
MapPro: Proactive runtime mapping for dynamic workloads by quantifying ripple effect of applications on networks-on-chip2015In: Proceedings - 2015 9th IEEE/ACM International Symposium on Networks-on-Chip, NOCS 2015, Association for Computing Machinery (ACM), 2015Conference paper (Refereed)

Increasing dynamic workloads running on NoC-based many-core systems necessitates efficient runtime mapping strategies. With an unpredictable nature of application profiles, selecting a rational region to map an incoming application is an NP-hard problem in view of minimizing congestion and maximizing performance. In this paper, we propose a proactive region selection strategy which prioritizes nodes that offer lower congestion and dispersion. Our proposed strategy, MapPro, quantitatively represents the propagated impact of spatial availability and dispersion on the network with every new mapped application. This allows us to identify a suitable region to accommodate an incoming application that results in minimal congestion and dispersion. We cluster the network into squares of different radii to suit applications of different sizes and proactively select a suitable square for a new application, eliminating the overhead caused with typical reactive mapping approaches. We evaluated our proposed strategy over different traffic patterns and observed gains of up to 41% in energy efficiency, 28% in congestion and 21% dispersion when compared to the state-of-the-art region selection methods. Copyright 2015 ACM.

• 20. Haghbayan, M. -H
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Power-aware online testing of manycore systems in the dark silicon era2015In: Proceedings -Design, Automation and Test in Europe, DATE, IEEE conference proceedings, 2015, p. 435-440Conference paper (Refereed)

Online defect screening techniques to detect runtime faults are becoming a necessity in current and near future technologies. At the same time, due to aggressive technology scaling into the nanometer regime, power consumption is becoming a significant burden. Most of today's chips employ advanced power management features to monitor the power consumption and apply dynamic power budgeting (i.e., capping) accordingly to prevent over-heating of the chip. Given the notable power dissipation of existing testing methods, one needs to efficiently manage the power budget to cover test process of a many-core system in runtime. In this paper, we propose a power-aware online testing method for many-core systems benefiting from advanced power management capabilities. The proposed power-aware method uses non-intrusive online test scheduling strategy to functionally test the cores in their idle period. In addition, we propose a test-aware utilization-oriented runtime mapping technique that considers the utilization of cores and their test criticality in the mapping process. Our extensive experimental results reveal that the proposed power-aware online testing approach can efficiently utilize temporarily free resources and available power budget for the testing purposes, within less than 1% penalty on system throughput for the 16nm technology.

• 21. Haghbayan, M. -H
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. Department of Information Technology, University of Turku, Turku, Finland .
Dark silicon aware power management for manycore systems under dynamic workloads2014In: 2014 32nd IEEE International Conference on Computer Design, ICCD 2014, 2014, p. 509-512Conference paper (Refereed)

Dark Silicon denotes the phenomenon that, due to thermal and power constraints, the fraction of transistors that can operate at full frequency is decreasing with each technology generation. We propose a PID (Proportional Integral Derivative) controller based dynamic power management method that considers an upper bound on power consumption (called the Thermal Design Power (TDP)). To avoid violation of the TDP constraint for manycore systems running highly dynamic workloads, it provides fine-grained DVFS (Dynamic Voltage and Frequency Scaling) including near-threshold operation. In addition, the method distinguishes applications with hard Real-Time, soft Real-Time and no Real-Time constraints and treats them with appropriate priorities. In simulations with dynamic workloads mixed-critical application profiles, we show that the method is effective in honoring the TDP bound and it can boost system throughput by over 43% compared to a naive TDP scheduling policy.

• 22.
University of Turku, Finland.
University of Turku, Finland. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland. University of Turku, Finland. TU Wien, Austria. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland.
MapPro: Proactive Runtime Mapping for Dynamic Workloads by Quantifying Ripple Effect of Applications on Networks-on-Chip2015In: NOCS '15 Proceedings of the 9th International Symposium on Networks-on-Chip, ACM Digital Library, 2015Conference paper (Refereed)

Increasing dynamic workloads running on NoC-based many-core systems necessitates efficient runtime mapping strategies. With an unpredictable nature of application profiles, selecting a rational region to map an incoming application is an NP-hard problem in view of minimizing congestion and maximizing performance. In this paper, we propose a proactive region selection strategy which prioritizes nodes that offer lower congestion and dispersion. Our proposed strategy, MapPro, quantitatively represents the propagated impact of spatial availability and dispersion on the network with every new mapped application. This allows us to identify a suitable region to accommodate an incoming application that results in minimal congestion and dispersion. We cluster the network into squares of different radii to suit applications of different sizes and proactively select a suitable square for a new application, eliminating the overhead caused with typical reactive mapping approaches. We evaluated our proposed strategy over different traffic patterns and observed gains of up to 41% in energy efficiency, 28% in congestion and 21% dispersion when compared to the state-of-the-art region selection methods.

KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. Univ Turku.
A Lifetime-Aware Runtime Mapping Approach for Many-core Systems in the Dark Silicon Era2016In: PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), IEEE conference proceedings, 2016, p. 854-857Conference paper (Refereed)

In this paper, we propose a novel lifetime reliability-aware resource management approach for many-core architectures. The approach is based on hierarchical architecture, composed of a long-term runtime reliability analysis unit and a short-term runtime mapping unit. The former periodically analyses the aging status of the various processing units with respect to a target value specified by the designer, and performs recovery actions on highly stressed cores. The calculated reliability metrics are utilized in runtime mapping of the newly arrived applications to maximize the performance of the system while fulfilling reliability requirements and the available power budget. Our extensive experimental results reveal that the proposed reliability-aware approach can efficiently select the processing cores to be used over time in order to enhance the reliability at the end of the operational life (up to 62%) while offering the comparable performance level of the state-of-the-art runtime mapping approach.

KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland.
A Power-Aware Approach for Online Test Scheduling in Many-Core Architectures2016In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 65, no 3, p. 730-743Article in journal (Refereed)

Aggressive technology scaling triggers novel challenges to the design of multi-/many-core systems, such as limited power budget and increased reliability issues. Today's many-core systems employ dynamic power management and runtime mapping strategies trying to offer optimal performance while fulfilling power constraints. On the other hand, due to the reliability challenges, online testing techniques are becoming a necessity in current and near future technologies. However, state-of-the-art techniques are not aware of the other power/performance requirements. This paper proposes a power-aware non-intrusive online testing approach for many-core systems. The approach schedules software based self-test routines on the various cores during their idle periods, while honoring the power budget and limiting delays in the workload execution. A test criticality metric, based on a device aging model, is used to select cores to be tested at a time. Moreover, power and reliability issues related to the testing at different voltage and frequency levels are also handled. Extensive experimental results reveal that the proposed approach can i) efficiently test the cores within the available power budget causing a negligible performance penalty, ii) adapt the test frequency to the current cores' aging status, and iii) cover available voltage and frequency levels during the testing.

KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. Turku Univ.. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Adaptive Fault Simulation on Many-core Microprocessor Systems2015In: PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFTS), IEEE Computer Society, 2015, p. 151-154Conference paper (Refereed)

Efficiency of Network-on-Chip based many-core microprocessors to implement parallel fault simulation methods for different circuit sizes is explored in this paper. We show that a naive and straightforward execution of fault simulation programs on such systems does not provide the maximum speedup due to severe bottlenecks in off-chip shared memory access at memory controllers. In order to exploit the available massive parallelism of homogenous many-core microprocessors, a runtime approach capable of adaptively balancing the load during the fault simulation process is proposed. We demonstrate the proposed adaptive fault simulation approach on a many-core platfonn, Intels Single-chip Cloud Computer showing up to 45X speedup compared to a serial fault simulation approach.

• 26.
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku (UTU), Finland. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
A Programmable Low Power Current Source for Bioimpedance Measurement: Towards a Wearable Personalized Health2015In: 2015 37th Annual International Conference of The IEEE ENGINEERING in Medicine and Biology Society (EMBC), 2015, p. 2038-2042Conference paper (Refereed)

Bioimpedance is a noninvasive measurement method that facilitates body composition analysis, besides being indicative of many other health parameters. In this work a novel programmable, low complexity, high output impedance, high voltage compliance and wideband current source for bioimpedance applications is presented. Previously, we designed, fabricated and tested in vivo a bio-patch for acquisition of multiple bio-signals [1]. Upon integration with our previous work, this circuit is envisioned to constitute part of a personalized health assistant. Simulation at worst case corners and real operation conditions was carried out using UMC-180 nm 1 poly 6 metal CMOS process. Full duty cycle, shortened or stepped square waves can be generated. Amplitude control of 8 different current levels is supported. Frequency can be tuned up to 1 MHz and an output impedance of 2.8 MO @ 250 KHz is achieved at full current capacity. Total current consumption is comparable to the injected current, making the circuit highly efficient.

• 27. Hiremath, S.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
Wearable Internet of Things: Concept, architectural components and promises for person-centered healthcare2015In: Proceedings of the 2014 4th International Conference on Wireless Mobile Communication and Healthcare - "Transforming Healthcare Through Innovations in Mobile and Wireless Technologies", MOBIHEALTH 2014, 2015, p. 304-307Conference paper (Refereed)

The proliferation of mobile devices, ubiquitous internet, and cloud computing has sparked a new era of Internet of Things (IoT), thus allowing researchers to create application-specific solutions based on the interconnection between physical objects and the internet. Recently, wearable devices are rapidly emerging and forming a new segment-'Wearable IoT (WIoT)' due to their capability of sensing, computing and communication. Future generations of WIoT promise to transform the healthcare sector, wherein individuals are seamlessly tracked by wearable sensors for personalized health and wellness information-body vital parameters, physical activity, behaviors, and other critical parameters impacting quality of daily life. This paper presents an effort to conceptualize WIoT in terms of their design, function, and applications. We discuss the building blocks of WIoT-including wearable sensors, internet-connected gateways and cloud and big data support-that are key to its future success in healthcare domain applications. We also present a new system science for WIoT that suggests future directions, encompassing operational and clinical aspects.

• 28.
KTH, School of Information and Communication Technology (ICT).
KTH, School of Information and Communication Technology (ICT). KTH, School of Information and Communication Technology (ICT). KTH, School of Information and Communication Technology (ICT). KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. Fudan University, China . KTH, School of Information and Communication Technology (ICT). KTH, School of Information and Communication Technology (ICT). KTH, School of Information and Communication Technology (ICT). KTH, School of Information and Communication Technology (ICT).
Biofeedback neuromuscular electrical stimulation front-end for dysphagia treatment2014In: IEEE 2014 Biomedical Circuits and Systems Conference, BioCAS 2014 - Proceedings, IEEE Press, 2014, p. 612-615Conference paper (Refereed)

A dedicated front-end for biofeedback neuromuscular electrical stimulation (NESM) system is proposed. For controllable dysphagia treatment, the integrated circuit (IC) provides a stimulator front-end with programmable stimulation parameters (2μA-1mA current amplitude, DC-2KHz frequency, and variable duty cycle) and an electromyogram/impedance (EMG/ETI) readout front-end with programmable gain and bandwidth (42-80dB, 0.1Hz-1.2KHz) for biofeedback. Area-efficient, low-power but high precision current controlling is achieved by inducing the sigma-delta modulator technique in the stimulation channel. The measured impedance and EMG signal are used to determine the stimulation parameters, enabling a closed loop optimized treatment. The proposed front-end is fabricated in a 0.18 μm standard CMOS process technology and dissipates a peak power of 2.3 mW at the supply voltage of 1.8 V. Measurement results on a live person are also provided to validate the system's effectiveness.

• 29. Huan, Yuxiang
KTH, School of Information and Communication Technology (ICT). KTH, School of Information and Communication Technology (ICT), Electronic Systems. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
A 61 μa/MHz reconfigurable application-specific processor and system-on-chip for Internet-of-Things2016In: International System on Chip Conference, IEEE Computer Society, 2016, p. 235-239Conference paper (Refereed)

This paper presents a SoC design that combines general purpose control and application-specific acceleration within a reconfigurable ASIP core for Internet-of-Things applications. Sufficient processing capability and re-configurability are provided by highly customizable data path and efficient sequence control loop. By fully utilizing the data path of proposed architecture, the processor significantly reduces >4X code size and offers superior performance compared with MSP430 and Atmega128 in FIR and Whetstone benchmarks. More than 10X speedup can be obtained in executing encryption algorithms by optimized micro-instructions without extra hardware accelerators. Fabricated in 0.18 μm CMOS, our SoC's energy efficiency beats most of the microcontrollers with a value as low as 61 μA/MHz.

• 30. Huang, L.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland.
Tolerating transient illegal turn faults in NoCs2016In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 43, no SI, p. 104-115Article in journal (Refereed)

Network-on-Chip (NoC) is becoming a competitive solution to connect hundreds of processing elements in modern computing platforms. Under the trend of shrinking feature sizes, circuits are likely to suffer from faults which lead to degraded performance and erroneous behaviour. Compared to permanent faults, transient faults happen even more frequently and seriously while they are hidden within complex on chip behaviours. One of the serious consequences caused by transient faults is taking illegal turns by the packets after the damage of control logic in on-chip routers which may lead to a deadlock situation and eventually crashing the entire system. To avoid this situation, in this paper, we propose a comprehensive scheme called ODT including an improved router architecture, an illegal-turn-resilient routing algorithm, online fault-detect units and a fault classification method. By applying ODT, more turns are supported on routing level and the deadlock situations can be significantly reduced. Experimental results indicate up to 22% increase of the survived packets in the network when 4% of routing computation units in failure. The extra area overhead and power consumption of ODT method is around 9.22% and 9.63%.

• 31. Huang, Letian
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems.
Non-Blocking Testing for Network-on-Chip2016In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 65, no 3, p. 679-692Article in journal (Refereed)

To achieve high reliability in on-chip networks, it is necessary to test the network as frequently as possible to detect physical failures before they lead to system-level failures. A main obstacle is that the circuit under test has to be isolated, resulting in network cuts and packet blockage which limit the testing frequency. To address this issue, we propose a comprehensive network-level approach which could test multiple routers simultaneously at high speed without blocking or dropping packets. We first introduce a reconfigurable router architecture allowing the cores to keep their connections with the network while the routers are under test. A deadlock-free and highly adaptive routing algorithm is proposed to support reconfigurations for testing. In addition, a testing sequence is defined to allow testing multiple routers to avoid dropping of packets. A procedure is proposed to control the behavior of the affected packets during the transition of a router from the normal to the testing mode and vice versa. This approach neither interrupts the execution of applications nor has a significant impact on the execution time. Experiments with the PARSEC benchmarks on an 8x8 NoC-based chip multiprocessors show only 3 percent execution time increase with four routers simultaneously under test.

• 32. Jafri, Syed M. A. H.
KTH. KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Architecture and Implementation of Dynamic Parallelism, Voltage and Frequency Scaling (PVFS) on CGRAs2015In: ACM Journal on Emerging Technologies in Computing Systems, ISSN 1550-4832, Vol. 11, no 4, article id 40Article in journal (Refereed)

In the era of platforms hosting multiple applications with arbitrary performance requirements, providing a worst-case platform-wide voltage/frequency operating point is neither optimal nor desirable. As a solution to this problem, designs commonly employ dynamic voltage and frequency scaling (DVFS). DVFS promises significant energy and power reductions by providing each application with the operating point (and hence the performance) tailored to its needs. To further enhance the optimization potential, recent works interleave dynamic parallelism with conventional DVFS. The induced parallelism results in performance gains that allow an application to lower its operating point even further (thereby saving energy and power consumption). However, the existing works employ costly dedicated hardware (for synchronization) and rely solely on greedy algorithms to make parallelism decisions. To efficiently integrate parallelism with DVFS, compared to state-of-the-art, we exploit the reconfiguration (to reduce DVFS synchronization overheads) and enhance the intelligence of the greedy algorithm (to make optimal parallelism decisions). Specifically, our solution relies on dynamically reconfigurable isolation cells and an autonomous parallelism, voltage, and frequency selection algorithm. The dynamically reconfigurable isolation cells reduce the area overheads of DVFS circuitry by configuring the existing resources to provide synchronization. The autonomous parallelism, voltage, and frequency selection algorithm ensures high power efficiency by combining parallelism with DVFS. It selects that parallelism, voltage, and frequency trio which consumes minimum power to meet the deadlines on available resources. Synthesis and simulation results using various applications/algorithms (WLAN, MPEG4, FFT, FIR, matrix multiplication) show that our solution promises significant reduction in area and power consumption (23% and 51%) compared to state-of-the-art.

• 33. Jafri, Syed M. A. H.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Private reliability environments for efficient fault-tolerance in CGRAs2014In: Design automation for embedded systems, ISSN 0929-5585, E-ISSN 1572-8080, Vol. 18, no 3-4, p. 295-327Article in journal (Refereed)

In the era of platforms hosting multiple applications with variable reliability needs, worst-case platform-wide fault-tolerance decisions are neither optimal nor desirable. As a solution to this problem, designs commonly employ adaptive fault-tolerance strategies that provide each application with the reliability level actually needed. However, in the CGRA domain, the existing schemes either only allow to shift between different levels of modular redundancy (duplication, triplication, etc.) or protect only a particular region of a device (e.g. configuration memory, computation, or data memory). To complement these strategies, we propose private fault-tolerance environments which, in addition to modular redundancy, also provide low cost sub-modular (e.g. residue mod 3) redundancy capable of handling both permanent and temporary faults in configuration memory, computation, communication, and data memory. In addition, we also present adaptive configuration scrubbing techniques which prevent fault accumulation in the configuration memory. Simulation results using a few selected algorithms (FFT, matrix multiplication, and FIR filter) show that the approach proposed is capable of providing flexible protection with energy overhead ranging from 3.125 % to 107 % for different reliability levels. Synthesis results have confirmed that the proposed architecture reduces the area overhead for self-checking (58 %) and fault-tolerant (7.1 %) versions, compared to the state of the art adaptive reliability techniques.

• 34.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku, Finland.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku, Finland. KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku, Finland. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Customizable Compression Architecture for Efficient Configuration in CGRAs2011In: Proceedings: 2014 IEEE 22nd International Symposium on Field-Programmable Custom Computing Machines, FCCM 2014, 2011, p. 31-31Conference paper (Refereed)

Today, Coarse Grained Reconfigurable Architectures (CGRAs) host multiple applications. Novel CGRAs allow each application to exploit runtime parallelism and time sharing. Although these features enhance the power and silicon efficiency, they significantly increase the configuration memory overheads. As a solution to this problem researchers have employed statistical compression, intermediate compact representation, and multicasting. Each of these techniques has different properties, and is therefore best suited for a particular class of applications. However, existing research only deals with these methods separately. In this paper we propose a morphable compression architecture that interleaves these techniques in a unique platform.

• 35.
KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. University of Turku, Finland.
KTH. KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Polymorphic Configuration Architecture for CGRAs2016In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 24, no 1, p. 403-407Article in journal (Refereed)

In the era of platforms hosting multiple applications with arbitrary reconfiguration requirements, static configuration architectures are neither optimal nor desirable. The static reconfiguration architectures either incur excessive overheads or cannot support advanced features (like time-sharing and runtime parallelism). As a solution to this problem, we present a polymorphic configuration architecture (PCA) that provides each application with a configuration infrastructure tailored to its needs.

• 36. Javed, Nimra
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland.
Directly Printable Moisture Sensor Tag for Intelligent Packaging2016In: IEEE Sensors Journal, ISSN 1530-437X, E-ISSN 1558-1748, Vol. 16, no 16, p. 6147-6148Article in journal (Refereed)

A compact, flexible 24-b dual-polarized chip-less radio frequency identification tag with a size of 20.6mm x 19.9mm is realized. The tag structure is optimized and analyzed for Taconic, Kapton HN and organic substrate. The prototype fabricated on HP photopaper with silver nanoparticles-based conductive ink is exhibiting a behavior of moisture sensor. The proposed moisture sensor tag has a bandwidth of 13.5GHz. The direct printability of moisture sensor tag makes it suitable for intelligent packaging and various low-cost applications.

• 37. Javeda, Nimra
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
16-bit frequency signatured directly printable tag for organic electronics2016In: IEICE Electronics Express, ISSN 1349-2543, E-ISSN 1349-2543, Vol. 13, no 11, article id 20160406Article in journal (Refereed)

A compact 16-bit chipless RFID moisture sensor tag with a size of 13.2 x 19.6mm(2) is designed, fabricated and analyzed. The presented moisture sensor tag is realized on a paper substrate with silver nano particle based ink patches as conducting material. The frequency band of operation is 0.5 to 14 GHz having an overall bandwidth of 13.5 GHz. It is loaded with slots of different lengths and widths, etched on the conductive material. The tag exhibits stable sensing characteristic towards moisture in the real environment. The flexible, sensitive and environmental friendly nature of the proposed tag makes it suitable for wider, low-cost and organic electronics applications.

• 38.
KTH, School of Technology and Health (STH).
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Technology and Health (STH). KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
A User-friendly Wearable Device Based on Plastic Substrate for Heart Disease Monitoring2015In: the 4th International Conference on Computational & Mathematical Biomedical Engineering (CMBE2015), 2015Conference paper (Refereed)
• 39. Jiang, M.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. University of Turku, Finland.
Facial expression recognition with sEMG method2015In: Proceedings - 15th IEEE International Conference on Computer and Information Technology, CIT 2015, 14th IEEE International Conference on Ubiquitous Computing and Communications, IUCC 2015, 13th IEEE International Conference on Dependable, Autonomic and Secure Computing, DASC 2015 and 13th IEEE International Conference on Pervasive Intelligence and Computing, PICom 2015, Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 981-988Conference paper (Refereed)

Facial expression recognition has broad application prospects in the fields of psychological study, nursing care, Human Computer Interaction as well as affective computing. The method with surface Electromyogram (sEMG), which is one of vital bio-signals, has its superiority in several aspects such as high temporal resolution and data processing efficiency over other methods. Researches regarding EMG signal to study emotional expression have started since the second half of last century. Meanwhile, studies on myoelectrical control systems focusing on the computation of bio-signal processing and data analysis have been blooming in the recent twenty years. To have a comprehensive view of utilizing facial sEMG method, a systematic review is presented in this paper for facial expression recognition from experiment design to measurement systems, and data analysis steps.

• 40. Jiang, Mingzhe
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
IoT-based Remote Facial Expression Monitoring System with sEMG Signal2016In: 2016 IEEE SENSORS APPLICATIONS SYMPOSIUM (SAS 2016) PROCEEDINGS, IEEE, 2016, p. 211-216Conference paper (Refereed)

Biopotentials including Electrocardiography (ECG), Electromyography (EMG) and Electroencephalography (EEG) measure the activity of heart, muscles and brain, respectively. They can be used for noninvasive diagnostic applications, assistance in rehabilitation medicine and human-computer interaction. The concept of Internet of Things (IoT) can bring added value to applications with biopotential signals in healthcare and human-computer interaction by integrating multiple technologies such as sensors, wireless communication and data science. In this work, we present a wireless biopotentials remote monitoring and processing system. A prototype with the case study of facial expression recognition using four channel facial sEMG signals is implemented. A multivariate Gaussian classifier is trained offline from one person's surface EMG (sEMG) signals with four facial expressions: neutral, smile, frown and wrinkle nose. The presented IoT application system is implemented on the basis of an eight channel biopotential measurement device, Wi-Fi module as well as signal processing and classification provided as a Cloud service. In the system, the real-time sEMG data stream is filtered, feature extracted and classified within each data segment and the processed data is visualized in a browser remotely together with the classification result.

• 41. Jin, Han
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
A Mobile-Based High Sensitivity On-Field Organophosphorus Compounds Detecting System for IoT-Based Food Safety Tracking2017In: Journal of Sensors, ISSN 1687-725X, E-ISSN 1687-7268, article id 8797435Article in journal (Refereed)

A mobile-based high sensitivity absorptiometer is presented to detect organophosphorus (OP) compounds for Internet-of-Things based food safety tracking. This instrument consists of a customized sensor front-end chip, LED-based light source, low power wireless link, and coin battery, along with a sample holder packaged in a recycled format. The sensor front-end integrates optical sensor, capacitive transimpedance amplifier, and a folded-reference pulse width modulator in a single chip fabricated in a 0.18 mu m 1-poly 5-metal CMOS process and has input optical power dynamic range of 71 dB, sensitivity of 3.6 nW/cm(2) (0.77 pA), and power consumption of 14.5 mu W. Enabled by this high sensitivity sensor front-end chip, the proposed absorptiometer has a small size of 96 cm(3), with features including on-field detection and wireless communication with a mobile. OP compound detection experiments of the handheld system demonstrate a limit of detection (LOD) of 0.4 mu mol/L, comparable to that of a commercial spectrophotometer. Meanwhile, an android-based application (APP) is presented which makes the absorptiometer access to the Internet-of-Things (IoT).

• 42. Kanduri, A.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Predictable Application Mapping for Manycore Real-Time and Cyber-Physical Systems2015In: Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015, 2015, p. 135-142Conference paper (Refereed)

Cyber Physical Systems (CPS) are typically implemented on multicore platforms to handle computational pressure and performance requirements. Complex data flows in those applications cause contention among networked processors, resulting in unpredictable performance. In this work, we explore the impact of application mapping on network contention and predictability. A mapping algorithm focusing on minimizing the number of shared paths while not worsening the total path count is proposed. This algorithm is verified against other recent works over synthetic and realistic traffic patterns. The proposed algorithm considerably improved predictability with 0% shared paths and reasonable latency constraints compared to the other recently proposed algorithms.

• 43. Kanduri, Anil
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Approximation Knob: Power Capping Meets Energy Efficiency2016In: 2016 IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD), Institute of Electrical and Electronics Engineers (IEEE), 2016Conference paper (Refereed)

Power Capping techniques are used to restrict power consumption of computer systems to a thermally safe limit. Current many-core systems employ dynamic voltage and frequency scaling (DVFS), power gating (PG) and scheduling methods as actuators for power capping. These knobs are oriented towards power actuation, while the need for performance and energy savings are increasing in the dark silicon era. To address this, we propose approximation (APPX) as another knob for close-looped power management, lending performance and energy efficiency to existing power capping techniques. We use approximation in a pro-active way for long-term performance-energy objectives, complementing the short-term reactive power objectives. We implement an approximation-enabled power management framework, APPEND, that dynamically chooses an application with appropriate level of approximation from a set of variable accuracy implementations. Subject to the system dynamics, our power manager chooses an effective combination of knobs APPX, DVFS and PG, in a hierarchical way to ensure power capping with performance and energy gains. Our proposed approach yields 1.5x higher throughput, improved latency upto 5x, better performance per energy and dark silicon mitigation compared to state-of-the-art power management techniques over a set of applications ranging from high to no error resilience.

• 44. Karimi, E.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Accelerated On-chip Communication Test Methodology Using a Novel High-Level Fault Model2015In: Proceedings - IEEE 9th International Symposium on Embedded Multicore/Manycore SoCs, MCSoC 2015, Institute of Electrical and Electronics Engineers (IEEE), 2015, p. 283-288Conference paper (Refereed)

A novel high-level fault model to accelerate test process of on-chip communication structures for SoCs is proposed. To this end, bus components are modeled using a simple, yet efficient, graph-based technique and all possible faults on the graph nodes are probed. The proposed method is optimized in terms of test time. The method applies the same test process to all interconnects and components. Compared to the conventional stuck-at fault testing methods, our extensive simulations on the AMBA-AHB bus architecture reveal that our test method can help in achieving a significant test speed improvement. © 2015 IEEE.

• 45. Khan, U. H.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
A novel asterisk-shaped circularly polarized RFID tag for on-metal applications2016In: Applied Computational Electromagnetics Society Journal, ISSN 1054-4887, Vol. 31, no 9, p. 1035-1042Article in journal (Refereed)

An asterisk-shaped, metal-mountable RFID tag with a minuscule footprint is presented. The proposed design makes use of multiple asymmetric slots patterned in a cross-shaped fashion to achieve circular polarization. The structure is excited capacitively using a terminally-grounded, T-shaped feed line positioned within the slots. This peculiar arrangement permits the attainment of circular polarized radiation characteristics over a wide band of operation. Impedance matching, antenna size reduction and read range enhancement are the additional advantages offered by the embedded feed line. The final design is realized on a commercially available FR-4 substrate over dimensions of 40 x 40 mm2 yielding an impedance bandwidth and an axial ratio bandwidth of 37 MHz and 20 MHz, respectively. Improvement in antenna gain (and consequently in the read range) is reported upon mounting the tag on metallic surfaces.

• 46. Khan, Umar Hasan
KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. University of Turku, Finland.
Compact RFID Enabled Moisture Sensor2016In: Radioengineering, ISSN 1210-2512, E-ISSN 1805-9600, Vol. 25, no 3, p. 449-456Article in journal (Refereed)

This research proposes a novel, low-cost RFID tag sensor antenna implemented using commercially available Kodak photo-paper. The aim of this paper is to investigate the possibility of stable, RFID centric communication under varying moisture levels. Variation in the frequency response of the RFID tag in presence of moisture is used to detect different moisture levels. Combination of unique jaw shaped contours and T-matching network is used for impedance matching which results in compact size and minimal ink consumption. Proposed tag is 1.4x9.4 cm(2) in size and shows optimum results for various moisture levels upto 45 % in FCC band with a bore sight read range of 12.1 m.

• 47. Ling, Li
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. Fudan Univ, Peoples R China.
Precisely Controlled Hydration Water for Performance Improvement of Organic-Inorganic Perovskite Solar Cells2016In: Advanced Functional Materials, ISSN 1616-301X, E-ISSN 1616-3028, Vol. 26, no 28, p. 5028-5034Article in journal (Refereed)

Recently, intensive studies on the role of water molecule in the formation of organic-inorganic perovskite film have been reported. However, not only the contradictive phenomena but also the complex processing technique has hindered the widespread use of water molecule in perovskite preparation. Here the hydration water is introduced into the precursors instead of water. By precisely controlling the content of hydration water, a smoother and more uniform perovskite film is obtained through a simple one-step spin coating method. The improvement of perovskite film quality leads to highly efficient planar perovskite solar cells. Summing up the device studies and the investigation of morphology, crystallization, and optical properties, the impact of water molecule in the formation of perovskite crystal and consequences of device performance is understood. Due to its universal adaptability and simplified process, precise control of hydration water is therefore of great utility to high quality perovskite films fabrication and large-scale production of this upcoming photovoltaic technology.

• 48.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK.
Ultra-low-power Design and Implementation of Application-specific Instruction-set Processors for Ubiquitous Sensing and Computing2015Doctoral thesis, comprehensive summary (Other academic)

The feature size of transistors keeps shrinking with the development of technology, which enables ubiquitous sensing and computing. However, with the break down of Dennard scaling caused by the difficulties for further lowering supply voltage, the power density increases significantly. The consequence is that, for a given power budget, the energy efficiency must be improved for hardware resources to maximize the performance. Application-specific integrated circuits (ASICs) obtain high energy efficiency at the cost of low flexibility for various applications, while general-purpose processors (GPPs) gain generality at the expense of efficiency.

To provide both high energy efficiency and flexibility, this dissertation explores the ultra-low-power design of application-specific instruction-set processors (ASIP) for ubiquitous sensing and computing. Two application scenarios, i.e. high-throughput compute-intensive processing for multimedia and low-throughput low-cost processing for Internet of Things (IoT) are implemented in the proposed ASIPs.

Multimedia stream processing for human-computer interaction is always featured with high data throughput. To design processors for networked multimedia streams, customizing application-specific accelerators controlled by the embedded processor is exploited. By abstracting the common features from multiple coding algorithms, video decoding accelerators are implemented for networked multi-standard multimedia stream processing. Fabricated in 0.13 $\mu$m CMOS technology, the processor running at 216 MHz is capable of decoding real-time high-definition video streams with power consumption of 414 mW.

When even higher throughput is required, such as in multi-view video coding applications, multiple customized processors will be connected with an on-chip network. Design problems are further studied for selecting the capability of single processors, the number of processors, the capacity of communication network, as well as the task assignment schemes.

In the IoT scenario, low processing throughput but high energy efficiency and adaptability are demanded for a wide spectrum of devices. In this case, a tile processor including a multi-mode router and dual cores is proposed and implemented. The multi-mode router supports both circuit and wormhole switching to facilitate inter-silicon extension for providing on-demand performance. The control-centric dual-core architecture uses control words to directly manipulate all hardware resources. Such a mechanism avoids introducing complex control logics, and the hardware utilization is increased. Programmable control words enable reconfigurability of the processor for supporting general-purpose ISAs, application-specific instructions and dedicated implementations. The idea of reducing global data transfer also increases the energy efficiency. Finally, a single tile processor together with network of bare dies and network of packaged chips has been demonstrated as the result. The processor implemented in 65 nm low leakage CMOS technology and achieves the energy efficiency of 101.4 GOPS/W for each core.

• 49.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
A 2-mW Multi-mode Router Design with Dual-core Processor in 65 nm LL CMOS for Inter-silicon Communication2015Manuscript (preprint) (Other academic)
• 50.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics. KTH, School of Information and Communication Technology (ICT), Electronics and Embedded Systems. KTH, School of Information and Communication Technology (ICT), Industrial and Medical Electronics.
Design and Implementation of Multi-mode Routers for Large-scale Inter-core Networks2016In: Integration, ISSN 0167-9260, E-ISSN 1872-7522, Vol. 53, p. 1-13Article in journal (Other academic)

Constructing on-chip or inter-silicon (inter-die/inter-chip) networks to connect multiple processors extends the system capability and scalability. It is a key issue to implement a flexible router that can fit into various application scenarios. This paper proposes a multi-mode adaptable router that can support both circuit and wormhole switching with supplying flexible working strategies for specific traffic patterns in diverse applications. The limitation of mono-mode switched routers is shown at first, followed by algorithm exploration in the proposed router for choosing the proper working strategy in a specific network. We then present the performance improvement when applying the mixed circuit/wormhole switching mode to different applications, and analyze the image decoding as a case study. The multi-mode router has been implemented with different configurations in a 65 nm CMOS technology. The one with 8-bit flit width is demonstrated together with a multi-core processor to show the feasibility. Working at 350 MHz, the average power consumption of the whole system is 22 mW.

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