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  • 1. Aldinucci, Marco
    et al.
    Brorsson, Mats
    KTH, School of Information and Communication Technology (ICT), Software and Computer systems, SCS.
    D'Agostino, Daniele
    Daneshtalab, Masoud
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems.
    Kilpatrick, Peter
    Leppanen, Ville
    Preface2017In: The international journal of high performance computing applications, ISSN 1094-3420, E-ISSN 1741-2846, Vol. 31, no 3, p. 179-180Article in journal (Refereed)
  • 2.
    Chen, Dejiu
    et al.
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems.
    A methodological framework for model-based self-management of services and components in dependable cyber-physical systems2017In: 12th International Conference on Dependability and Complex Systems, DepCoS-RELCOMEX 2017, Springer, 2017, Vol. 582, p. 97-105Conference paper (Refereed)
    Abstract [en]

    Modern automotive vehicles featuring ADAS (Advanced Driving Assistant Systems) and AD (Autonomous Driving) represent one category of dependable CPS (Cyber-Physical Systems). For such systems, the adaptation of generic purpose COTS (Commercial-Off-The-Shelf) services and components has been advocated in the industry as a necessary means for shortening the innovation loops and enabling efficient product evolution. This will however not be a trivial task due to the system safety- and time-criticality. This calls on one hand for formal specification of systems, and on the other hand for a systematic approach to module design, supervision and adaptions. Accordingly, we propose in this paper a novel method that emphasizes an integration of system models, formal contracts, and embedded services for effective self-management of COTS. The key modeling technologies include the EAST-ADL for formal system description and the A-G contract theory for module specification.

  • 3.
    Chen, DeJiu
    et al.
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Embedded Control Systems.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems.
    A Model-based Approach to Dynamic Self-Assessment for Automated Performance and Safety Awareness of Cyber-Physical Systems2017In: Model-Based Safety and Assessment - 5th International Symposium, Trento, Italy, September 11–13, 2017 / [ed] Marco Bozzano, Yiannis Papadopoulos, Springer, 2017, Vol. LNCS 10437, p. 227-240Conference paper (Refereed)
    Abstract [en]

    Modern automotive vehicles represent one category of CPS (Cyber-Physical Systems) that are inherently time- and safety-critical. To justify the actions for quality-of-service adaptation and safety assurance, it is fundamental to perceive the uncertainties of system components in operation, which are caused by emergent properties, design or operation anomalies. From an industrial point of view, a further challenge is related to the usages of generic purpose COTS (Commercial-Off-The-Shelf) components, which are separately developed and evolved, often not sufficiently verified and validated for specific automotive contexts. While introducing additional uncertainties in regard to the overall system performance and safety, the adoption of COTS components constitutes a necessary means for effective product evolution and innovation. Accordingly, we propose in this paper a novel approach that aims to enable advanced operation monitoring and self-assessment in regard to operational uncertainties and thereby automated performance and safety awareness. The emphasis is on the integration of several modeling technologies, including the domain-specific modeling framework EAST-ADL, the A-G contract theory and Hidden Markov Model (HMM). In particular, we also present some initial concepts in regard to the usage performance and safety awareness for quality-of-service adaptation and dynamic risk mitigation.

  • 4.
    Chen, Xiamen
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems. National University of Defense Technology, China.
    Lu, Zhonghai
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems.
    Lei, Yuanwu
    Wang, Yaohua
    Chen, Shenggang
    Multi-bit Transient Fault Control for NoC Links Using 2D Fault Coding Method2016In: 2016 TENTH IEEE/ACM INTERNATIONAL SYMPOSIUM ON NETWORKS-ON-CHIP (NOCS), IEEE, 2016Conference paper (Refereed)
    Abstract [en]

    In deep nanometer scale, Network-on-Chip (NoC) links are more prone to multi-bit transient fault. Conventional ECC techniques brings heavy area, power, and timing overheads when correcting and detecting multiple transient faults. Therefore, a cost-effective ECC technique, named 2D fault coding method, is adopted to overcome the multi-bit transient fault issue of NoC links. Its key innovation is that the wires of a link are treated as its matrix appearance and light-weight Parity Check Coding (PCC) is performed on the matrix's two dimensions (horizontal matrix rows and vertical matrix columns). Horizontal PCCs and vertical PCCs work together to find the faults' position and then correct them by simply inverting them. The procedure of using the 2D fault coding method to protect a NoC link is proposed, its correction and detection capability is analyzed, and its hardware implementation is carried out. Comparative experiments show that the proposal can largely reduce the ECC hardware cost, have much higher fault detection coverage, maintain almost zero silent fault percentages, and have higher fault correction percentages normalized under the same area, demonstrating that it is cost-effective and suitable to the multi-bit transient fault control for NoC links.

  • 5.
    Ebrahimi, Masoumeh
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems.
    Daneshtalab, Masoud
    MDH.
    EbDa: A New Theory on Design and Verification of Deadlock-free Interconnection Networks2017In: In Proceedings of ISCA ’17, ACM Press, 2017, p. 1-13Conference paper (Refereed)
    Abstract [en]

    Freedom from deadlock is one of the most important issues whendesigning routing algorithms in on-chip/off-chip networks. Manyworks have been developed upon Dally’s theory proving that a networkis deadlock-free if there is no cyclic dependency on the channeldependency graph. However, finding such acyclic graph has beenvery challenging, which limits Dally’s theory to networks with a lownumber of channels. In this paper, we introduce three theorems thatdirectly lead to routing algorithms with an acyclic channel dependencygraph.We also propose the partitioning methodology, enablinga design to reach the maximum adaptiveness for the n-dimensionalmesh and k-ary n-cube topologies with any given number of channels.In addition, deadlock-free routing algorithms can be derivedranging from maximally fully adaptive routing down to deterministicrouting. The proposed theorems can drastically remove thedifficulties of designing deadlock-free routing algorithms.

  • 6.
    Kyriakakis, Eleftherios
    et al.
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems.
    Ngo, Kalle
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems.
    Öberg, Johnny
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems.
    Implementation of a Fault-Tolerant, Globally-Asynchronous-Locally-Synchronous, Inter-Chip NoC Communication Bridge on FPGAs2017In: 2017 IEEE NORDIC CIRCUITS AND SYSTEMS CONFERENCE (NORCAS): NORCHIP AND INTERNATIONAL SYMPOSIUM OF SYSTEM-ON-CHIP (SOC) / [ed] Nurmi, J Vesterbacka, M Wikner, JJ Alvandpour, A NielsenLonn, M Nielsen, IR, IEEE , 2017Conference paper (Refereed)
    Abstract [en]

    Network-on-Chip (NoC) architectures were introduced to help mitigate the bottleneck and scalability issues faced by the traditional bus interconnect in Multi-Processor System-On Chip (MPSoC). Nowadays, many embedded systems host a significant number of micro-controllers and processors (i.e. vehicles, airplanes, satellites, etc.) and as this number continues to increase, traditional bus solutions will start to fail on those platforms as well. NoCs not only offer a scalable solution for MPSoC interconnects but they can also provide a uniform platform of communication to embedded systems with multiple off-chip, often heterogeneous, processors. This leads to the need for investigation on inter-chip communication bridges suitable for transmitting flits/packets across chips and possibly across clock domains. This paper investigates an inter-chip communication link, of an MPSoC NoC architecture which is extended with an off-chip, heterogeneous processor (node) and proposes a scalable, fault-tolerant, globally asynchronous locally synchronous bridge for inter-chip communication. The proposed bridge is implemented on a prototype board of the SEUD KTH experiment where it successfully enables the communication of a NoC distributed over two FPGAs. The inter-chip bridge is verified in-circuit achieving transfer speeds up to 24 MByte/s (approximate to 1.5 Mflit/s) and its ability to correct single bit errors is demonstrated in simulation.

  • 7.
    Lu, Zhonghai
    et al.
    KTH, School of Information and Communication Technology (ICT), Elektronics, Electronic and embedded systems.
    Yao, Yuan
    KTH, School of Information and Communication Technology (ICT), Elektronics, Electronic and embedded systems.
    Aggregate flow-based performance fairness in CMPs2016In: ACM Transactions on Architecture and Code Optimization (TACO), ISSN 1544-3566, E-ISSN 1544-3973, Vol. 13, no 4, article id 53Article in journal (Refereed)
    Abstract [en]

    In CMPs, multiple co-executing applications create mutual interference when sharing the underlying network-on-chip architecture. Such interference causes different performance slowdowns to different applications. To mitigate the unfairness problem, we treat traffic initiated from the same thread as an aggregate flow such that causal request/reply packet sequences can be allocated to resources consistently and fairly according to online profiled traffic injection rates. Our solution comprises three coherent mechanisms from rate profiling, rate inheritance, and rate-proportional channel scheduling to facilitate and realize unbiased workload-adaptive resource allocation. Full-system evaluations in GEM5 demonstrate that, compared to classic packet-centric and latest application-prioritization approaches, our approach significantly improves weighted speed-up for all multi-application mixtures and achieves nearly ideal performance fairness.

  • 8. Majd, A.
    et al.
    Troubitsyna, E.
    Daneshtalab, Masoud
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems.
    Safety-aware control of swarms of drones2017In: Computer Safety, Reliability, and Security: SAFECOMP 2017 Workshops, ASSURE, DECSoS, SASSUR, TELERISE, and TIPS, Trento, Italy, September 12, 2017, Proceedings, Springer, 2017, Vol. 10489, p. 249-260Conference paper (Refereed)
    Abstract [en]

    In this paper, we propose a novel approach to ensuring safety while planning and controlling an operation of swarms of drones. We derive the safety constraints that should be verified both during the mission planning and at the run-time and propose an approach to safety-aware mission planning using evolutionary algorithms. High performance of the proposed algorithm allows us to use it also at run-time to predict and resolve in a safe and optimal way dynamically emerging hazards. The benchmarking of the proposed approach validate its efficiency and safety.

  • 9. Momenzadeh, E.
    et al.
    Modarressi, M.
    Mazloumi, A.
    Daneshtalab, Masoud
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems. Mälardalen University (MDH), Sweden.
    Parallel forwarding for efficient bandwidth utilization in networks-on-chip2017In: 30th International Conference on Architecture of Computing Systems, ARCS 2017, Springer Verlag , 2017, p. 152-163Conference paper (Refereed)
    Abstract [en]

    Networks-on-chip (NoC) provide a scalable and power-efficient communication infrastructure for different computing chips, ranging from fully customized multi/many-processor systems-on-chip (MPSoCs) to general-purpose chip multiprocessors (CMPs). A common aspect in almost all NoC workloads is the varying size of data transmitted by each transaction: while large data blocks are transferred as multiple-flit packets, a part of the traffic consists of short data segment (control data) that does not even fill a single flit. In conventional NoCs, switch allocator assigns/ grants a switch output (and the link connected to it) to a single flit at each cycle, even if the flit is shorter than the link bit-width. In this paper, we propose a novel NoC architecture that enables routers to simultaneously send two short flits on the same link, effectively utilizing the link bandwidth that otherwise would be wasted. To this end, new crossbar, virtual channel (VC), and switch allocator architectures are presented to support parallel short packet forwarding on NoC links. Simulation results using synthetic and realistic workloads show that the proposed architecture improves the NoC performance by up to 24%.

  • 10. Rezaei, A.
    et al.
    Daneshtalab, Masoud
    KTH, School of Information and Communication Technology (ICT), Electronics, Electronic and embedded systems.
    Zhao, D.
    CAP-W: Congestion-aware platform for wireless-based network-on-chip in many-core era2017In: Microprocessors and microsystems, ISSN 0141-9331, E-ISSN 1872-9436, Vol. 52, p. 23-33Article in journal (Refereed)
    Abstract [en]

    In order to fulfill the ever-increasing demand for high-speed and high-bandwidth, wireless-based MCSoC is presented based on a NoC communication infrastructure. Inspiring the separation between the communication and the computation demands as well as providing the flexible topology configurations, makes wireless-based NoC a promising future MCSoC architecture. However, congestion occurrence in wireless routers reduces the benefit of high-speed wireless links and significantly increases the network latency. Therefore, in this paper, a congestion-aware platform, named CAP-W, is introduced for wireless-based NoC in order to reduce congestion in the network and especially over wireless routers. The triple-layer platform of CAP-W is composed of mapping, migration, and routing layers. In order to minimize the congestion probability, the mapping layer is responsible for selecting the suitable free core as the first candidate, finding the suitable first task to be mapped onto the selected core, and allocating other tasks with respect to contiguity. Considering dynamic variation of application behaviors, the migration layer modifies the primary task mapping to improve congestion situation. Furthermore, the routing layer balances utilization of wired and wireless networks by separating short-distance and long-distance communications. Experimental results show meaningful gain in congestion control of wireless-based NoC compared to state-of-the-art works.

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