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  • 1.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH.
    GOI fabrication for Monolithic 3D integrationIn: Article in journal (Other academic)
  • 2.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Germanium on Insulator Fabrication for Monolithic 3-D Integration2018In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed)
    Abstract [en]

    A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 3.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    GOI fabrication for monolithic 3D integration2018In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Institute of Electrical and Electronics Engineers (IEEE), 2018, Vol. 2018, p. 1-3Conference paper (Refereed)
    Abstract [en]

    A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 4.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH.
    Compressive-Strained Ge and Tensile-Strained SiGe on Insulator Fabrication via Wafer Bonding for Monolithic 3D IntegrationManuscript (preprint) (Other academic)
  • 5.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Fabrication of Group IV Semiconductors on Insulator for Monolithic 3D Integration2018Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The conventional 2D geometrical scaling of transistors is now facing many challenges in order to continue the performance enhancement while decreasing power consumption. The decrease in the device power consumption is related to the scaling of the power supply voltage (Vdd) and interconnects wiring length. In addition, monolithic three dimensional (M3D) integration in the form of vertically stacked devices, is a possible solution to increase the device density and reduce interconnect wiring length. Integrating strained germanium on insulator (sGeOI) pMOSFETs monolithically with strained silicon/silicon-germanium on insulator (sSOI/sSiGeOI) nMOSFETs can increase the device performance and packing density. Low temperature processing (<550 ºC) is essential as interconnects and strained layers limit the thermal budget in M3D. This thesis presents an experimental investigation of the low temperature (<450 ºC) fabrication of group IV semiconductor-on-insulator substrates with the focus on sGeOI and sSiGeOI fabrication processes compatible with M3D.

      To this aim, direct bonding was used to transfer the relaxed and strained semiconductor layers. The void formation dependencies of the oxide thickness, the surface treatment of the oxide and the post annealing time were fully examined. Low temperature SiGe epitaxy was investigated with the emphasis on the fabrication of Si0.5Ge0.5 strain-relaxed buffers (SRBs), etch-stop layer, and the device layer in the SiGeOI and GeOI process schemes. Ge epitaxial growth on Si as thick SRBs and thin device layers was investigated. Thick (500 nm-3 µm) and thin (<30 nm) relaxed GeOI substrates were fabricated. The latter was fabricated by continuous epitaxial growth of a 3-µm Ge (SRB)/Si0.5Ge0.5 (etch stop)/Ge (device layer) stack on Si. The fabricated long channel Ge pFETs from these GeOI substrates exhibit well-behaved IV characteristics with an effective mobility of 160 cm2/Vs.

      The planarization of SiO2 and SiGe SRBs for the fabrication of the strained GeOI and SiGeOI were accomplished by chemical mechanical polishing (CMP). Low temperature processes (<450 ºC) were developed for compressively strained GeOI layers (ɛ ~ -1.75 %, < 20 nm), which are used for high mobility and low power devices. For the first time, tensile strained Si0.5Ge0.5 (ɛ ~ 2.5 %, < 20 nm) films were successfully fabricated and transferred onto patterned substrates for 3D integration.

  • 6.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH.
    Low Temperature SiGe Epitaxy Using SiH4-GeH4and Si2H6-Ge2H6 Gas PrecursorsIn: Journal of Solid State Science and TechnologyArticle in journal (Other academic)
  • 7.
    Ayedh, H. M.
    et al.
    Norway.
    Nipoti, R.
    Italy.
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Svensson, B. G.
    Norway.
    Kinetics modeling of the carbon vacancy thermal equilibration in 4H-SiC2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, p. 233-236Conference paper (Refereed)
    Abstract [en]

    The carbon vacancy (VC) is a major limiting-defect of minority carrier lifetime in n-type 4H-SiC epitaxial layers and it is readily formed during high temperature processing. In this study, a kinetics model is put forward to address the thermodynamic equilibration of VC, elucidating the possible atomistic mechanisms that control the VC equilibration under C-rich conditions. Frenkel pair generation, injection of carbon interstitials (Ci’s) from the C-rich surface, followed by recombination with VC’s, and diffusion of VC’s towards the surface appear to be the major mechanisms involved. The modelling results show a close agreement with experimental deep-level transient spectroscopy (DLTS) depth profiles of VC after annealing at different temperatures.

  • 8.
    Azarov, Alexander
    et al.
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway.;Natl Ctr Nucl Res, A Soltana 7, PL-05400 Otwock, Poland..
    Aarseth, Bjorn L.
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
    Vines, Lasse
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Monakhov, Edouard
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
    Kuznetsov, Andrej
    Univ Oslo, Dept Phys, Ctr Mat Sci & Nanotechnol, POB 1048, N-0316 Oslo, Norway..
    Defect annealing kinetics in ZnO implanted with Zn substituting elements: Zn interstitials and Li redistribution2019In: Journal of Applied Physics, ISSN 0021-8979, E-ISSN 1089-7550, Vol. 125, no 7, article id 075703Article in journal (Refereed)
    Abstract [en]

    It is known that the behavior of residual Li in ion implanted ZnO depends on the preferential localization of the implants, in particular, forming characteristic Li depleted or Li pile-up regions for Zn or O sublattice occupation of the implants due to the corresponding excess generation of Zn and O interstitials in accordance with the so-called "+1 model." However, the present study reveals that conditions for the radiation damage annealing introduce additional complexity into the interpretation of the Li redistribution trends. Specifically, four implants residing predominantly in the Zn-sublattice, but exhibiting different lattice recovery routes, were considered. Analyzing Li redistribution trends in these samples, it is clearly shown that Li behavior depends on the defect annealing kinetics which is a strong function of the implanted fluence and ion species. Thus, Li depleted and Li pile-up regions (or even combinations of the two) were observed and correlated with the defect evolution in the samples. It is discussed how the observed Li redistribution trends can be used for better understanding a thermal evolution of point defects in ZnO and, in particular, energetics and migration properties of Zn interstitials.

  • 9.
    Becker, Matthias
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Lu, Zhonghai
    KTH, Superseded Departments (pre-2005), Electronic Systems Design. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Chen, DeJiu
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Machine Design (Div.). KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Embedded Control Systems. KTH, Superseded Departments (pre-2005), Machine Design. KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Towards QoS-Aware Service-Oriented Communication in E/E Automotive Architectures2018In: Proceedings of the 44th Annual Conference of the IEEE Industrial Electronics Society (IECON), 2018, p. 4096-4101Conference paper (Refereed)
    Abstract [en]

    With the raise of increasingly advanced driving assistance systems in modern cars, execution platforms that build on the principle of service-oriented architectures are being proposed. Alongside, service oriented communication is used to provide the required adaptive communication infrastructure on top of automotive Ethernet networks. A middleware is proposed that enables QoS aware service-oriented communication between software components, where the prescribed behavior of each software component is defined by Assume/Guarantee (A-G) contracts. To enable the use of COTS components, that are often not sufficiently verified for the use in automotive systems, the middleware monitors the communication behavior of components and verifies it against the components A/G contract. A violation of the allowed communication behavior then triggers adaption processes in the system while the impact on other communication is minimized. The applicability of the approach is demonstrated by a case study that utilizes a prototype implementation of the proposed approach.

  • 10.
    Becker, Matthias
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Mubeen, Saad
    Mälardalen University.
    Timing Analysis Driven Design-Space Exploration of Cause-Effect Chains in Automotive Systems2018In: IECON 2018 - 44th Annual Conference of the IEEE Industrial Electronics Society, 2018Conference paper (Refereed)
    Abstract [en]

    Model-based development and component-based software engineering have emerged as a promising approach to deal with enormous software complexity in automotive systems. This approach supports the development of software architectures by interconnecting (and reusing) software components (SWCs) at various abstraction levels. Automotive software architectures are often modeled with chains of SWCs, also called cause-effect chains that are constrained by timing requirements. Based on the variations in activation patterns of SWCs, a single model of a cause-effect chain at a higher abstraction level can conform to several valid refined models of the chain at a lower abstraction level, which is closer to the system implementation. As a consequence, the total number of valid implementation-level models generated by the existing techniques increases exponentially, thereby significantly increasing the runtime of the timing analysis engines and liming the scalability of the existing techniques. This paper computes an upper bound on the activation pattern combinations that may result from a system of cause-effect chains in a given high-level model of the software architecture. An efficient algorithm is presented that traverses only a reduced number of possible combinations of the cause-effect chains, resulting in the timing analysis of a significantly lower number of implementation-level models of the software architecture. A proof of concept is provided by conducting a case study that shows significant reduction in the runtime of timing analysis engines, i.e., the timing behavior of the considered system is verified by performing the timing analysis of only 27% of all possible combinations of the cause-effect chains.

  • 11. Ben Dhaou, I.
    et al.
    Kondoro, Aron
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. University of Dar es Salaam, Tanzania.
    Kelati, Amleset
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems. University of Turku, Finland.
    Rwegasira, Diana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics. University of Turku, Finland.
    Naiman, S.
    Mvungi, N. H.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Communication and security technologies for smart grid2018In: Fog Computing: Breakthroughs in Research and Practice, IGI Global , 2018, p. 305-331Chapter in book (Other academic)
    Abstract [en]

    The smart grid is a new paradigm that aims to modernize the legacy power grid. It is based on the integration of ICT technologies, embedded system, sensors, renewable energy and advanced algorithms for management and optimization. The smart grid is a system of systems in which communication technology plays a vital role. Safe operations of the smart grid need a careful design of the communication protocols, cryptographic schemes, and computing technology. In this article, the authors describe current communication technologies, recently proposed algorithms, protocols, and architectures for securing smart grid communication network. They analyzed in a unifying approach the three principles pillars of smart-gird: Sensors, communication technologies, and security. Finally, the authors elaborate open issues in the smart-grid communication network.

  • 12.
    Chaourani, Panagiotis
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH Royal Institute of Technology.
    A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors2018Conference paper (Refereed)
    Abstract [en]

    The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance.

  • 13.
    Chaourani, Panagiotis
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Rusu, Ana
    KTH, Superseded Departments (pre-2005), Electronic Systems Design.
    Inductors in a Monolithic 3-D Process: Performance Analysis and Design Guidelines2019In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 27, no 2, p. 468-480Article in journal (Refereed)
    Abstract [en]

    Monolithic 3-D (M3D) integration technology has demonstrated significant area reduction in digital systems. Recently, its applications to other fields have been considered as well. To fully investigate the potential of M3D for radio-frequency/analog-mixed signal (RF/AMS) circuits and systems, the behavior of inductors in this technology needs to be evaluated. Toward this, in this paper, the effect of M3D integration on their inductance densities and quality factors has been analyzed. The impact of shields on M3D inductors has been investigated, as well as the shunting of multiple metal layers to form multimetal inductors. In an attempt to improve the area efficiency of M3D RF/AMS circuits, the potential of placing bottom-tier blocks underneath top-tier inductors has been identified, and a set of guidelines has been proposed to maximize the inter-tier electromagnetic isolation. These guidelines deal with the suitable position of both low- and high-frequency blocks, their wiring, as well as the type of shield that is needed between them and the inductors. To prove the efficiency of these guidelines, an array of bottom-tier resistors has been placed underneath a top-tier inductor, resulting in more than 50 dB of inter-tier isolation for frequencies up to 20 GHz.

  • 14.
    Chen, DeJiu
    et al.
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Embedded Control Systems. KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Machine Design (Div.). KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Mechatronics.
    Östberg, Kenneth
    RISE - Research Institutes of Sweden.
    Becker, Matthias
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Sivencrona, Håkan
    Zenuity AB.
    Warg, Fredrik
    RISE - Research Institutes of Sweden.
    Design of a Knowledge-Base Strategy for Capability-Aware Treatment of Uncertainties of Automated Driving Systems2018In: Computer Safety, Reliability, and Security. / [ed] Gallina B., Skavhaug A., Schoitsch E., Bitsch F., Cham, 2018, Vol. 11094Conference paper (Refereed)
    Abstract [en]

    Automated Driving Systems (ADS) represent a key technological advancement in the area of Cyber-physical systems (CPS) and Embedded Control Systems (ECS) with the aim of promoting traffic safety and environmental sustainability. The operation of ADS however exhibits several uncertainties that if improperly treated in development and operation would lead to safety and performance related problems. This paper presents the design of a knowledge-base (KB) strategy for a systematic treatment of such uncertainties and their system-wide implications on design-space and state-space. In the context of this approach, we use the term Knowledge-Base (KB) to refer to the model that stipulates the fundamental facts of a CPS in regard to the overall system operational states, action sequences, as well as the related costs or constraint factors. The model constitutes a formal basis for describing, communicating and inferring particular operational truths as well as the belief and knowledge representing the awareness or comprehension of such truths. For the reasoning of ADS behaviors and safety risks, each system operational state is explicitly formulated as a conjunction of environmental state and some collective states showing the ADS capabilities for perception, control and actuations. Uncertainty Models (UM) are associated as attributes to such state definitions for describing and quantifying the corresponding belief or knowledge status due to the presences of evidences about system performance and deficiencies, etc. On a broader perspective, the approach is part of our research on bridging the gaps among intelligent functions, system capability and dependability for mission-&safety-critical CPS, through a combination of development- and run-time measures.

  • 15.
    Chen, Xiaowen
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Efficient Memory Access and Synchronization in NoC-based Many-core Processors2019Doctoral thesis, monograph (Other academic)
    Abstract [en]

    In NoC-based many-core processors, memory subsystem and synchronization mechanism are always the two important design aspects, since mining parallelism and pursuing higher performance require not only optimized memory management but also efficient synchronization mechanism. Therefore, we are motivated to research on efficient memory access and synchronization in three topics, namely, efficient on-chip memory organization, fair shared memory access, and efficient many-core synchronization.

    One major way of optimizing the memory performance is constructing a suitable and efficient memory organization. A distributed memory organization is more suitable to NoC-based many-core processors, since it features good scalability. We envision that it is essential to support Distributed Shared Memory (DSM) because of the huge amount of legacy code and easy programming. Therefore, we first adopt the microcoded approach to address DSM issues, aiming for hardware performance but maintaining the flexibility of programs. Second, we further optimize the DSM performance by reducing the virtual-to-physical address translation overhead. In addition to the general-purpose memory organization such as DSM, there exists special-purpose memory organization to optimize the performance of application-specific memory access. We choose Fast Fourier Transform (FFT) as the target application, and propose a multi-bank data memory specialized for FFT computation.

    In 3D NoC-based many-core processors, because processor cores and memories reside in different locations (center, corner, edge, etc.) of different layers, memory accesses behave differently due to their different communication distances. As the network size increases, the communication distance difference of memory accesses becomes larger, resulting in unfair memory access performance among different processor cores. This unfair memory access phenomenon may lead to high latencies of some memory accesses, thus negatively affecting the overall system performance. Therefore, we are motivated to study on-chip memory and DRAM access fairness in 3D NoC-based many-core processors through narrowing the round-trip latency difference of memory accesses as well as reducing the maximum memory access latency.

    Barrier synchronization is used to synchronize the execution of parallel processor cores. Conventional barrier synchronization approaches such as master-slave, all-to-all, tree-based, and butterfly are algorithm oriented. As many processor cores are networked on a single chip, contended synchronization requests may cause large performance penalty. Motivated by this, different from the algorithm-based approaches, we choose another direction (i.e., exploiting efficient communication) to address the barrier synchronization problem. We propose cooperative communication as a means and combine it with the master-slave algorithm and the all-to-all algorithm to achieve efficient many-core barrier synchronization. Besides, a multi-FPGA implementation case study of fast many-core barrier synchronization is conducted.

  • 16.
    Chen, Xiaowen
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS). Natl Univ Def Technol, Coll Comp, Changsha 410073, Hunan, Peoples R China.
    Lei, Yuanwu
    Natl Univ Def Technol, Coll Comp, Changsha 410073, Hunan, Peoples R China..
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Chen, Shuming
    Natl Univ Def Technol, Coll Comp, Changsha 410073, Hunan, Peoples R China..
    A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition2018In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 26, no 10, p. 1953-1966Article in journal (Refereed)
    Abstract [en]

    Fast Fourier transform (FFT) is the kernel and the most time-consuming algorithm in the domain of digital signal processing, and the FFT sizes of different applications are very different. Therefore, this paper proposes a variable-size FFT hardware accelerator, which fully supports the IEEE-754 single-precision floating-point standard and the FFT calculation with a wide size range from 2 to 220 points. First, a parallel Cooley-Tukey FFT algorithm based on matrix transposition (MT) is proposed, which can efficiently divide a large size FFT into several small size FFTs that can be executed in parallel. Second, guided by this algorithm, the FFT hardware accelerator is designed, and several FFT performance optimization techniques such as hybrid twiddle factor generation, multibank data memory, block MT, and token-based task scheduling are proposed. Third, its VLSI implementation is detailed, showing that it can work at 1 GHz with the area of 2.4 mm(2) and the power consumption of 91.3 mW at 25 degrees C, 0.9 V. Finally, several experiments are carried out to evaluate the proposal's performance in terms of FFT execution time, resource utilization, and power consumption. Comparative experiments show that our FFT hardware accelerator achieves at most 18.89x speedups in comparison to two software-only solutions and two hardware-dedicated solutions.

  • 17.
    Chen, Yancang
    et al.
    Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China..
    Xie, Lunguo
    Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China..
    Li, Jinwen
    Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China..
    Shi, Zhu
    Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China..
    Zhang, Minxuan
    Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China..
    Chen, Xiaowen
    Natl Univ Def Technol, Dept Comp, Changsha, Hunan, Peoples R China..
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    A Trace-driven Hardware-level Simulator for Design and Verification of Network-on-Chips2010In: 2011 INTERNATIONAL CONFERENCE ON COMPUTERS, COMMUNICATIONS, CONTROL AND AUTOMATION (CCCA 2011), VOL II / [ed] Thaung, K S, IEEE , 2010, p. 32-35Conference paper (Refereed)
    Abstract [en]

    Traditional communications of general-purpose multi-core processor and application-specific System-on-Chip face challenges in terms of scalability and complexity. Network-on-Chip (NoC) has been the most promising solution for the communications of multi-core and many-core chips. In this paper, we present a trace-driven hardware-level simulator (noted HS) based on SystemVerilog for the design and verification of NoCs. Different from the state-of-the-art NoC simulators, the HS owns three important characteristics in addition to the capability of creating simulation and synthesizable NoC descriptions: 1) hardware-level simulation can be done, which means more implementation details of hardware than flit-level simulation; 2) router debugging and verification can be done at RTL by inserting assertions and coverage; 3) trace-based application simulations can be done besides synthetic workloads. A 4 X 4 2D mesh NoC with output virtual-channel routers verifies the capability of our HS.

  • 18.
    Chung, Sunjae
    et al.
    KTH, School of Engineering Sciences (SCI), Applied Physics. Department of Physics, University of Gothenburg.
    Jiang, Sheng
    KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics.
    Eklund, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Iacocca, Ezio
    Department of Applied Mathematics, University of Colorado.
    Le, Quang Tuan
    KTH, School of Engineering Sciences (SCI), Applied Physics.
    Mazraati, Hamid
    KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics.
    Mohseni, Seyed Majid
    Department of Physics, Shahid Beheshti University, Tehran 19839, Iran.
    Sani, Sohrab Redjai
    Department of Physics and Astronomy, Uppsala University,.
    Åkerman, Johan
    KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics.
    Effect of canted magnetic field on magnetic droplet nucleation boundariesManuscript (preprint) (Other academic)
    Abstract [en]

    The influence on magnetic droplet nucleation boundaries by canted magnetic elds are investigated and reported. The nucleation boundary condition, In = αAH + BH + C, is determined at different canted angles (0°< θH<20°) using magnetoresistance (MR) and microwave measurements in nanocontact spintorque oscillators (NC-STOs). As θH increased, the nucleation boundary shifts gradually towards higher In and H. The coefficient B of the nucleation boundary equation also nearly doubled as θH increases. On theother hand, the coefficient αA remained constant for all values of θH. These observations can be explained by considering the drift instability of magnetic droplets and the different tilt behaviour of the Co fixed layer induced by different θH.

  • 19.
    de Medeiros, Jose. E. G.
    et al.
    Univ Brasilia, Dept Elect Engn, Brasilia, DF, Brazil..
    Ungureanu, George
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Sander, Ingo
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    An Algebra for Modeling Continuous Time Systems2018In: PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), IEEE, 2018, p. 861-864Conference paper (Refereed)
    Abstract [en]

    Advancements on analog integrated design have led to new possibilities for complex systems combining both continuous and discrete time modules on a signal processing chain. However, this also increases the complexity any design flow needs to address in order to describe a synergy between the two domains, as the interactions between them should be better understood. We believe that a common language for describing continuous and discrete time computations is beneficial for such a goal and a step towards it is to gain insight and describe more fundamental building blocks. In this work we present an algebra based on the General Purpose Analog Computer, a theoretical model of computation recently updated as a continuous time equivalent of the Turing Machine.

  • 20.
    Delekta, Szymon Sollami
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Li, Jiantong
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Wet Transfer of Inkjet Printed Graphene for Microsupercapacitors on Arbitrary Substrates2019In: ACS Applied Energy Materials, ISSN 2574-0962, Vol. 2, no 1, p. 158-163Article in journal (Refereed)
    Abstract [en]

    Significant research interest is being devoted to exploiting the properties of graphene but the difficult integration on various substrates limits its use. In this regard, we developed a transfer technique that allows the direct deposition of inkjet printed graphene devices on arbitrary substrates, even 3D objects and living plants. With this technique, we fabricated micro-supercapacitors, which exhibited good adhesion on almost all substrates and no performance degradation induced by the process. Specifically, the microsupercapacitor on an orchid leaf showed an areal capacitance as high as 441 mu F cm(-2) and a volumetric capacitance of 1.16 F cm(-3). This technique can boost the use of graphene in key technological applications, such as self powered epidermal electronics and environmental monitoring systems.

  • 21. Dhaou, I. B.
    et al.
    Skhiri, H.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Study and implementation of a secure random number generator for DSRC devices2018In: 2017 9th IEEE-GCC Conference and Exhibition, GCCCE 2017, Institute of Electrical and Electronics Engineers Inc. , 2018Conference paper (Refereed)
    Abstract [en]

    This work presents an algorithm to select a low-cost modulus for the implementation of Blum Blum Shub pseudorandom number generator in an FPGA device. Additionally, it elaborates a low-latency architecture for the BBS algorithm suitable for the security service of the IEEE 1609.2 standard. The architecture uses diminished-1 arithmetic and is log2($N$) faster than previously reported implementation using Montgomery multiplier. The architecture is able to implement 224-bit and 256-bit BBS sequences. Synthesis results show that the latencies for the 224-bit and 256-bit BBS are, respectively, 1.12μs and 1.28μs.

  • 22.
    Dubrova, Elena
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    A reconfigurable arbiter PUF with 4 x 4 switch blocks2018In: Proceedings of The International Symposium on Multiple-Valued Logic, IEEE Computer Society , 2018, p. 31-37Conference paper (Refereed)
    Abstract [en]

    Physical Unclonable Functions (PUFs) exploit manufacturing process variation to create responses that are unique to individual integrated circuits (ICs). Typically responses of a PUF cannot be modified once the PUF is fabricated. In applications which use PUFs as a long-Term secret key, it would be useful to have a simple mechanism for reconfiguring the PUF in order to update the key periodically. In this paper, we present a new type of arbiter PUFs which use 4 x 4 switch blocks instead of the conventional 2 x 2 ones. Each 4 x 4 switch block can be reconfigured in many different ways during the PUF's lifetime, making possible regular key updates. © 2018 IEEE.

  • 23.
    Dubrova, Elena
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Naslund, Mats
    Ericsson AB, Ericsson Res, Stockholm, Sweden..
    Selander, Göran
    Ericsson AB, Ericsson Res, Stockholm, Sweden..
    Lindqvist, Fredrik
    Ericsson AB, Ericsson Res, Stockholm, Sweden..
    Message authentication based on cryptographically secure CRC without polynomial irreducibility test2018In: Cryptography and Communications, ISSN 1936-2447, E-ISSN 1936-2455, Vol. 10, no 2, p. 383-399Article in journal (Refereed)
    Abstract [en]

    In this paper, we present a message authentication scheme based on cryptographically secure cyclic redundancy check (CRC). Similarly to previously proposed cryptographically secure CRCs, the presented one detects both random and malicious errors without increasing bandwidth. The main difference from previous approaches is that we use random instead of irreducible generator polynomials. This eliminates the need for irreducibility tests. We provide a detailed quantitative analysis of the achieved security as a function of message and CRC sizes. The results show that the presented scheme is particularly suitable for the authentication of short messages.

  • 24.
    Dubrova, Elena
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Selander, G.
    Näslund, Mats
    KTH.
    Lindqvist, Fredrik
    KTH.
    Lightweight message authentication for constrained devices2018In: WiSec 2018 - Proceedings of the 11th ACM Conference on Security and Privacy in Wireless and Mobile Networks, Association for Computing Machinery (ACM), 2018, p. 196-201Conference paper (Refereed)
    Abstract [en]

    Message Authentication Codes (MACs) used in today's wireless communication standards may not be able to satisfy resource limitations of simpler 5G radio types and use cases such as machine type communications. As a possible solution, we present a lightweight message authentication scheme based on the cyclic redundancy check (CRC). It has been previously shown that a CRC with an irreducible generator polynomial as the key is an -almost XOR-universal (AXU) hash function with = (m + n)/2n-1, where m is the message size and n is the CRC size. While the computation of n-bit CRCs can be efficiently implemented in hardware using linear feedback shift registers, generating random degree-n irreducible polynomials is computationally expensive for large n. We propose using a product of k irreducible polynomials whose degrees sum up to n as a generator polynomial for an n-bit CRC and show that the resulting hash functions are -AXU with = (m + n)k/2n -k. The presented message authentication scheme can be seen as providing a trade-off between security and implementation efficiency.

  • 25.
    Dubrova, Elena
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Teslenko, Maxim
    An efficient SAT-based algorithm for finding short cycles in cryptographic algorithms2018In: Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018, Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 65-72Conference paper (Refereed)
    Abstract [en]

    The absence of short cycles is a desirable property for cryptographic algorithms that are iterated. Furthermore, as demonstrated by the cryptanalysis of A5, short cycles can be exploited to reduce the complexity of an attack. We present an algorithm which uses a SAT-based bounded model checking for finding all short cycles of a given length. The existing Boolean Decision Diagram (BDD) based algorithms for finding cycles have limited capacity due to the excessive memory requirements of BDDs. The simulation-based algorithms can be applied to larger problem instances, however, they cannot guarantee the detection of all cycles of a given length. The same holds for general-purpose SAT-based model checkers. The presented algorithm can handle cryptographic algorithms with very large state spaces, including important ciphers such as Trivium and Grain-128. We found that these ciphers contain short cycles whose existence, to our best knowledge, was previously unknown. This potentially opens new possibilities for cryptanalysis.

  • 26.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Forsberg, Fredrik
    Scania Technical Centre.
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Wagner, Stefan
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Lemme, Max
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Suspended graphenemembranes with attached proof masses as piezoresistive NEMS accelerometersIn: Article in journal (Refereed)
  • 27.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Forsberg, Fredrik
    Wagner, Stefan
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Fisher, Andreas
    Silex Microsystems AB.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Lemme, Max
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Manufacturing of Graphene Membranes with Suspended Silicon Proof Masses forMEMS and NEMSIn: Article in journal (Refereed)
  • 28.
    Fuglesang, Christer
    et al.
    KTH, School of Engineering Sciences (SCI), Physics, Particle and Astroparticle Physics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Wilson, C. F.
    Venus long-life surface package (VL2SP)2017In: Proceedings of the International Astronautical Congress, IAC, International Astronautical Federation, IAF , 2017, p. 3035-3043Conference paper (Refereed)
    Abstract [en]

    Measurements in the atmosphere and at the surface of Venus are required to understand fundamental processes of how terrestrial planets evolve and how they work today. While the European Venus community is unified in its support of the EnVision orbiter proposal as the next step in European Venus exploration, many scientific questions also require in situ Venus exploration. We suggest a long-duration lander at Venus, which would be capable of undertaking a seismometry mission, operating in the 460°C surface conditions of Venus. Radar maps have shown Venus to be covered with volcanic and tectonic features, and mounting evidence, including observations from Venus Express, suggests that some of these volcanoes are active today. Assessing Venus' current seismicity, and measuring its interior structure, is essential if we are to establish the geological history of our twin planet, for example to establish whether it ever had a habitable phase with liquid water oceans. Although some constraints on seismic activity can be obtained from orbit, using radar or ionospheric observation, the most productive way to study planetary interiors is through seismometry. Seismometry requires a mission duration of months or (preferably) years. Previous landers have used passive cooling, relying on thermal insulation and the lander's thermal inertia to provide a brief window of time in which to conduct science operations - but this allows mission durations of hours, not months. Proposals relying on silicon electronics require an electronics enclosure cooled to < 200 °C; the insulation, cooling and power system requirements escalate rapidly to require a > 1 ton, > €1bn class mission, such as those studied in the context of NASA flagship missions. However, there are alternatives to silicon electronics: in particular, there have been promising advances in silicon carbide (SiC) electronics capable of operating at temperatures of 500°C. Within the coming decade it will be possible to assemble at least simple circuits using SiC components, sufficient to run a seismometry lander. We are proposing a Venus Long-Lived Surface Package (VL2SP) consisting of power source (RTG), science payload (seismometer and meteorology sensors), and ambient temperature electronics including a telecommunications system weighing < 100 kg. We do not specify how this VL2SP gets to the surface of Venus, but we estimate that an orbiter providing data relay would be essential. This presentation is based on a response sumitted to ESA's Call for New Scientific Ideas in September 2016. 

  • 29.
    Fuglesang, Christer
    et al.
    KTH, School of Engineering Sciences (SCI), Physics, Particle and Astroparticle Physics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Working on venus and beyond - SiC electronics for extreme environments2017In: Proceedings of the International Astronautical Congress, IAC, International Astronautical Federation, IAF , 2017, p. 10393-10398Conference paper (Refereed)
    Abstract [en]

    Venus is our closest planet, but we know much less about it than about Mars. The main reason for this is the extreme conditions, with a dense atmosphere of mainly CO2 at 92 bar atmosphere and 460 °C temperature at the surface. Only six spacecraft have succeeded to land on Venus and transmit data back to Earth; however none survived for long due to the high temperature. Venera-13 has the record, with 127 minutes at the surface of Venus in 1982. There are many compelling reasons to learn more about the sister planet of Earth, which requires measurements over months rather than minutes on the surface of Venus. Perhaps the single-most challenging task for long-term data taking on the surface of Venus is to build electronics that can operate at temperatures up to 500 °C without cooling. It seems that such technology must be based on wide bandgap semiconductors, such as GaN, SiC or diamond. At KTH, research with SiC devices and integrated circuits has been done for more than 20 years, demonstrating high voltage devices and digital integrated circuit operation at 600 °C. In 2014 the project Working On Venus launched, with funding from Knut and Alice Wallenberg Foundation. The goal is to demonstrate all the electronics for a complete working lander, with all electronics from sensors through amplifiers and analog-to-digital converters to microcontroller with memory and radio, including power supply. The particular sensors the project has in mind are seismic, gas and image sensors. So far, a 200 device level integration has been demonstrated at 500 °C and a 5000+ device level 4 bit microcontroller is being fabricated in an in-house bipolar technology. As for all devices for space, radiation is another concern. SiC integrated circuits have survived exposure to 3 MeV protons with fluences of 1013 cm-2 and gamma rays with doses of 332 Mrad. The dedicated project SUPERHARD IC will study manufacture methods for radiation hardened instrument components that could go beyond Venus, for example for Jovian system exploration. Members of Working on Venus are discussing with scientists seeking opportunities for a Venus Long-Life Surface Package (lander). In 2016 a response was submitted to ESA's Call for New Scientific Ideas. 

  • 30.
    Hallén, Anders
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Suvanam, S. S.
    Radiation hardness for silicon oxide and aluminum oxide on 4H-SiC2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications Inc., 2018, Vol. 924, p. 229-232Conference paper (Refereed)
    Abstract [en]

    The radiation hardness of two dielectrics, SiO2 and Al2O3, deposited on low doped, ntype 4H-SiC epitaxial layers has been investigated by exposing MOS structures involving these materials to MeV proton irradiation. The samples are examined by capacitance voltage (CV) measurements and, from the flat band voltage shift, it is concluded that positive charge is induced in the exposed structures detectable for fluence above 1×1011 cm-2. The positive charge increases with proton fluence, but the SiO2/4H-SiC structures are slightly more sensitive, showing that Al2O3 can provide a more radiation hard passivation, or gate dielectric for 4H-SiC devices.

  • 31.
    Hou, Shuoben
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Silicon Carbide High Temperature Photodetectors and Image Sensor2019Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Silicon Carbide (SiC) has the advantages of ultraviolet (UV) sensing and high temperature characteristics because of its wide band gap. Both merits make SiC photodetectors very attractive in astronomy, oil drilling, combustion detection, biology and medical applications. Driven by the objective of probing the high temperature surface of Venus (460 °C), this thesis develops SiC photodetectors and an image sensor for extremely high temperature functions. The devices and circuits are demonstrated through the procedure of layout design, in-house processing and characterizations on two batches.

    The process flow has been optimized to be suitable for large scale integration (LSI) of SiC bipolar integrated circuits (IC). The improved processing steps are SiC dry etching, ohmic contacts and two-level metal interconnect with chemical-mechanical polishing (CMP). The optimized process flow is applied in the fabrication of discrete devices, a transistor-transistor logic (TTL) process design kit (PDK) and LSI circuits.

    The photodetectors developed in this thesis, including photodiodes with various mesa areas, a phototransistor and a phototransistor Darlington pair have stable characteristics in a wide temperature range (25 °C ~ 500 °C). The maximum operational temperature of the p-i-n photodiode (550 °C) is the highest recorded temperature accomplished ever by a photodiode. The optical responsivity of the photodetectors covers the spectrum from 220 nm to 380 nm, which is UV-only.

    The SiC pixel sensor and image sensor developed in this thesis are pioneer works. The pixel sensor overcomes the challenge of monolithic integration of SiC photodiode and transistors by sharing the same epitaxial layers and topside contacts. The pixel sensor is characterized from 25 °C to 500 °C. The whole image sensor circuit has 256 (16 ×16) pixel sensors and one 8-bit counter together with two 4-to-16 decoders for row/column selection. The digital circuits are built by the standard logic gates selected from the TTL PDK. The image sensor has 1959 transistors in total. The function of the image sensor up to 400 °C is verified by taking basic photos of nonuniform UV illumination on the pixel sensor array.

    This thesis makes an important attempt on the demonstration of SiC opto-electronic on-chip integration. The results lay a foundation on the development of future high temperature high resolution UV image sensors.

  • 32.
    Hou, Shuoben
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    High Temperature High Current Gain IC Compatible 4H-SiC Phototransistor2019Conference paper (Refereed)
    Abstract [en]

    This paper presents our in-house fabricated 4H-SiC n-p-n phototransistors. The wafer mapping of the phototransistor on two wafers shows a mean maximum forward current gain (βFmax) of 100 at 25 ºC. The phototransistor with the highest βFmax of 113 has been characterized from room temperature to 500 ºC. The βFmax drops to 51 at 400 ºC and remains the same at 500 ºC. The photo current gain of the phototransistor is 3.9 at 25 ºC and increases to 14 at 500 ºC under the 365 nm UV light with the optical power of 0.31 mW. The processing of the phototransistor is same to our 4HSiC-based bipolar integrated circuits, so it is a promising candidate for 4H-SiC opto-electronics onchip integration.

  • 33.
    Hou, Shuoben
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Shakir, Muhammad
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Process Control and Optimization of 4H-SiC Semiconductor Devices and Circuits2019In: Proceedings of the 3rd Electron Devices Technology and Manufacturing, (EDTM) Conference 2019, IEEE, 2019Conference paper (Refereed)
  • 34. Huang, Letian
    et al.
    Chen, Shuyu
    Wu, Qiong
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Wang, Junshi
    Jiang, Shuyan
    Li, Qiang
    A Lifetime-aware Mapping Algorithm to Extend MTTF of Networks-on-Chip2018In: 2018 23rd Asia and South Pacific Design Automation Conference Proceedings (ASP-DAC), Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 147-152Conference paper (Refereed)
    Abstract [en]

    Fast aging of components has become one of the major concerns in Systems-on-Chip with further scaling of the submicron technology. This problem accelerates when combined with improper working conditions such as unbalanced components' utilization. Considering the mapping algorithms in the Networks-on-Chip domain, some routers/links might be frequently selected for mapping while others are underutilized. Consequently, the highly utilized components may age faster than others which results in disconnecting the related cores from the network. To address this issue, we propose a mapping algorithm, called lifetime-aware neighborhood allocation (LaNA), that takes the aging of components into account when mapping applications. The proposed method is able to balance the wear-out of NoC components, and thus extending the service time of NoC. We model the lifetime as a resource consumed over time and accordingly define the lifetime budget metric. LaNA selects a suitable node for mapping which has the maximum lifetime budget. Experimental results show that the lifetime-aware mapping algorithm could improve the minimal MTTF of NoC around 72.2%, 58.3%, 46.6% and 48.2% as compared to NN, CoNA, WeNA and CASqA, respectively.

  • 35.
    Huan, Yuxiang
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS). Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
    Xu, Jiawei
    Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
    Zheng, Li-rong
    KTH. Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH Royal Inst Technol, Stockholm, Sweden..
    Zou, Zhuo
    Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
    A 3D Tiled Low Power Accelerator for Convolutional Neural Network2018In: 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2018Conference paper (Refereed)
    Abstract [en]

    It remains a challenge to run Deep Learning in devices with stringent power budget in the Internet-of-Things. This paper presents a low-power accelerator for processing Convolutional Neural Networks on the embedded devices. The power reduction is realized by exploring data reuse in three different aspects, with regards to convolution, filter and input features. A systolic-like data flow is proposed and applied to rows of Processing Elements (PEs), which facilitate reusing the data during convolution. Reuse of input features and filters is achieved by arranging the PE array in a 3D tiled architecture, whose dimension is 3 x 14 x 4. Local storage within PEs is therefore reduced and only cost 17.75 kB, which is 20% of the state-of-the-art. With dedicated delay chains in each PE, this accelerator is reconfigurable to suit various parameter settings of convolutional layers. Evaluated in UMC 65 nm low leakage process, the accelerator can reach a peak performance of 84 GOPS and consume only 136 mW at 250 Mhz.

  • 36.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Zumbro, John E.
    University of Arkansas.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Mantooth, H. Alan
    University of Arkansas.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A 500 °C Active Down-Conversion Mixer in Silicon Carbide Bipolar Technology2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 6, p. 855-858Article in journal (Refereed)
    Abstract [en]

    This letter presents an active down-conversion mixer for high-temperature communication receivers. The mixer is based on an in-house developed 4H-SiC BJT and down-converts a narrow-band RF input signal centered around 59 MHz to an intermediate frequency of 500 kHz. Measurements show that the mixer operates from room temperature up to 500 °C. The conversion gain is 15 dB at 25 °C, which decreases to 4.7 dB at 500 °C. The input 1-dB compression point is 1 dBm at 25 °C and −2.5 dBm at 500 °C. The mixer is biased with a collector current of 10 mA from a 20 V supply and has a maximum DC power consumption of 204 mW. High-temperature reliability evaluation of the mixer shows a conversion gain degradation of 1.4 dB after 3-hours of continuous operation at 500 °C.

  • 37.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Ascatron AB.
    Zumbro, John E.
    University of Arkansas.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Mantooth, H. Alan
    University of Arkansas.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A SiC BJT-Based Negative Resistance Oscillator for High-Temperature Applications2019In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 7, no 1, p. 191-195Article in journal (Refereed)
    Abstract [en]

    This brief presents a 59.5 MHz negative resistanceoscillator for high-temperature operation. The oscillator employs an in-house 4H-SiC BJT, integrated with the requiredcircuit passives on a low-temperature co-fired ceramic substrate. Measurements show that the oscillator operates from room-temperature up to 400 C. The oscillator delivers an output◦power of 11.2 dBm into a 50 Ω load at 25 C, which decreases to 8.4 dBm at 400 C. The oscillation frequency varies by 3.3% in the entire temperature range. The oscillator is biased witha collector current of 35 mA from a 12 V supply and has amaximum DC power consumption of 431 mW.

  • 38.
    Ivanisevic, Nikola
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Circuit Design Techniques for Implantable Closed-Loop Neural Interfaces2019Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    Implantable neural interfaces are microelectronic systems, which have the potential to enable a wide range of applications, such as diagnosis and treatment of neurological disorders. These applications depend on neural interfaces to accurately record electrical activity from the surface of the brain, referred to as electrocorticography (ECoG), and provide controlled electrical stimulation as feedback. Since the electrical activity in the brain is caused by ionic currents in neurons, the bridge between living tissue and inorganic electronics is achieved via microelectrode arrays. The conversion of the ionic charge into freely moving electrons creates a built-in electrode potential that is several orders of magnitude larger than the ECoG signal, which increases the dynamic range, resolution, and power consumption requirements of neural interfaces. Also, the small surface area of microelectrodes implies a high-impedance contact, which can attenuate the ECoG signal. Moreover, the applied electrical stimulation can also interfere with the recording and ultimately cause irreversible damages to the electrodes or change their impedance. This thesis is devoted to resolving the challenges of high-resolution recording and monitoring the electrode impedance in implantable neural interfaces.

    The first part of this thesis investigates the state-of-the-art neural interfaces for ECoG and identifies their limitations. As a result of the investigation, a high-resolution ADC is proposed and implemented based on a ΔΣ modulator. In order to enhance performance, dynamic biasing and area-efficient switched-capacitor circuits were proposed. The ΔΣ modulator is combined with the analog front-end to provide a complete readout solution for high-resolution ECoG recording. The corresponding chip prototype was fabricated in a 180 nm CMOS process, and the measurement results showed a 14-ENOB over a 300-Hz bandwidth while dissipating 54-μW.

    The second part of this thesis expands upon the well-known methods for impedance measurements and proposes an alternative digital method for monitoring the electrode-tissue interface impedance. The proposed method is based on the system identification technique from adaptive digital filtering, and it is compatible with existing circuitry for neural stimulation. The method is simple to implement and performs wide-band measurements. The system identification was first verified through behavioral simulations and then tested with a board-level prototype in order to validate the functionality under real conditions. The measurement results showed successful identification of the electrode-electrolyte and electrode-skin impedance magnitudes.

  • 39.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems2018In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 05Article in journal (Refereed)
    Abstract [en]

    This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 μm CMOS triple-well process and has a total power consumption of 54 μW. Measurement results, across 10 packaged samples, show approximately 14-ENOB over a 300Hz bandwidth with an input referred noise of 5.23 μVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.

  • 40.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation2018Conference paper (Refereed)
    Abstract [en]

    A fully differential switched-capacitor circuit that combines the functionality of a voltage buffer and an integrator is proposed. The employed switching scheme exhibits intrinsic flicker noise canceling properties, whereas conventional techniques require additional circuit components. The circuit has been designed in a 0.18 μm CMOS process for 1.8 V supply. The estimated power consumption is 13.5 μW, while the occupied area is 121×442 μm2. Area-efficient design is achieved by exploiting the correlation between the effective noise bandwidth and noise floor density in the proposed circuit. The sampled input referred noise floor is −133 dBV/√Hz, which is remarkably low when considering that the sampling capacitance is just 1.8 pF.

  • 41.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Impedance Spectroscopy Based on Linear System Identification2019In: IEEE Transactions on Biomedical Circuits and Systems, ISSN 1932-4545, E-ISSN 1940-9990Article in journal (Refereed)
    Abstract [en]

    Impedance spectroscopy is a commonly used mea-surement technique for electrical characterization of a sample-under-test over a wide frequency range. Most measurementmethods employ a sine wave excitation generator, which implies apoint-by-point frequency sweep and a complex readout architec-ture. This paper presents a fast, wide-band, measurement methodfor impedance spectroscopy based on linear system identification.The main advantage of the proposed method is the low hardwarecomplexity, which consists of a 3-level pulse waveform, aninverting voltage amplifier and a general purpose ADC. A proof-of-concept prototype, which is implemented with off-the-shelfcomponents, achieves an estimation fit of approximately 96%.The prototype operation is validated electrically using knownRC component values and tested in real application conditions.

  • 42.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Impedance spectroscopy systems: Review and an all-digital adaptive IIR filtering approach2017In: 2017 IEEE Biomedical Circuits and Systems Conference, Turin, October 19-21, 2017, Turin, Italy: Institute of Electrical and Electronics Engineers (IEEE), 2017Conference paper (Refereed)
    Abstract [en]

    Impedance spectroscopy is a low-cost sensing technique that is generating considerable interest in wearable and implantable biomedical applications since it can be efficiently integrated on a single microchip. In this paper, the fundamental characteristics of the most well-known system architectures are presented, and a more robust and hardware-efficient solution is proposed. An all-digital implementation based on adaptive filtering is used for identifying the impedance parameters of a sample-under-test. The coefficients of an infinite-impulse-response (IIR) filter are tuned by an adaptive algorithm based on pseudo-linear regression and output-error formulation. A three-level pseudorandom noise generator with a concave power spectral density is employed without deteriorating the nominal performance. Proof-of-concept has been verified with behavioral simulations.

  • 43.
    Jayakumar, Ganesh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application2018In: Micromachines, ISSN 2072-666X, E-ISSN 2072-666X, Vol. 9, no 11, article id 544Article in journal (Refereed)
    Abstract [en]

    Silicon ribbons (SiRi) have been well-established as highly sensitive transducers for biosensing applications thanks to their high surface to volume ratio. However, selective and multiplexed detection of biomarkers remains a challenge. Further, very few attempts have been made to integrate SiRi with complementary-metal-oxide-semiconductor (CMOS) circuits to form a complete lab-on-chip (LOC). Integration of SiRi with CMOS will facilitate real time detection of the output signal and provide a compact small sized LOC. Here, we propose a novel pixel based SiRi device monolithically integrated with CMOS field-effect-transistors (FET) for real-time selective multiplexed detection. The SiRi pixels are fabricated on a silicon-on-insulator wafer using a top-down method. Each pixel houses a control FET, fluid-gate (FG) and SiRi sensor. The pixel is controlled by simultaneously applying frontgate (V-G) and backgate voltage (V-BG). The liquid potential can be monitored using the FG. We report the transfer characteristics (I-D-V-G) of N- and P-type SiRi pixels. Further, the I-D-V-G characteristics of the SiRis are studied at different V-BG. The application of V-BG to turn ON the SiRi modulates the subthreshold slope (SS) and threshold voltage (V-TH) of the control FET. Particularly, N-type pixels cannot be turned OFF due to the control NFET operating in the strong inversion regime. This is due to large V-BG (25 V) application to turn ON the SiRi sensor. Conversely, the P-type SiRi sensors do not require large V-BG to switch ON. Thus, P-type pixels exhibit excellent I-ON/I-OFF 10(6), SS of 70-80 mV/dec and V-TH of 0.5 V. These promising results will empower the large-scale cost-efficient production of SiRi based LOC sensors.

  • 44.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Silicon nanowire based devices for More than Moore Applications2018Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Silicon nanowires (SiNW) are in the spotlight for a few years in the research community as a good candidate for biosensing applications. This is attributed to their small dimensions in nanometer scale that offers high sensitivity, label-free detection and at the same time utilizing small amount of sample. While the recent research has concentrated predominantly on utilizing single or multiple SiNW for biosensing applications, very few attempts have been made to integrate SiNW with complementary-metal-oxide- semiconductor (CMOS) integration to arrive at a complete lab-on-chip (LOC) sensor. Further, the manufacturing methods reported thus far in the production of SiNW for biosensing applications have not fully exploited both the front-end-of-line (FEOL) as well as back-end-of-line (BEOL) methods in CMOS integration. Neither does the research community address CMOS integration based methods to realize multi and specific target detection that are important attributes for an ideal LOC biosensor.

    Integration of SiNW with CMOS circuitry will facilitate real time detection of the output signal and in addition provide a compact small sized sensor that is fully portable operating at high speed. In order to avail the benefits of CMOS circuits and develop a large scale production friendly LOC sensor, the scheme of SiNW fabrication has to facilitate either the FEOL or BEOL CMOS integration schemes. This thesis work is focused on revealing a novel FEOL as well as BEOL scheme for integration of SiNW with CMOS circuitry. The major part of the FEOL research work is concentrated on developing a high volume SiNW manufacturing method that is suitable for industrial production. Likewise, in the BEOL scheme, predominant focus was to develop a wafer scale scheme to integrate network of nanowires (nanonets) with CMOS circuitry to manufacture a monolithic 3D above-IC LOC biosensor.

    In the FEOL scheme, the SiNWs are fabricated using a revised pattern transfer technique called sidewall transfer lithography (STL). The STL method is identified as one of the efficient methods of fabricating SiNW as it uses CMOS industry grade materials that is fully compatible with the FEOL fabrication scheme. Thanks to the usage of single lithography and controlled selective etching techniques used in the STL process, the line width and aspect ratio of the SiNW can be tailored to suit the requirements for DNA hybridization detection. A fabrication process flow matching standard CMOS process integration flows has been developed to integrate SiNW with HfO2 and TiN metal gate MOSFETS. An emphasis has been placed in the design of a novel pixel matrix based SiNW LOC sensor. Specific and multi-target detection has been kept as top priority in the design of the SiNW LOC sensor. The possibility to monitor the potential of the electrolyte during the detection process using a fluid gate has been accounted in this design. Furthermore, the SiNW pixel design eliminates the intricate microfluidics and eases access to the SiNW test site using a simple photolithography mask and RIE. The SiNW and MOSFETS demonstrate excellent electrical characteristics. For the very first time, the concept to access single as well as multiple array SiNW pixels using a transistor has been successfully demonstrated.

    In the BEOL scheme, the nanonets are fabricated using the bottom-up method and transferred onto a pre-fabricated CMOS wafer supplied by ams foundry. The connection between the nanonets lying above-IC and the underlying CMOS layer was established by employing a thin metal backgate electrode, backgate dielectric and metal source/drain contact pads. Many challenges in the BEOL scheme have been identified and overcome by incorporating efficient device architecture and careful selection of materials. To the first of its kind, a wafer scale process was developed to integrate nanonets with CMOS to form a monolithic 3D IC. The devices exhibit excellent electrical characteristics and lower leakage currents compared to standalone nanonet sensors fabricated on Si/SiN substrate. Further, the FEOL and BEOL integration schemes are compared and the various pro’s and con’s of both approaches for integration of SiNW with CMOS circuits to build a LOC biosensor are discussed in detail.

    Finally, dry environment DNA hybridization detection is demonstrated on the surface of thin HfO2 encapsulated SiNW sensors. Upon DNA hybridization, SiNW devices exhibit threshold voltage shift larger than the noise introduced by the exposition to saline solutions used for the bio-processes. More specifically, based on a statistical analysis, it is demonstrated that 85% of the tested devices were efficient for DNA hybridization detection. The estimated density of hybridized DNA was in the order of 1010 cm-2. These promising results of realizing a SiNW based lab-on-chip platform through the FEOL and BEOL monolithic integration of SiNW and CMOS circuitry further strengthen the profile of SiNW as a nano biosensor. Indeed, this is expected to pave the way for more than Moore applications of SiNW based devices and integrated circuits.

  • 45.
    Jayakumar, Ganesh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Legallais, Maxime
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Mouis, Mireille
    Pignot-Paintrand, Isabelle
    Stambouli, Valérie
    Ternon, Céline
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Wafer-scale HfO 2 encapsulated silicon nanowire field effect transistor for efficient label-free DNA hybridization detection in dry environment2019In: Nanotechnology, ISSN 0957-4484, E-ISSN 1361-6528, Vol. 30, no 18Article in journal (Refereed)
  • 46.
    Jensen, J.
    et al.
    Linkoping Univ, IFM, Thin Film Phys Div, SE-58183 Linkoping, Sweden..
    Sanz, R.
    CSIC, Inst Ciencia Mat Madrid, Madrid 28043, Spain..
    Jaafar, M.
    CSIC, Inst Ciencia Mat Madrid, Madrid 28043, Spain..
    Hernandez-Velez, M.
    CSIC, Inst Ciencia Mat Madrid, Madrid 28043, Spain.;Univ Autonoma Madrid, Appl Phys Dept, Madrid 28043, Spain..
    Asenjo, A.
    CSIC, Inst Ciencia Mat Madrid, Madrid 28043, Spain..
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Vazquez, M.
    Linkoping Univ, IFM, Thin Film Phys Div, SE-58183 Linkoping, Sweden..
    Localized Fe-56(+) Ion Implantation of TiO2 Using Anodic Porous Alumina2010In: ION BEAMS AND NANO-ENGINEERING / [ed] Ila, D Chu, PK Lindner, JKN Kishimoto, N Baglin, JEE, MATERIALS RESEARCH SOC , 2010, p. 3-+Conference paper (Refereed)
    Abstract [en]

    We present result following localized ion implantation of rutile titanium dioxide (TiO2) using anodic porous alumina as a mask. The implantation were performed with 100 keV Fe-56(+) ions using a fluence of 1.3.10(16) ions/cm(2). The surface modifications where studied by means of SEM, AFM/MFM and XRD. A well-defined hexagonal pattern of modified material in the near surface structure is observed. Local examination of the implanted areas revealed no clear magnetic signal. However, a variation in mechanical and electrostatic behavior between implanted and non-implanted zones is inferred from the variation in AFM signals.

  • 47.
    Jin, Yi
    et al.
    Fudan Univ, Shanghai, Peoples R China..
    Huan, Yuxiang
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Fudan Univ, Shanghai, Peoples R China..
    Chu, Haoming
    Fudan Univ, Shanghai, Peoples R China..
    Zou, Zhuo
    Fudan Univ, Shanghai, Peoples R China..
    Zheng, Li-rong
    KTH. Fudan Univ, Shanghai, Peoples R China..
    TMR Group Coding Method for Optimized SEU and MBU Tolerant Memory Design2018In: 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2018Conference paper (Refereed)
    Abstract [en]

    This work proposes a fault tolerant memory design using the method of Triple Module Redundancy (TMR) group coding to tolerant the Single-Event Upset (SEU) and Multi-Bit Upset (MBU) influence on memory devices in space environment. The group coding method uses different models to partition and code each word line in memory with Hamming code to achieve best performance. TMR group coding method further increases the capability of self-correction for the errors occurred in parity bits. The evaluation results show that the suggested approach can obtain improved correctness for the memory output with optimized tradeoff between reliability and cost. At 5% error rate, the probability of correct output reaches 70.78% with small cost increment. To achieve 90% reliability, the accuracy improvement is 31.9% compared to TMR with 9% increased area. This solution proposed is evaluated on the memory rich micro-coded processor, but can be further extended to other memory-based processors that need high reliability for the SEU and MBU influence in aerospace applications.

  • 48.
    Kajihara, J.
    et al.
    Japan.
    Kuroki, S. -I
    Japan.
    Ishikawa, S.
    Japan.
    Maeda, T.
    Japan.
    Sezaki, H.
    japan.
    Makino, T.
    Japan.
    Ohshima, T.
    japan.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    4H-SiC pMOSFETs with al-doped S/D and NbNi silicide ohmic contacts2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, p. 423-427Conference paper (Refereed)
    Abstract [en]

    4H-SiC pMOSFETs with Al-doped S/D and NbNi silicide ohmic contacts were demonstrated and were characterized at up to a temperature of 200°C. For the pMOSFETs, silicides on p-type 4H-SiC with Nb/Ni stack, Nb-Ni Alloy, Ni and Nb/Ti were investigated, and the Nb/Ni stack silicide with the contact resistance of 5.04×10-3 Ωcm2 were applied for the pMOSFETs.

  • 49. Kalinga, E. A.
    et al.
    Ibwe, K. S.
    Mvungi, N. H.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Active learning through smart grid model site in challenge based learning course2018In: IMSCI 2018 - 12th International Multi-Conference on Society, Cybernetics and Informatics, Proceedings, International Institute of Informatics and Systemics, IIIS , 2018, p. 120-126Conference paper (Refereed)
    Abstract [en]

    Smart Grid is a new and growing technology to developing countries. Its implementation and sustainability rely on well trained experts. Sustainability of the smart grid need local experts, hence a project named iGRID: Smart Grid Capacity Development and Enhancement in Tanzania was started. The project is running at the College of Information and Communication Technologies, University of Dar es Salaam. It intends to generate the necessary technical and scientific skills to ensure sustainable implementation of smart grid. iGRID project introduced taught PhD and Masters programs focusing on society, innovation and entrepreneurship in iGRID aspects, as well as to facilitate implementation of automation of monitoring, evaluation, analysis, control and management of electrical power system (smart grid) in order to improve delivery efficiency and to optimize operational costs in the electrical power system in Tanzania. The project made use of Challenge-Based Learning (CBL) methodology to engage students to work together with stakeholders in identifying challenges facing electrical power system in Tanzania. This paper presents the experience of using CBL methodology to achieve active learning to engineering students. The dynamicity of the teaching model, allowed students to acquire skills necessary to solve medium to high tech complex problems. The results build a continuous learning platform for students researching in electrical field. 

  • 50.
    Kargarrazi, Saleh
    et al.
    Stanford Univ, Dept Aeronaut & Astronaut, Stanford, CA 94305 USA..
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Saggini, Stefano
    DIEGM Univ Udine, I-33100 Udine, Italy..
    Senesky, Debbie
    Stanford Univ, Dept Aeronaut & Astronaut, Stanford, CA 94305 USA..
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    500 degrees C SiC PWM Integrated Circuit2019In: IEEE transactions on power electronics, ISSN 0885-8993, E-ISSN 1941-0107, Vol. 34, no 3, p. 1997-2001Article in journal (Refereed)
    Abstract [en]

    This letter reports on a high-temperature pulsewidth modulation (PWM) integrated circuit microfabricated in 4H-SiC bipolar process technology that features an on-chip integrated ramp generator. The circuit has been characterized and shown to be operational in a wide temperature range from 25 to 500 degrees C. The operating frequency of the PWM varies in the range of 160 to 210 kHz and the duty cycle varies less than 17% over the entire temperature range. The proposed PWM is suggested to efficiently and reliably control power converters in extreme environments.

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