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  • 1.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH.
    GOI fabrication for Monolithic 3D integrationIn: Article in journal (Other academic)
  • 2.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Germanium on Insulator Fabrication for Monolithic 3-D Integration2018In: IEEE Journal of the Electron Devices Society, ISSN 2168-6734, Vol. 6, no 1, p. 588-593Article in journal (Refereed)
    Abstract [en]

    A low temperature (T-max = 350 degrees C) process for Germanium (Ge) on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this paper. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. GOI substrates with surface roughness below 0.5 nm, 0.15% tensile strain, thickness nonuniformity of less than 3 nm and residual p-type doping of less than 1016 cm(-3) were fabricated. Ge pFETs are fabricated (T-max = 600 degrees C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of -0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 3.
    Abedin, Ahmad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Zurauskaite, Laura
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Garidis, Konstantinos
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    GOI fabrication for monolithic 3D integration2018In: 2017 IEEE SOI-3D-Subthreshold Microelectronics Unified Conference, S3S 2017, Institute of Electrical and Electronics Engineers (IEEE), 2018, Vol. 2018, p. 1-3Conference paper (Refereed)
    Abstract [en]

    A low temperature (Tmax=350 °C) process for Ge on insulator (GOI) substrate fabrication with thicknesses of less than 25 nm is reported in this work. The process is based on a single step epitaxial growth of a Ge/SiGe/Ge stack on Si, room temperature wafer bonding, and an etch-back process using Si0.5Ge0.5 as an etch-stop layer. Using this technique, GOI substrates with surface roughness below 0.5 nm, thickness nonuniformity of less than 3 nm, and residual p-type doping of less than 1016 cm-3 are achieved. Ge pFETs are fabricated (Tmax=600 °C) on the GOI wafer with 70% yield. The devices exhibit a negative threshold voltage of-0.18 V and 60% higher mobility than the SOI pFET reference devices.

  • 4.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH.
    Compressive-Strained Ge and Tensile-Strained SiGe on Insulator Fabrication via Wafer Bonding for Monolithic 3D IntegrationManuscript (preprint) (Other academic)
  • 5.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Fabrication of Group IV Semiconductors on Insulator for Monolithic 3D Integration2018Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The conventional 2D geometrical scaling of transistors is now facing many challenges in order to continue the performance enhancement while decreasing power consumption. The decrease in the device power consumption is related to the scaling of the power supply voltage (Vdd) and interconnects wiring length. In addition, monolithic three dimensional (M3D) integration in the form of vertically stacked devices, is a possible solution to increase the device density and reduce interconnect wiring length. Integrating strained germanium on insulator (sGeOI) pMOSFETs monolithically with strained silicon/silicon-germanium on insulator (sSOI/sSiGeOI) nMOSFETs can increase the device performance and packing density. Low temperature processing (<550 ºC) is essential as interconnects and strained layers limit the thermal budget in M3D. This thesis presents an experimental investigation of the low temperature (<450 ºC) fabrication of group IV semiconductor-on-insulator substrates with the focus on sGeOI and sSiGeOI fabrication processes compatible with M3D.

      To this aim, direct bonding was used to transfer the relaxed and strained semiconductor layers. The void formation dependencies of the oxide thickness, the surface treatment of the oxide and the post annealing time were fully examined. Low temperature SiGe epitaxy was investigated with the emphasis on the fabrication of Si0.5Ge0.5 strain-relaxed buffers (SRBs), etch-stop layer, and the device layer in the SiGeOI and GeOI process schemes. Ge epitaxial growth on Si as thick SRBs and thin device layers was investigated. Thick (500 nm-3 µm) and thin (<30 nm) relaxed GeOI substrates were fabricated. The latter was fabricated by continuous epitaxial growth of a 3-µm Ge (SRB)/Si0.5Ge0.5 (etch stop)/Ge (device layer) stack on Si. The fabricated long channel Ge pFETs from these GeOI substrates exhibit well-behaved IV characteristics with an effective mobility of 160 cm2/Vs.

      The planarization of SiO2 and SiGe SRBs for the fabrication of the strained GeOI and SiGeOI were accomplished by chemical mechanical polishing (CMP). Low temperature processes (<450 ºC) were developed for compressively strained GeOI layers (ɛ ~ -1.75 %, < 20 nm), which are used for high mobility and low power devices. For the first time, tensile strained Si0.5Ge0.5 (ɛ ~ 2.5 %, < 20 nm) films were successfully fabricated and transferred onto patterned substrates for 3D integration.

  • 6.
    Asadollahi, Ali
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH.
    Low Temperature SiGe Epitaxy Using SiH4-GeH4and Si2H6-Ge2H6 Gas PrecursorsIn: Journal of Solid State Science and TechnologyArticle in journal (Other academic)
  • 7.
    Ayedh, H. M.
    et al.
    Norway.
    Nipoti, R.
    Italy.
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Svensson, B. G.
    Norway.
    Kinetics modeling of the carbon vacancy thermal equilibration in 4H-SiC2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, p. 233-236Conference paper (Refereed)
    Abstract [en]

    The carbon vacancy (VC) is a major limiting-defect of minority carrier lifetime in n-type 4H-SiC epitaxial layers and it is readily formed during high temperature processing. In this study, a kinetics model is put forward to address the thermodynamic equilibration of VC, elucidating the possible atomistic mechanisms that control the VC equilibration under C-rich conditions. Frenkel pair generation, injection of carbon interstitials (Ci’s) from the C-rich surface, followed by recombination with VC’s, and diffusion of VC’s towards the surface appear to be the major mechanisms involved. The modelling results show a close agreement with experimental deep-level transient spectroscopy (DLTS) depth profiles of VC after annealing at different temperatures.

  • 8.
    Chaourani, Panagiotis
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH Royal Institute of Technology.
    A Study on Monolithic 3-D RF/AMS ICs: Placing Digital Blocks Under Inductors2018Conference paper (Refereed)
    Abstract [en]

    The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance.

  • 9.
    Chen, DeJiu
    et al.
    KTH, School of Industrial Engineering and Management (ITM), Machine Design (Dept.), Embedded Control Systems.
    Östberg, Kenneth
    RISE - Research Institutes of Sweden.
    Becker, Matthias
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Sivencrona, Håkan
    Zenuity AB.
    Warg, Fredrik
    RISE - Research Institutes of Sweden.
    Design of a Knowledge-Base Strategy for Capability-Aware Treatment of Uncertainties of Automated Driving Systems2018In: Computer Safety, Reliability, and Security. / [ed] Gallina B., Skavhaug A., Schoitsch E., Bitsch F., Cham, 2018, Vol. 11094Conference paper (Refereed)
    Abstract [en]

    Automated Driving Systems (ADS) represent a key technological advancement in the area of Cyber-physical systems (CPS) and Embedded Control Systems (ECS) with the aim of promoting traffic safety and environmental sustainability. The operation of ADS however exhibits several uncertainties that if improperly treated in development and operation would lead to safety and performance related problems. This paper presents the design of a knowledge-base (KB) strategy for a systematic treatment of such uncertainties and their system-wide implications on design-space and state-space. In the context of this approach, we use the term Knowledge-Base (KB) to refer to the model that stipulates the fundamental facts of a CPS in regard to the overall system operational states, action sequences, as well as the related costs or constraint factors. The model constitutes a formal basis for describing, communicating and inferring particular operational truths as well as the belief and knowledge representing the awareness or comprehension of such truths. For the reasoning of ADS behaviors and safety risks, each system operational state is explicitly formulated as a conjunction of environmental state and some collective states showing the ADS capabilities for perception, control and actuations. Uncertainty Models (UM) are associated as attributes to such state definitions for describing and quantifying the corresponding belief or knowledge status due to the presences of evidences about system performance and deficiencies, etc. On a broader perspective, the approach is part of our research on bridging the gaps among intelligent functions, system capability and dependability for mission-&safety-critical CPS, through a combination of development- and run-time measures.

  • 10.
    Chen, Xiaowen
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS). Natl Univ Def Technol, Coll Comp, Changsha 410073, Hunan, Peoples R China.
    Lei, Yuanwu
    Natl Univ Def Technol, Coll Comp, Changsha 410073, Hunan, Peoples R China..
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Chen, Shuming
    Natl Univ Def Technol, Coll Comp, Changsha 410073, Hunan, Peoples R China..
    A Variable-Size FFT Hardware Accelerator Based on Matrix Transposition2018In: IEEE Transactions on Very Large Scale Integration (vlsi) Systems, ISSN 1063-8210, E-ISSN 1557-9999, Vol. 26, no 10, p. 1953-1966Article in journal (Refereed)
    Abstract [en]

    Fast Fourier transform (FFT) is the kernel and the most time-consuming algorithm in the domain of digital signal processing, and the FFT sizes of different applications are very different. Therefore, this paper proposes a variable-size FFT hardware accelerator, which fully supports the IEEE-754 single-precision floating-point standard and the FFT calculation with a wide size range from 2 to 220 points. First, a parallel Cooley-Tukey FFT algorithm based on matrix transposition (MT) is proposed, which can efficiently divide a large size FFT into several small size FFTs that can be executed in parallel. Second, guided by this algorithm, the FFT hardware accelerator is designed, and several FFT performance optimization techniques such as hybrid twiddle factor generation, multibank data memory, block MT, and token-based task scheduling are proposed. Third, its VLSI implementation is detailed, showing that it can work at 1 GHz with the area of 2.4 mm(2) and the power consumption of 91.3 mW at 25 degrees C, 0.9 V. Finally, several experiments are carried out to evaluate the proposal's performance in terms of FFT execution time, resource utilization, and power consumption. Comparative experiments show that our FFT hardware accelerator achieves at most 18.89x speedups in comparison to two software-only solutions and two hardware-dedicated solutions.

  • 11.
    Chung, Sunjae
    et al.
    KTH, School of Engineering Sciences (SCI), Applied Physics. Department of Physics, University of Gothenburg.
    Jiang, Sheng
    KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics.
    Eklund, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Iacocca, Ezio
    Department of Applied Mathematics, University of Colorado.
    Le, Quang Tuan
    KTH, School of Engineering Sciences (SCI), Applied Physics.
    Mazraati, Hamid
    KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics.
    Mohseni, Seyed Majid
    Department of Physics, Shahid Beheshti University, Tehran 19839, Iran.
    Sani, Sohrab Redjai
    Department of Physics and Astronomy, Uppsala University,.
    Åkerman, Johan
    KTH, School of Engineering Sciences (SCI), Applied Physics, Materials and Nanophysics.
    Effect of canted magnetic field on magnetic droplet nucleation boundariesManuscript (preprint) (Other academic)
    Abstract [en]

    The influence on magnetic droplet nucleation boundaries by canted magnetic elds are investigated and reported. The nucleation boundary condition, In = αAH + BH + C, is determined at different canted angles (0°< θH<20°) using magnetoresistance (MR) and microwave measurements in nanocontact spintorque oscillators (NC-STOs). As θH increased, the nucleation boundary shifts gradually towards higher In and H. The coefficient B of the nucleation boundary equation also nearly doubled as θH increases. On theother hand, the coefficient αA remained constant for all values of θH. These observations can be explained by considering the drift instability of magnetic droplets and the different tilt behaviour of the Co fixed layer induced by different θH.

  • 12.
    de Medeiros, Jose. E. G.
    et al.
    Univ Brasilia, Dept Elect Engn, Brasilia, DF, Brazil..
    Ungureanu, George
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Sander, Ingo
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    An Algebra for Modeling Continuous Time Systems2018In: PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), IEEE, 2018, p. 861-864Conference paper (Refereed)
    Abstract [en]

    Advancements on analog integrated design have led to new possibilities for complex systems combining both continuous and discrete time modules on a signal processing chain. However, this also increases the complexity any design flow needs to address in order to describe a synergy between the two domains, as the interactions between them should be better understood. We believe that a common language for describing continuous and discrete time computations is beneficial for such a goal and a step towards it is to gain insight and describe more fundamental building blocks. In this work we present an algebra based on the General Purpose Analog Computer, a theoretical model of computation recently updated as a continuous time equivalent of the Turing Machine.

  • 13.
    Dubrova, Elena
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Naslund, Mats
    Ericsson AB, Ericsson Res, Stockholm, Sweden..
    Selander, Göran
    Ericsson AB, Ericsson Res, Stockholm, Sweden..
    Lindqvist, Fredrik
    Ericsson AB, Ericsson Res, Stockholm, Sweden..
    Message authentication based on cryptographically secure CRC without polynomial irreducibility test2018In: Cryptography and Communications, ISSN 1936-2447, E-ISSN 1936-2455, Vol. 10, no 2, p. 383-399Article in journal (Refereed)
    Abstract [en]

    In this paper, we present a message authentication scheme based on cryptographically secure cyclic redundancy check (CRC). Similarly to previously proposed cryptographically secure CRCs, the presented one detects both random and malicious errors without increasing bandwidth. The main difference from previous approaches is that we use random instead of irreducible generator polynomials. This eliminates the need for irreducibility tests. We provide a detailed quantitative analysis of the achieved security as a function of message and CRC sizes. The results show that the presented scheme is particularly suitable for the authentication of short messages.

  • 14.
    Dubrova, Elena
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Selander, G.
    Näslund, Mats
    KTH.
    Lindqvist, Fredrik
    KTH.
    Lightweight message authentication for constrained devices2018In: WiSec 2018 - Proceedings of the 11th ACM Conference on Security and Privacy in Wireless and Mobile Networks, Association for Computing Machinery (ACM), 2018, p. 196-201Conference paper (Refereed)
    Abstract [en]

    Message Authentication Codes (MACs) used in today's wireless communication standards may not be able to satisfy resource limitations of simpler 5G radio types and use cases such as machine type communications. As a possible solution, we present a lightweight message authentication scheme based on the cyclic redundancy check (CRC). It has been previously shown that a CRC with an irreducible generator polynomial as the key is an -almost XOR-universal (AXU) hash function with = (m + n)/2n-1, where m is the message size and n is the CRC size. While the computation of n-bit CRCs can be efficiently implemented in hardware using linear feedback shift registers, generating random degree-n irreducible polynomials is computationally expensive for large n. We propose using a product of k irreducible polynomials whose degrees sum up to n as a generator polynomial for an n-bit CRC and show that the resulting hash functions are -AXU with = (m + n)k/2n -k. The presented message authentication scheme can be seen as providing a trade-off between security and implementation efficiency.

  • 15.
    Dubrova, Elena
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Teslenko, Maxim
    An efficient SAT-based algorithm for finding short cycles in cryptographic algorithms2018In: Proceedings of the 2018 IEEE International Symposium on Hardware Oriented Security and Trust, HOST 2018, Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 65-72Conference paper (Refereed)
    Abstract [en]

    The absence of short cycles is a desirable property for cryptographic algorithms that are iterated. Furthermore, as demonstrated by the cryptanalysis of A5, short cycles can be exploited to reduce the complexity of an attack. We present an algorithm which uses a SAT-based bounded model checking for finding all short cycles of a given length. The existing Boolean Decision Diagram (BDD) based algorithms for finding cycles have limited capacity due to the excessive memory requirements of BDDs. The simulation-based algorithms can be applied to larger problem instances, however, they cannot guarantee the detection of all cycles of a given length. The same holds for general-purpose SAT-based model checkers. The presented algorithm can handle cryptographic algorithms with very large state spaces, including important ciphers such as Trivium and Grain-128. We found that these ciphers contain short cycles whose existence, to our best knowledge, was previously unknown. This potentially opens new possibilities for cryptanalysis.

  • 16.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Forsberg, Fredrik
    Scania Technical Centre.
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Wagner, Stefan
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Lemme, Max
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Suspended graphenemembranes with attached proof masses as piezoresistive NEMS accelerometersIn: Article in journal (Refereed)
  • 17.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Forsberg, Fredrik
    Wagner, Stefan
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Fisher, Andreas
    Silex Microsystems AB.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Lemme, Max
    Faculty of Electrical Engineering and Information Technology, RWTH Aachen University.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Manufacturing of Graphene Membranes with Suspended Silicon Proof Masses forMEMS and NEMSIn: Article in journal (Refereed)
  • 18.
    Fuglesang, Christer
    et al.
    KTH, School of Engineering Sciences (SCI), Physics, Particle and Astroparticle Physics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Wilson, C. F.
    Venus long-life surface package (VL2SP)2017In: Proceedings of the International Astronautical Congress, IAC, International Astronautical Federation, IAF , 2017, p. 3035-3043Conference paper (Refereed)
    Abstract [en]

    Measurements in the atmosphere and at the surface of Venus are required to understand fundamental processes of how terrestrial planets evolve and how they work today. While the European Venus community is unified in its support of the EnVision orbiter proposal as the next step in European Venus exploration, many scientific questions also require in situ Venus exploration. We suggest a long-duration lander at Venus, which would be capable of undertaking a seismometry mission, operating in the 460°C surface conditions of Venus. Radar maps have shown Venus to be covered with volcanic and tectonic features, and mounting evidence, including observations from Venus Express, suggests that some of these volcanoes are active today. Assessing Venus' current seismicity, and measuring its interior structure, is essential if we are to establish the geological history of our twin planet, for example to establish whether it ever had a habitable phase with liquid water oceans. Although some constraints on seismic activity can be obtained from orbit, using radar or ionospheric observation, the most productive way to study planetary interiors is through seismometry. Seismometry requires a mission duration of months or (preferably) years. Previous landers have used passive cooling, relying on thermal insulation and the lander's thermal inertia to provide a brief window of time in which to conduct science operations - but this allows mission durations of hours, not months. Proposals relying on silicon electronics require an electronics enclosure cooled to < 200 °C; the insulation, cooling and power system requirements escalate rapidly to require a > 1 ton, > €1bn class mission, such as those studied in the context of NASA flagship missions. However, there are alternatives to silicon electronics: in particular, there have been promising advances in silicon carbide (SiC) electronics capable of operating at temperatures of 500°C. Within the coming decade it will be possible to assemble at least simple circuits using SiC components, sufficient to run a seismometry lander. We are proposing a Venus Long-Lived Surface Package (VL2SP) consisting of power source (RTG), science payload (seismometer and meteorology sensors), and ambient temperature electronics including a telecommunications system weighing < 100 kg. We do not specify how this VL2SP gets to the surface of Venus, but we estimate that an orbiter providing data relay would be essential. This presentation is based on a response sumitted to ESA's Call for New Scientific Ideas in September 2016. 

  • 19.
    Fuglesang, Christer
    et al.
    KTH, School of Engineering Sciences (SCI), Physics, Particle and Astroparticle Physics.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Working on venus and beyond - SiC electronics for extreme environments2017In: Proceedings of the International Astronautical Congress, IAC, International Astronautical Federation, IAF , 2017, p. 10393-10398Conference paper (Refereed)
    Abstract [en]

    Venus is our closest planet, but we know much less about it than about Mars. The main reason for this is the extreme conditions, with a dense atmosphere of mainly CO2 at 92 bar atmosphere and 460 °C temperature at the surface. Only six spacecraft have succeeded to land on Venus and transmit data back to Earth; however none survived for long due to the high temperature. Venera-13 has the record, with 127 minutes at the surface of Venus in 1982. There are many compelling reasons to learn more about the sister planet of Earth, which requires measurements over months rather than minutes on the surface of Venus. Perhaps the single-most challenging task for long-term data taking on the surface of Venus is to build electronics that can operate at temperatures up to 500 °C without cooling. It seems that such technology must be based on wide bandgap semiconductors, such as GaN, SiC or diamond. At KTH, research with SiC devices and integrated circuits has been done for more than 20 years, demonstrating high voltage devices and digital integrated circuit operation at 600 °C. In 2014 the project Working On Venus launched, with funding from Knut and Alice Wallenberg Foundation. The goal is to demonstrate all the electronics for a complete working lander, with all electronics from sensors through amplifiers and analog-to-digital converters to microcontroller with memory and radio, including power supply. The particular sensors the project has in mind are seismic, gas and image sensors. So far, a 200 device level integration has been demonstrated at 500 °C and a 5000+ device level 4 bit microcontroller is being fabricated in an in-house bipolar technology. As for all devices for space, radiation is another concern. SiC integrated circuits have survived exposure to 3 MeV protons with fluences of 1013 cm-2 and gamma rays with doses of 332 Mrad. The dedicated project SUPERHARD IC will study manufacture methods for radiation hardened instrument components that could go beyond Venus, for example for Jovian system exploration. Members of Working on Venus are discussing with scientists seeking opportunities for a Venus Long-Life Surface Package (lander). In 2016 a response was submitted to ESA's Call for New Scientific Ideas. 

  • 20.
    Hallén, Anders
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Suvanam, S. S.
    Radiation hardness for silicon oxide and aluminum oxide on 4H-SiC2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications Inc., 2018, Vol. 924, p. 229-232Conference paper (Refereed)
    Abstract [en]

    The radiation hardness of two dielectrics, SiO2 and Al2O3, deposited on low doped, ntype 4H-SiC epitaxial layers has been investigated by exposing MOS structures involving these materials to MeV proton irradiation. The samples are examined by capacitance voltage (CV) measurements and, from the flat band voltage shift, it is concluded that positive charge is induced in the exposed structures detectable for fluence above 1×1011 cm-2. The positive charge increases with proton fluence, but the SiO2/4H-SiC structures are slightly more sensitive, showing that Al2O3 can provide a more radiation hard passivation, or gate dielectric for 4H-SiC devices.

  • 21.
    Huan, Yuxiang
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS). Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
    Xu, Jiawei
    Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
    Zheng, Li-rong
    KTH. Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. KTH Royal Inst Technol, Stockholm, Sweden..
    Zou, Zhuo
    Fudan Univ, State Key Lab ASIC & Syst, Shanghai, Peoples R China..
    A 3D Tiled Low Power Accelerator for Convolutional Neural Network2018In: 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2018Conference paper (Refereed)
    Abstract [en]

    It remains a challenge to run Deep Learning in devices with stringent power budget in the Internet-of-Things. This paper presents a low-power accelerator for processing Convolutional Neural Networks on the embedded devices. The power reduction is realized by exploring data reuse in three different aspects, with regards to convolution, filter and input features. A systolic-like data flow is proposed and applied to rows of Processing Elements (PEs), which facilitate reusing the data during convolution. Reuse of input features and filters is achieved by arranging the PE array in a 3D tiled architecture, whose dimension is 3 x 14 x 4. Local storage within PEs is therefore reduced and only cost 17.75 kB, which is 20% of the state-of-the-art. With dedicated delay chains in each PE, this accelerator is reconfigurable to suit various parameter settings of convolutional layers. Evaluated in UMC 65 nm low leakage process, the accelerator can reach a peak performance of 84 GOPS and consume only 136 mW at 250 Mhz.

  • 22. Huang, Letian
    et al.
    Chen, Shuyu
    Wu, Qiong
    Ebrahimi, Masoumeh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Wang, Junshi
    Jiang, Shuyan
    Li, Qiang
    A Lifetime-aware Mapping Algorithm to Extend MTTF of Networks-on-Chip2018In: 2018 23rd Asia and South Pacific Design Automation Conference Proceedings (ASP-DAC), Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 147-152Conference paper (Refereed)
    Abstract [en]

    Fast aging of components has become one of the major concerns in Systems-on-Chip with further scaling of the submicron technology. This problem accelerates when combined with improper working conditions such as unbalanced components' utilization. Considering the mapping algorithms in the Networks-on-Chip domain, some routers/links might be frequently selected for mapping while others are underutilized. Consequently, the highly utilized components may age faster than others which results in disconnecting the related cores from the network. To address this issue, we propose a mapping algorithm, called lifetime-aware neighborhood allocation (LaNA), that takes the aging of components into account when mapping applications. The proposed method is able to balance the wear-out of NoC components, and thus extending the service time of NoC. We model the lifetime as a resource consumed over time and accordingly define the lifetime budget metric. LaNA selects a suitable node for mapping which has the maximum lifetime budget. Experimental results show that the lifetime-aware mapping algorithm could improve the minimal MTTF of NoC around 72.2%, 58.3%, 46.6% and 48.2% as compared to NN, CoNA, WeNA and CASqA, respectively.

  • 23.
    Hussain, Muhammad Waqar
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Elahipanah, Hossein
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Zumbro, John E.
    University of Arkansas.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, B. Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Mantooth, H. Alan
    University of Arkansas.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A 500 °C Active Down-Conversion Mixer in Silicon Carbide Bipolar Technology2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 6, p. 855-858Article in journal (Refereed)
    Abstract [en]

    This letter presents an active down-conversion mixer for high-temperature communication receivers. The mixer is based on an in-house developed 4H-SiC BJT and down-converts a narrow-band RF input signal centered around 59 MHz to an intermediate frequency of 500 kHz. Measurements show that the mixer operates from room temperature up to 500 °C. The conversion gain is 15 dB at 25 °C, which decreases to 4.7 dB at 500 °C. The input 1-dB compression point is 1 dBm at 25 °C and −2.5 dBm at 500 °C. The mixer is biased with a collector current of 10 mA from a 20 V supply and has a maximum DC power consumption of 204 mW. High-temperature reliability evaluation of the mixer shows a conversion gain degradation of 1.4 dB after 3-hours of continuous operation at 500 °C.

  • 24.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A 14-ENOB Delta-Sigma-Based Readout Architecture for ECoG Recording Systems2018In: IEEE Transactions on Circuits and Systems Part 1: Regular Papers, ISSN 1549-8328, E-ISSN 1558-0806, Vol. 05Article in journal (Refereed)
    Abstract [en]

    This paper presents a delta-sigma based readout architecture targeting electrocortical recording in brain stimulation applications. The proposed architecture can accurately record a peak input signal up to 240 mV in a power-efficient manner without saturating or employing offset rejection techniques. The readout architecture consists of a delta-sigma modulator with an embedded analog front-end. The proposed architecture achieves a total harmonic distortion of -95 dB by employing a current-steering DAC and a multi-bit quantizer implemented as a tracking ADC. A system prototype is implemented in a 0.18 μm CMOS triple-well process and has a total power consumption of 54 μW. Measurement results, across 10 packaged samples, show approximately 14-ENOB over a 300Hz bandwidth with an input referred noise of 5.23 μVrms, power-supply/common-mode rejection ratio of 100 dB/98 dB and an input impedance larger than 94 MΩ.

  • 25.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Area-Efficient Switched-Capacitor Integrator with Flicker Noise Cancellation2018Conference paper (Refereed)
    Abstract [en]

    A fully differential switched-capacitor circuit that combines the functionality of a voltage buffer and an integrator is proposed. The employed switching scheme exhibits intrinsic flicker noise canceling properties, whereas conventional techniques require additional circuit components. The circuit has been designed in a 0.18 μm CMOS process for 1.8 V supply. The estimated power consumption is 13.5 μW, while the occupied area is 121×442 μm2. Area-efficient design is achieved by exploiting the correlation between the effective noise bandwidth and noise floor density in the proposed circuit. The sampled input referred noise floor is −133 dBV/√Hz, which is remarkably low when considering that the sampling capacitance is just 1.8 pF.

  • 26.
    Ivanisevic, Nikola
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rodriguez, Saul
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Rusu, Ana
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Impedance spectroscopy systems: Review and an all-digital adaptive IIR filtering approach2017In: 2017 IEEE Biomedical Circuits and Systems Conference, Turin, October 19-21, 2017, Turin, Italy: Institute of Electrical and Electronics Engineers (IEEE), 2017Conference paper (Refereed)
    Abstract [en]

    Impedance spectroscopy is a low-cost sensing technique that is generating considerable interest in wearable and implantable biomedical applications since it can be efficiently integrated on a single microchip. In this paper, the fundamental characteristics of the most well-known system architectures are presented, and a more robust and hardware-efficient solution is proposed. An all-digital implementation based on adaptive filtering is used for identifying the impedance parameters of a sample-under-test. The coefficients of an infinite-impulse-response (IIR) filter are tuned by an adaptive algorithm based on pseudo-linear regression and output-error formulation. A three-level pseudorandom noise generator with a concave power spectral density is employed without deteriorating the nominal performance. Proof-of-concept has been verified with behavioral simulations.

  • 27.
    Jayakumar, Ganesh
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Silicon nanowire based devices for More than Moore Applications2018Doctoral thesis, monograph (Other academic)
    Abstract [en]

    Silicon nanowires (SiNW) are in the spotlight for a few years in the research community as a good candidate for biosensing applications. This is attributed to their small dimensions in nanometer scale that offers high sensitivity, label-free detection and at the same time utilizing small amount of sample. While the recent research has concentrated predominantly on utilizing single or multiple SiNW for biosensing applications, very few attempts have been made to integrate SiNW with complementary-metal-oxide- semiconductor (CMOS) integration to arrive at a complete lab-on-chip (LOC) sensor. Further, the manufacturing methods reported thus far in the production of SiNW for biosensing applications have not fully exploited both the front-end-of-line (FEOL) as well as back-end-of-line (BEOL) methods in CMOS integration. Neither does the research community address CMOS integration based methods to realize multi and specific target detection that are important attributes for an ideal LOC biosensor.

    Integration of SiNW with CMOS circuitry will facilitate real time detection of the output signal and in addition provide a compact small sized sensor that is fully portable operating at high speed. In order to avail the benefits of CMOS circuits and develop a large scale production friendly LOC sensor, the scheme of SiNW fabrication has to facilitate either the FEOL or BEOL CMOS integration schemes. This thesis work is focused on revealing a novel FEOL as well as BEOL scheme for integration of SiNW with CMOS circuitry. The major part of the FEOL research work is concentrated on developing a high volume SiNW manufacturing method that is suitable for industrial production. Likewise, in the BEOL scheme, predominant focus was to develop a wafer scale scheme to integrate network of nanowires (nanonets) with CMOS circuitry to manufacture a monolithic 3D above-IC LOC biosensor.

    In the FEOL scheme, the SiNWs are fabricated using a revised pattern transfer technique called sidewall transfer lithography (STL). The STL method is identified as one of the efficient methods of fabricating SiNW as it uses CMOS industry grade materials that is fully compatible with the FEOL fabrication scheme. Thanks to the usage of single lithography and controlled selective etching techniques used in the STL process, the line width and aspect ratio of the SiNW can be tailored to suit the requirements for DNA hybridization detection. A fabrication process flow matching standard CMOS process integration flows has been developed to integrate SiNW with HfO2 and TiN metal gate MOSFETS. An emphasis has been placed in the design of a novel pixel matrix based SiNW LOC sensor. Specific and multi-target detection has been kept as top priority in the design of the SiNW LOC sensor. The possibility to monitor the potential of the electrolyte during the detection process using a fluid gate has been accounted in this design. Furthermore, the SiNW pixel design eliminates the intricate microfluidics and eases access to the SiNW test site using a simple photolithography mask and RIE. The SiNW and MOSFETS demonstrate excellent electrical characteristics. For the very first time, the concept to access single as well as multiple array SiNW pixels using a transistor has been successfully demonstrated.

    In the BEOL scheme, the nanonets are fabricated using the bottom-up method and transferred onto a pre-fabricated CMOS wafer supplied by ams foundry. The connection between the nanonets lying above-IC and the underlying CMOS layer was established by employing a thin metal backgate electrode, backgate dielectric and metal source/drain contact pads. Many challenges in the BEOL scheme have been identified and overcome by incorporating efficient device architecture and careful selection of materials. To the first of its kind, a wafer scale process was developed to integrate nanonets with CMOS to form a monolithic 3D IC. The devices exhibit excellent electrical characteristics and lower leakage currents compared to standalone nanonet sensors fabricated on Si/SiN substrate. Further, the FEOL and BEOL integration schemes are compared and the various pro’s and con’s of both approaches for integration of SiNW with CMOS circuits to build a LOC biosensor are discussed in detail.

    Finally, dry environment DNA hybridization detection is demonstrated on the surface of thin HfO2 encapsulated SiNW sensors. Upon DNA hybridization, SiNW devices exhibit threshold voltage shift larger than the noise introduced by the exposition to saline solutions used for the bio-processes. More specifically, based on a statistical analysis, it is demonstrated that 85% of the tested devices were efficient for DNA hybridization detection. The estimated density of hybridized DNA was in the order of 1010 cm-2. These promising results of realizing a SiNW based lab-on-chip platform through the FEOL and BEOL monolithic integration of SiNW and CMOS circuitry further strengthen the profile of SiNW as a nano biosensor. Indeed, this is expected to pave the way for more than Moore applications of SiNW based devices and integrated circuits.

  • 28.
    Jayakumar, Ganesh
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Hellström, Per-Erik
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Monolithic Wafer Scale Integration of Silicon Nanoribbon Sensors with CMOS for Lab-on-Chip Application2018In: Micromachines, ISSN 2072-666X, E-ISSN 2072-666X, Vol. 9, no 11, article id 544Article in journal (Refereed)
    Abstract [en]

    Silicon ribbons (SiRi) have been well-established as highly sensitive transducers for biosensing applications thanks to their high surface to volume ratio. However, selective and multiplexed detection of biomarkers remains a challenge. Further, very few attempts have been made to integrate SiRi with complementary-metal-oxide-semiconductor (CMOS) circuits to form a complete lab-on-chip (LOC). Integration of SiRi with CMOS will facilitate real time detection of the output signal and provide a compact small sized LOC. Here, we propose a novel pixel based SiRi device monolithically integrated with CMOS field-effect-transistors (FET) for real-time selective multiplexed detection. The SiRi pixels are fabricated on a silicon-on-insulator wafer using a top-down method. Each pixel houses a control FET, fluid-gate (FG) and SiRi sensor. The pixel is controlled by simultaneously applying frontgate (V-G) and backgate voltage (V-BG). The liquid potential can be monitored using the FG. We report the transfer characteristics (I-D-V-G) of N- and P-type SiRi pixels. Further, the I-D-V-G characteristics of the SiRis are studied at different V-BG. The application of V-BG to turn ON the SiRi modulates the subthreshold slope (SS) and threshold voltage (V-TH) of the control FET. Particularly, N-type pixels cannot be turned OFF due to the control NFET operating in the strong inversion regime. This is due to large V-BG (25 V) application to turn ON the SiRi sensor. Conversely, the P-type SiRi sensors do not require large V-BG to switch ON. Thus, P-type pixels exhibit excellent I-ON/I-OFF 10(6), SS of 70-80 mV/dec and V-TH of 0.5 V. These promising results will empower the large-scale cost-efficient production of SiRi based LOC sensors.

  • 29.
    Jin, Yi
    et al.
    Fudan Univ, Shanghai, Peoples R China..
    Huan, Yuxiang
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Fudan Univ, Shanghai, Peoples R China..
    Chu, Haoming
    Fudan Univ, Shanghai, Peoples R China..
    Zou, Zhuo
    Fudan Univ, Shanghai, Peoples R China..
    Zheng, Li-rong
    KTH. Fudan Univ, Shanghai, Peoples R China..
    TMR Group Coding Method for Optimized SEU and MBU Tolerant Memory Design2018In: 2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), IEEE , 2018Conference paper (Refereed)
    Abstract [en]

    This work proposes a fault tolerant memory design using the method of Triple Module Redundancy (TMR) group coding to tolerant the Single-Event Upset (SEU) and Multi-Bit Upset (MBU) influence on memory devices in space environment. The group coding method uses different models to partition and code each word line in memory with Hamming code to achieve best performance. TMR group coding method further increases the capability of self-correction for the errors occurred in parity bits. The evaluation results show that the suggested approach can obtain improved correctness for the memory output with optimized tradeoff between reliability and cost. At 5% error rate, the probability of correct output reaches 70.78% with small cost increment. To achieve 90% reliability, the accuracy improvement is 31.9% compared to TMR with 9% increased area. This solution proposed is evaluated on the memory rich micro-coded processor, but can be further extended to other memory-based processors that need high reliability for the SEU and MBU influence in aerospace applications.

  • 30.
    Kajihara, J.
    et al.
    Japan.
    Kuroki, S. -I
    Japan.
    Ishikawa, S.
    Japan.
    Maeda, T.
    Japan.
    Sezaki, H.
    japan.
    Makino, T.
    Japan.
    Ohshima, T.
    japan.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    4H-SiC pMOSFETs with al-doped S/D and NbNi silicide ohmic contacts2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications, 2018, p. 423-427Conference paper (Refereed)
    Abstract [en]

    4H-SiC pMOSFETs with Al-doped S/D and NbNi silicide ohmic contacts were demonstrated and were characterized at up to a temperature of 200°C. For the pMOSFETs, silicides on p-type 4H-SiC with Nb/Ni stack, Nb-Ni Alloy, Ni and Nb/Ti were investigated, and the Nb/Ni stack silicide with the contact resistance of 5.04×10-3 Ωcm2 were applied for the pMOSFETs.

  • 31.
    Kelati, Amleset
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. university of Turku.
    BioSignal Monitoring tool Using Wearable IoT2018In: Proceedings of the 22nd IEEE FRUCT conference,, Jyvaskyla, 2018, p. 4-8Conference paper (Refereed)
  • 32.
    Kelati, Amleset
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Univ Turku, Turku, Finland..
    Ben Dhaou, Imed
    Qassim Univ, Buraydah, Saudi Arabia.;Univ Monastir, Monastir, Tunisia..
    Taajamaa, Ville
    Univ Turku, Turku, Finland..
    Rwegasira, Diana
    Royal Inst Technol, Stockholm, Sweden.;Univ Dar Es Salaam, Dar Es Salaam, Tanzania..
    Kondoro, Aron
    Royal Inst Technol, Stockholm, Sweden.;Univ Dar Es Salaam, Dar Es Salaam, Tanzania..
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Univ Turku, Turku, Finland..
    Mvungi, Nerey
    Univ Dar Es Salaam, Dar Es Salaam, Tanzania..
    CHALLENGES FOR TEACHING AND LEARNING ACTIVITIES (TLA) AT ENGINEERING EDUCATION2018In: 12TH INTERNATIONAL TECHNOLOGY, EDUCATION AND DEVELOPMENT CONFERENCE (INTED) / [ed] Chova, LG Martinez, AL Torres, IC, IATED-INT ASSOC TECHNOLOGY EDUCATION & DEVELOPMENT , 2018, p. 9093-9098Conference paper (Refereed)
    Abstract [en]

    In the knowledge-based society, the legacy education system does not provide the needed skills for creative engineers especially enhancing student innovation and entrepreneurship capacity. Triple-helix model is a concept that aims to bond universities, industry and government in a bid to create innovations. In Europe, integrating research, education, and innovation together in a comprehensive manner has been the major driving force for local and European university development, as example in the form of European Institute Innovation Technology (EIT). At KTH, there are activities that alien the Teaching and Learning Activities (TLA) with different task group with the aim of creating a mutual innovation capacity to contribute solutions for major social challenges. Some of these task groups are Cross-Cultural Faculty Development for Challenge Driven Education, Global learning and digital platform and open innovation platform for learning. The progress and the success are measured by the number of joint student teams and their skills, knowledge development with the follow-up workshop, and the ongoing research and results of the socio-oriented projects. To enhance TLA and the teaching and learning practices, we have developed new curriculums (MSc. and PhD) for our partners to spark innovation and entrepreneurship where the students interact with Open Lab activities. The assessments show that the enrolled students have gained creative skills in dealing with engineering problem and consolidate their knowledge to improve the future TLA and the Intended Learning Outcome (ILO).

  • 33.
    Kelati, Amleset
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. University of Turku, Finland.
    Nigussie, Ethiopia
    University of Turku, Finland.
    Plosila, Juha
    University of Turku, Finland.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. University of Turku, Finland.
    Biosignal Feature Extraction Techniques for IoT Healthcare Platform2016In: IEEE Conference on Design and Architectures for Signal and Image Processing (DASIP2016), Rennes, France, 2016Conference paper (Other (popular science, discussion, etc.))
    Abstract [en]

    In IoT healthcare platform, a variety of biosignals are acquired from its sensors and appropriate feature extraction techniques are crucial in order to make use of the acquired biosignal data and help the healthcare scientist or bio-engineer to reach at optimal decisions. This work reviews the existing biosignal feature extraction and classification methods for different healthcare applications. Due the enormous amount of different biosignals and since most healthcare applications uses electrocardiogram (ECG), electroencephalogram (EEG), electromyogram (EMG), Electrogastrogram (EGG), we focus the review on feature extractions and classification method for these biosignals. The review also includes a summary of Blood Oxygen Saturation determined by Pulse Oximetry (SpO2), Electrooculography and eye movement (EOG), and Respiration (RSP) signals. Its discussion and analysis focuses on advantages, performance and drawbacks of the techniques.

  • 34. Kurose, T.
    et al.
    Kuroki, S. -I
    Ishikawa, S.
    Maeda, T.
    Sezaki, H.
    Makino, T.
    Ohshima, T.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Low-parasitic-capacitance self-aligned 4H-SiC nMOSFETs for harsh environment electronics2018In: Materials Science Forum, ISSN 0255-5476, E-ISSN 1662-9752, Vol. 924, p. 971-974Article in journal (Refereed)
    Abstract [en]

    Low-parasitic-capacitance 4H-SiC nMOSFETs using a novel self-aligned process were suggested and demonstrated. In these nMOSFETs, device characteristics including parasitic capacitances (gate-source, gate-drain, drain-source capacitance) were investigated and low parasitic capacitance was achieved by the self-aligned structure

  • 35.
    Li, Pu
    et al.
    Taiyuan Univ Technol, Minist Educ, Key Lab Adv Transducers & Intelligent Control Sys, Taiyuan 030024, Shanxi, Peoples R China.;Taiyuan Univ Technol, Coll Phys & Optoelect, Inst Optoelect Engn, Taiyuan 030024, Shanxi, Peoples R China.;Bangor Univ, Sch Elect Engn, Bangor LL57 1UT, Gwynedd, Wales.;Inst Southwestern Commun, Sci & Technol Commun Lab, Chengdu 610041, Sichuan, Peoples R China..
    Guo, Ya
    Taiyuan Univ Technol, Minist Educ, Key Lab Adv Transducers & Intelligent Control Sys, Taiyuan 030024, Shanxi, Peoples R China.;Taiyuan Univ Technol, Coll Phys & Optoelect, Inst Optoelect Engn, Taiyuan 030024, Shanxi, Peoples R China..
    Guo, Yanqiang
    Taiyuan Univ Technol, Minist Educ, Key Lab Adv Transducers & Intelligent Control Sys, Taiyuan 030024, Shanxi, Peoples R China.;Taiyuan Univ Technol, Coll Phys & Optoelect, Inst Optoelect Engn, Taiyuan 030024, Shanxi, Peoples R China..
    Fan, Yuanlong
    Bangor Univ, Sch Elect Engn, Bangor LL57 1UT, Gwynedd, Wales..
    Guo, Xiaomin
    Taiyuan Univ Technol, Minist Educ, Key Lab Adv Transducers & Intelligent Control Sys, Taiyuan 030024, Shanxi, Peoples R China.;Taiyuan Univ Technol, Coll Phys & Optoelect, Inst Optoelect Engn, Taiyuan 030024, Shanxi, Peoples R China..
    Liu, Xianglian
    Taiyuan Univ Technol, Minist Educ, Key Lab Adv Transducers & Intelligent Control Sys, Taiyuan 030024, Shanxi, Peoples R China.;Taiyuan Univ Technol, Coll Phys & Optoelect, Inst Optoelect Engn, Taiyuan 030024, Shanxi, Peoples R China..
    Shore, K. Alan
    Bangor Univ, Sch Elect Engn, Bangor LL57 1UT, Gwynedd, Wales..
    Dubrova, Elena
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Xu, Bingjie
    Inst Southwestern Commun, Sci & Technol Commun Lab, Chengdu 610041, Sichuan, Peoples R China..
    Wang, Yuncai
    Taiyuan Univ Technol, Minist Educ, Key Lab Adv Transducers & Intelligent Control Sys, Taiyuan 030024, Shanxi, Peoples R China.;Taiyuan Univ Technol, Coll Phys & Optoelect, Inst Optoelect Engn, Taiyuan 030024, Shanxi, Peoples R China..
    Wang, Anbang
    Taiyuan Univ Technol, Minist Educ, Key Lab Adv Transducers & Intelligent Control Sys, Taiyuan 030024, Shanxi, Peoples R China.;Taiyuan Univ Technol, Coll Phys & Optoelect, Inst Optoelect Engn, Taiyuan 030024, Shanxi, Peoples R China..
    Self-balanced real-time photonic scheme for ultrafast random number generation2018In: APL PHOTONICS, ISSN 2378-0967, Vol. 3, no 6, article id 061301Article in journal (Refereed)
    Abstract [en]

    We propose a real-time self-balanced photonic method for extracting ultrafast random numbers from broadband randomness sources. In place of electronic analog-to-digital converters (ADCs), the balanced photo-detection technology is used to directly quantize optically sampled chaotic pulses into a continuous random number stream. Benefitting from ultrafast photo-detection, our method can efficiently eliminate the generation rate bottleneck from electronic ADCs which are required in nearly all the available fast physical random number generators. A proof-of-principle experiment demonstrates that using our approach 10 Gb/s real-time and statistically unbiased random numbers are successfully extracted from a bandwidth-enhanced chaotic source. The generation rate achieved experimentally here is being limited by the bandwidth of the chaotic source. The method described has the potential to attain a real-time rate of 100 Gb/s.

  • 36.
    Linnarsson, Margareta K.
    et al.
    KTH.
    Ayedh, H. M.
    Hallén, Anders
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Vines, L.
    Svensson, B. G.
    Surface erosion of ion-implanted 4H-SiC during annealing with carbon cap2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications Inc., 2018, Vol. 924, p. 373-376Conference paper (Refereed)
    Abstract [en]

    The stability/ erosion of the interface between a C-cap and 4H-SiC have been studied by secondary ion mass spectrometry (SIMS). Aluminum implantation has been used to monitor the position of the moving interface as well as to investigate the influence on the interface stability by the crystal quality of the 4H-SiC. After Al implantation a C-cap has been deposited by pyrolysis of photoresist. Subsequent annealing has been performed at 1900 and 2000 °C with durations between 15 minutes and 1 hour. SIMS measurements have been performed without removal of the C-cap. The surface remains smooth after the heat treatment, but a large amount of SiC material from the uppermost part of the wafer is lost. The amount of lost material is related to for instance annealing temperature, ambient conditions and ion induced crystal damage. This contribution gives a brief account of the processes governing the SiC surface decomposition during C-cap post implant annealing.

  • 37. Liu, S. -C
    et al.
    Zhao, D.
    Reuterskiold-Hedlund, Carl
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Liu, Z.
    Hammar, Mattias
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Zhou, W.
    Electrically pumped hybrid III-V/Si photonic crystal surface emitting lasers with buried tunnel-junction2018In: Optics InfoBase Conference Papers, Optical Society of America, 2018Conference paper (Refereed)
    Abstract [en]

    We report here an electrically pumped hybrid photonic crystal surface emitting laser (PCSELs) on silicon. The laser cavity consists of a transferred InGaAsP multi-quantum well (MQW) heterostructure membrane, printed on a single layer silicon photonic crystal (Si-PC) cavity. A buried tunnel-junction (BTJ) has been employed in the MQW structure for efficiency charge injection. Single mode emitted spectrum was achieved at 1504 nm for a large area laser in the continuous-wave (c.w.) mode under room temperature operation.

  • 38.
    Loiko, Pavel
    et al.
    ITMO Univ, 49 Kronverkskiy Pr, St Petersburg 197101, Russia..
    Maria Serres, Josep
    Univ Rovira & Virgili, Fis & Cristallog Mat & Nanomat FiCMA FiCNA, Campus Sescelades,C Marcelli Domingo S-N, E-43007 Tarragona, Spain..
    Delekta, Szymon Sollami
    KTH, School of Information and Communication Technology (ICT).
    Kifle, Esrom
    Univ Rovira & Virgili, Fis & Cristallog Mat & Nanomat FiCMA FiCNA, Campus Sescelades,C Marcelli Domingo S-N, E-43007 Tarragona, Spain..
    Mateos, Xavier
    Univ Rovira & Virgili, Fis & Cristallog Mat & Nanomat FiCMA FiCNA, Campus Sescelades,C Marcelli Domingo S-N, E-43007 Tarragona, Spain.;Max Born Inst Nonlinear Opt & Short Pulse Spect, 2A Max Born Str, D-12489 Berlin, Germany..
    Baranov, Alexander
    ITMO Univ, 49 Kronverkskiy Pr, St Petersburg 197101, Russia..
    Aguilo, Magdalena
    Univ Rovira & Virgili, Fis & Cristallog Mat & Nanomat FiCMA FiCNA, Campus Sescelades,C Marcelli Domingo S-N, E-43007 Tarragona, Spain..
    Diaz, Francesc
    Univ Rovira & Virgili, Fis & Cristallog Mat & Nanomat FiCMA FiCNA, Campus Sescelades,C Marcelli Domingo S-N, E-43007 Tarragona, Spain..
    Griebner, Uwe
    Max Born Inst Nonlinear Opt & Short Pulse Spect, 2A Max Born Str, D-12489 Berlin, Germany..
    Petrov, Valentin
    Max Born Inst Nonlinear Opt & Short Pulse Spect, 2A Max Born Str, D-12489 Berlin, Germany..
    Popov, Sergei
    KTH, School of Engineering Sciences (SCI), Applied Physics, Photonics.
    Li, Jiantong
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Information and Communication Technology (ICT).
    Inkjet-Printing of Graphene Saturable Absorbers for similar to 2 mu m Bulk and Waveguide Lasers2017In: 2017 CONFERENCE ON LASERS AND ELECTRO-OPTICS (CLEO), IEEE , 2017Conference paper (Refereed)
    Abstract [en]

    We report on inkjet-printing of graphene saturable absorbers (SAs) suitable for passive Q-switching of similar to 2-mu m bulk and waveguide lasers. Using graphene-SA in a microchip Tm:KLu(WO4)(2) laser, 1.2 mu J/136 ns pulses are generated at 1917 nm.

  • 39.
    Lu, Zhonghai
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Yao, Yuan
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Thread Voting DVFS for Manycore NoCs2018In: I.E.E.E. transactions on computers (Print), ISSN 0018-9340, E-ISSN 1557-9956, Vol. 67, no 10, p. 1506-1524, article id 8338086Article in journal (Refereed)
    Abstract [en]

    We present a thread-voting DVFS technique for manycore networks-on-chip (NoCs). This technique has two remarkable features which differentiate from conventional NoC DVFS schemes. (1) Not only network-level but also thread-level runtime performance indicatives are used to guide DVFS decisions. (2) To resolve multiple perhaps conflicting performance indicatives from many cores, it allows each thread to 'vote' for a V/F level in its own performance interest, and a region-based V/F controller makes dynamic per-region V/F decision according to the major vote. We evaluate our technique on a 64-core CMP in full-system simulation environment GEM5 with both PARSEC and SPEC OMP2012 benchmarks. Compared to a network metric (router buffer occupancy) based approach, it can improve the network energy efficacy measured in MPPJ (million packets per joule) by up to 22 percent for PARSEC and 20 percent for SPEC OMP2012, and the system energy efficacy measured in MIPJ (million instructions per joule) by up to 35 percent for PARSEC and 33 percent for SPEC OMP2012. 

  • 40. Negash, B.
    et al.
    Westerlund, T.
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Towards an interoperable Internet of Things through a web of virtual things at the Fog layer2019In: Future generations computer systems, ISSN 0167-739X, E-ISSN 1872-7115, Vol. 91, p. 96-107Article in journal (Refereed)
    Abstract [en]

    A wide range of Internet of Things devices, platforms and applications have been implemented in the past decade. The variation in platforms, communication protocols and data formats of these systems creates islands of applications. Many organizations are working towards standardizing the technologies used at different layers of communication in these systems. However, interoperability still remains one of the main challenges towards realizing the grand vision of IoT. Intergration approaches proven in the existing Internet or enterprise applications are not suitable for the IoT, mainly due to the nature of the devices involved; the majority of the devices are resource constrained. To address this problem of interoperability, our work considers various types of IoT application domains, architecture of the IoT and the works of standards organizations to give a holistic abstract model of IoT. According to this model, there are three computing layers, each with a different level of interoperability needs — technical, syntactic or semantic. This work presents a Web of Virtual Things (WoVT) server that can be deployed at the middle layer of IoT (Fog layer) and Cloud to address the problem of interoperability. It exposes a REST like uniform interface for syntactic integration of devices at the bottom layer of IoT (perception layer). An additional RESTful api is used for integration with other similar WoVT servers at the Fog or the Cloud layer. The server uses a state of the art architecture to enable this integration pattern and provides means towards semantic interoperability. The analysis and evaluation of the implementation, such as performance, resource utilization and security perspectives, are presented. The simulation results demonstrate that an integrated and scalable IoT through the web of virtual things can be realized.

  • 41.
    Quellmalz, Arne
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Elgammal, Karim
    KTH, School of Engineering Sciences (SCI), Applied Physics.
    Fan, Xuge
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Delin, Anna
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Lemme, Max C.
    Chair of Electronic Devices, RWTH Aachen University.
    Gylfason, Kristinn
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Influence of Humidity on Contact Resistance in Graphene Devices2018In: ACS Applied Materials and Interfaces, ISSN 1944-8244, E-ISSN 1944-8252, Vol. 10, no 48, p. 41738-41746Article in journal (Refereed)
    Abstract [en]

    The electrical contact resistance at metal–graphene interfaces can significantly degrade the properties of graphene devices and is currently hindering the full exploitation of graphene’s potential. Therefore, the influence of environmental factors, such as humidity, on the metal–graphene contact resistance is of interest for all graphene devices that operate without hermetic packaging. We experimentally studied the influence of humidity on bottom-contacted chemical-vapor-deposited (CVD) graphene–gold contacts, by extracting the contact resistance from transmission line model (TLM) test structures. Our results indicate that the contact resistance is not significantly affected by changes in relative humidity (RH). This behavior is in contrast to the measured humidity sensitivity  of graphene’s sheet resistance. In addition, we employ density functional theory (DFT) simulations to support our experimental observations. Our DFT simulation results demonstrate that the electronic structure of the graphene sheet on top of silica is much more sensitive to adsorbed water molecules than the charge density at the interface between gold and graphene. Thus, we predict no degradation of device performance by alterations in contact resistance when such contacts are exposed to humidity. This knowledge underlines that bottom-contacting of graphene is a viable approach for a variety of graphene devices and the back end of the line integration on top of conventional integrated circuits.

  • 42.
    Reuterskiold Hedlund, Carl
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Oberg, Olof
    RISE Acreo, Box 1070, SE-16425 Kista, Sweden..
    Lim, Jang-Kwon
    RISE Acreo, Box 1070, SE-16425 Kista, Sweden..
    Wang, Qin
    RISE Acreo, Box 1070, SE-16425 Kista, Sweden..
    Salter, Michael
    RISE Acreo, Box 1070, SE-16425 Kista, Sweden..
    Hammar, Mattias
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Trench-Confined InP-Based Epitaxial Regrowth Using Metal-Organic Vapor-Phase Epitaxy2018In: Physica Status Solidi (a) applications and materials science, ISSN 1862-6300, E-ISSN 1862-6319, Vol. 215, no 8, article id 1700454Article in journal (Refereed)
    Abstract [en]

    In this study, an area-selective metal-organic vapor-phase epitaxy (MOVPE) for trench-confined InP-based epitaxial regrowth in-between arrayed rectangular-shaped device elements is reported. Test structures are fabricated to investigate the influence of MOVPE growth and other processing parameters on regrowth control, doping incorporation, and morphology. For correctly chosen crystallographic mesa orientation and mask geometry, good control of growth selectivity, layer morphology, and doping concentration can be achieved, although with an enhanced and non-constant growth rate. This is discussed in terms of orientation-dependent growth rate and loading effects. In addition, a selective etch and regrowth approach which allows for the processing of field-effect transistors of significance for spatial light modulators with trench-integrated driver electronics is successfully implemented.

  • 43.
    Rosvall, Kathrin
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Mohammadat, Tage
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Ungureanu, George
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Öberg, Johnny
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Sander, Ingo
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Exploring Power and Throughput for Dataflow Applications on Predictable NoC Multiprocessors2018Conference paper (Refereed)
    Abstract [en]

    System level optimization for multiple mixed-criticality applications on shared networked multiprocessor platforms is extremely challenging. Substantial complexity arises from the interdependence between the multiple subproblems of mapping, scheduling and platform configuration under the consideration of several, potentially orthogonal, performance metrics and constraints. Instead of using heuristic algorithms and problem decomposition, novel unified design space exploration (DSE) approaches based on Constraint Programming (CP) have in the recent years shown promising results. The work in this paper takes advantage of the modularity of CP models, in order to support heterogeneous multiprocessor Network-on-Chip (NoC) with Temporally Disjoint Networks (TDNs) aware message injection. The DSE supports a range of design criteria, in particular the optimization and satisfaction of power and throughput. In addition, the DSE now provides a valid configuration for the TDNs that guarantees the performance required to fulfil the design goals. The experiments show the capability of the approach to find low-power and high-throughput designs, and validate a resulting design on a physical TDN-based NoC implementation.

  • 44.
    Salemi, Arash
    et al.
    KTH.
    Elahipanah, Hossein
    KTH.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Conductivity modulated and implantation-free 4H-SiC ultra-high-voltage PiN Diodes2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications Inc., 2018, p. 568-572Conference paper (Refereed)
    Abstract [en]

    Implantation-free mesa etched ultra-high-voltage 4H-SiC PiN diodes are fabricated, measured and analyzed by device simulation. The diode’s design allows a high breakdown voltage of about 19.3 kV according to simulations. No reverse breakdown is observed up to 13 kV with a very low leakage current of 0.1 μA. A forward voltage drop (VF) and differential on-resistance (Diff. Ron) of 9.1 V and 41.4 mΩ cm2 are measured at 100 A/cm2, respectively, indicating the effect of conductivity modulation.

  • 45. Satti, Javeria Anum
    et al.
    Habib, Ayesha
    Anam, Hafsa
    Zeb, Sumra
    Amin, Yasar
    KTH, School of Information and Communication Technology (ICT), Centres, VinnExcellence Center for Intelligence in Paper and Packaging, iPACK. KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Loo, Jonathan
    Tenhunen, Hannu
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Miniaturized humidity and temperature sensing RFID enabled tags2018In: International Journal of RF and Microwave Computer-Aided Engineering, ISSN 1096-4290, E-ISSN 1099-047X, Vol. 28, no 1, article id e21151Article in journal (Refereed)
    Abstract [en]

    A compact 27-bit linearly polarized chipless radio frequency identification tag is presented in this research. The proposed tag is designed with an overall tag dimension of 23 x 23 mm(2). The tag comprises of metallic (copper) rings-based structure loaded with slots. These slots correspond to a particular sequence of bits. The circular tag is analysed using 2 different substrates, that is, Rogers RT/duroid/5870 and flexible Rogers RT/duroid/5880. The radar cross-section response of frequency signatured tag is analysed for humidity and temperature sensor designs. Humidity sensing is achieved by deploying a DuPont Kapton HN heat resistant sheet on the shortest slot of the tag, that is, the sensing slot. Temperature sensing is attained using Rogers RT/duroid/5870 and Stanyl polyamide as a combined substrate. Hence, the miniaturized, robust, and flexible tag can be deployed over irregular surfaces for sensing purposes.

  • 46. Scott, J. D.
    et al.
    Flener, P.
    Pearson, J.
    Schulte, Christian
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics.
    Design and implementation of bounded-length sequence variables2017In: 14th International Conference on Integration of Artificial Intelligence and Operations Research Techniques in Constraint Programming, CPAIOR 2017, Springer, 2017, Vol. 10335, p. 51-67Conference paper (Refereed)
    Abstract [en]

    We present the design and implementation of bounded -length sequence (BLS) variables for a CP solver. The domain of a BLS variable is represented as the combination of a set of candidate lengths and a sequence of sets of candidate characters. We show how this representation, together with requirements imposed by propagators, affects the implementation of BLS variables for a copying CP solver, most importantly the closely related decisions of data structure, domain restriction operations, and propagation events. The resulting implementation outperforms traditional bounded-length string representations for CP solvers, which use a fixed-length array of candidate characters and a padding symbol.

  • 47. Severikov, V. S.
    et al.
    Grishin, Alexander M.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. Petrozavodsk State University, Petrozavodsk, Karelian, 185910, Russian Federation; INMATECH Intelligent Materials Technology, Skärholmen, SE-127 51, Sweden.
    Ignakhin, V. S.
    Magnetostriction in Fe80-xCoxP14B6 amorphous ribbons evaluated by Becker-Kersten method2018In: Journal of Physics: Conference Series, Institute of Physics Publishing (IOPP), 2018, Vol. 1038, no 1, article id 012066Conference paper (Refereed)
    Abstract [en]

    Becker-Kersten method, which involves observing hysteresis M-H loops under mechanical stress, was applied to measure magnetostriction properties in amorphous rapid quenched ribbons Fe80-xCoxP14B6. It is shown that magnetostriction constant increases with the growth of cobalt atomic content from (1.75 ± 0.13)×10-6 for x = 25 to (1.60 ± 0.05)×10-5 for x = 40.

  • 48.
    Shakir, Muhammad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Elahipanah, Hossein
    KTH.
    Hedayati, Raheleh
    KTH.
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Electrical characterization of integrated 2-input TTL NAND Gate at elevated temperature, fabricated in bipolar SiC-technology2018In: International Conference on Silicon Carbide and Related Materials, ICSCRM 2017, Trans Tech Publications Inc., 2018, Vol. 924, p. 958-961Conference paper (Refereed)
    Abstract [en]

    This work presents the design and electrical characterization of in-house-fabricated 2-input NAND gate. The monolithic bipolar 2-input NAND gate employing transistor-transistor logic (TTL) is demonstrated in 4H-SiC and operates over a wide range of temperature and supply voltage. The fabricated circuit was characterized on the wafer by using a hot-chuck probe-station from 25 °C up to 500 °C. The circuit is also characterized over a wide range of voltage supply i.e. 11 to 20 V. The output-noise margin high (NMH) and output-noise margin low (NML) are also measured over a wide range of temperatures and supply voltages using voltage transfer characteristics (VTC). The transient response was measured by applying two square waves of, 5 kHz and 10 kHz. It is demonstrated that the dynamic parameters of the circuit are temperature dependent. The 2-input TTL NAND gate consumes 20 mW at 500 °C and 15 V.

  • 49.
    Shakir, Muhammad
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Hou, Shuoben
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Malm, Bengt Gunnar
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS).
    Zetterling, Carl-Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    A 600 degrees C TTL-Based 11-Stage Ring Oscillator in Bipolar Silicon Carbide Technology2018In: IEEE Electron Device Letters, ISSN 0741-3106, E-ISSN 1558-0563, Vol. 39, no 10, p. 1540-1543Article in journal (Refereed)
    Abstract [en]

    Ring oscillators (ROs) are used to study the high-temperature characteristics of an in-house silicon carbide (SiC) technology. Design and successful operation of the in-house-fabricated 4H-SiC n-p-n bipolar transistors and TTL inverter-based 11-stage RO are reported from 25 degrees C to 600 degrees C. Non-monotonous temperature dependence was observed for the oscillator frequency; in the range of 25 degrees C to 300 degrees C, it increased with the temperature (1.33 MHz at 300 degrees C and V-CC = 15 V), while it decreased in the range of 300 degrees C-600 degrees C. The oscillator output frequency and delay were also characterized over a wide range of supply voltage (10 to 20 V). The noise margins of the TTL inverter were also measured; noise margin low (NML) decreases with the temperature, whereas noise margin high (NMH) increases with the temperature. The measured power-delay product (P-D . T-P) of the TTL inverter and 11-stage RO was approximate to 4.5 and approximate to 285 nJ, respectively, at V-CC= 15 V. Reliability testing indicated that the RO frequency of oscillation decreased 16% after HT characterization.

  • 50.
    Shi, Xin
    et al.
    Huazhong Univ Sci & Technol, Wuhan Natl Lab Optoelect, Wuhan, Hubei, Peoples R China..
    Wu, Fei
    Huazhong Univ Sci & Technol, Wuhan Natl Lab Optoelect, Wuhan, Hubei, Peoples R China..
    Wang, Shunzhuo
    Huazhong Univ Sci & Technol, Wuhan Natl Lab Optoelect, Wuhan, Hubei, Peoples R China..
    Xie, Changsheng
    Huazhong Univ Sci & Technol, Wuhan Natl Lab Optoelect, Wuhan, Hubei, Peoples R China..
    Lu, Zhonghai
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Electronic and embedded systems.
    Program Error Rate-based Wear Leveling for NAND Hash Memory2018In: PROCEEDINGS OF THE 2018 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), Institute of Electrical and Electronics Engineers (IEEE), 2018, p. 1241-1246Conference paper (Refereed)
    Abstract [en]

    Wear leveling scheme has became a fundamental issue in the design of Solid State Disk (SSD) based on NAND Flash memory. Existing schemes aim to equalize the number of programming/erase (P/E) cycles and memory raw bit error rates (BER) among all the flash blocks. However, due to fabrication process variation, different blocks of the same flash chip usually have largely different endurance in terns of BER and program error rate (PER). Such conventional design cannot obtain the wear status of flash blocks precisely. This paper proposes PER WE, an efficient PER-based wear leveling scheme that uses PER statistics as the measurement of Hash block wear-out pace, and performs block data swapping to improve the wear leveling efficiency. In our evaluation with four realistic workloads, PER based wear leveling scheme can achieve 17% and 9% variance of program error rate reduction, 8% and 3% program error rate reduction with 5% and 2% system performance degradation when compared to two state-of-the-art wear leveling schemes on average.

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