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  • 1.
    Angelin, Marcus
    et al.
    KTH, School of Industrial Engineering and Management (ITM).
    Vongvilai, Pornrapee
    KTH, School of Chemical Science and Engineering (CHE).
    Fischer, Andreas C.
    KTH, School of Chemical Science and Engineering (CHE).
    Ramstrom, Olof
    KTH, School of Chemical Science and Engineering (CHE).
    ORGN 103-Tandem driven dynamic libraries: Amplification through internal selection pressure2007In: Abstract of Papers of the American Chemical Society, ISSN 0065-7727, Vol. 234Article in journal (Other academic)
  • 2.
    Antelius, Mikael
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Hermetic integration of liquids using high-speed stud bump bonding for cavity sealing at the wafer level2012In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 22, no 4, p. 045021-Article in journal (Refereed)
    Abstract [en]

    This paper reports a novel room-temperature hermetic liquid sealing process where the access ports of liquid-filled cavities are sealed with wire-bonded stud bumps. This process enables liquids to be integrated at the fabrication stage. Evaluation cavities were manufactured and used to investigate the mechanical and hermetic properties of the seals. Measurements on the successfully sealed structures show a helium leak rate of better than 10 (10) mbarL s (1), in addition to a zero liquid loss over two months during storage near boiling temperature. The bond strength of the plugs was similar to standard wire bonds on flat surfaces.

  • 3.
    Antelius, Mikael
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Wafer-Level Vacuum Sealing by Coining of Wire Bonded Gold Bumps2013In: Journal of microelectromechanical systems, ISSN 1057-7157, E-ISSN 1941-0158, Vol. 22, no 6, p. 1347-1353Article in journal (Refereed)
    Abstract [en]

    This paper reports on the investigation of a novel room-temperature vacuum sealing method based on compressing wire bonded gold bumps which are placed to partially overlap the access ports into the cavity. The bump compression, which is done under vacuum, causes a material flow into the access ports, thereby hermetically sealing a vacuum inside the cavities. The sealed cavity pressure was measured by residual gas analysis to 8x10(-4) mbar two weeks after sealing. The residual gas content was found to be mainly argon, which indicates the source as outgassing inside the cavity and no measurable external leak. The seals are found to be mechanically robust and easily implemented by the use of standard commercial tools and processes.

  • 4.
    Antelius, Mikael
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Fischer, Andreas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Hermetic integration of liquids in MEMS by room temperature, high-speed plugging of liquid-filled cavities at wafer level2011In: Proceedings IEEE International Conference on Micro Electro Mechanical Systems (MEMS), IEEE , 2011, p. 356-359Conference paper (Other academic)
    Abstract [en]

    This paper reports a novel room temperature hermetic liquid sealing process based on wire bonded "plugs" over the access ports of liquid-filled cavities. The method enables liquids to be integrated already at the fabrication stage. Test vehicles were manufactured and used to investigate the mechanical and hermetic properties of the seals. A helium leak rate of better than 1E-10 mbarL/s was measured on the successfully sealed structures. The bond strength of the "plugs" were similar to standard wire bonds on flat surfaces.

  • 5.
    Antelius, Mikael
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Fischer, Andreas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Room-temperature wafer-level vacuum sealing by compression of high-speed wire bonded gold bumps2011In: Proceedings IEEE International Conference on Solid-State Sensors, Actuators, and Microsystems (Transducers), IEEE , 2011, p. 1360-1363Conference paper (Other academic)
    Abstract [en]

    This paper reports experimental results of a novel room temperature vacuum sealing process based on compressing wire bonded gold “bumps”, causing a material flow into the access ports of vacuum-cavities. The leak rate out of manufactured cavities was measured over 5 days and evaluated to less than the detection limit, 6×10-12 mbarL/s, per sealed port. The cavities have been sealed at a vacuum level below 10 mbar. The method enables sealing of vacuum cavities at room temperature using standard commercial tools and processes.

  • 6.
    Asiatici, Mikhail
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems. Ecole Polytech Fed Lausanne, Switzerland.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems. Karlsruhe Inst Technol,Germany.
    Rodjegard, Henrik
    Haasl, Sjoerd
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Capacitive inertial sensing at high temperatures of up to 400 degrees C2016In: Sensors and Actuators A-Physical, ISSN 0924-4247, E-ISSN 1873-3069, Vol. 238, p. 361-368Article in journal (Refereed)
    Abstract [en]

    High-temperature-resistant inertial sensors are increasingly requested in a variety of fields such as aerospace, automotive and energy. Capacitive detection is especially suitable for sensing at high temperatures due to its low intrinsic temperature dependence. In this paper, we present high-temperature measurements utilizing a capacitive accelerometer, thereby proving the feasibility of capacitive detection at temperatures of up to 400 degrees C. We describe the observed characteristics as the temperature is increased and propose an explanation of the physical mechanisms causing the temperature dependence of the sensor, which mainly involve the temperature dependence of the Young's modulus and of the viscosity and the pressure of the gas inside the sensor cavity. Therefore a static electromechanical model and a dynamic model that takes into account squeeze film damping were developed.

  • 7.
    Bleiker, Simon J.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems. Karlsruhe Institute of Technology (KIT), Germany.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    High-speed Metal-filling of Through-Silicon Vias (TSVs) by Parallelized Magnetic Assembly of Micro-Wires2016In: 2016 IEEE 29th International Conference on Micro Electro Mechanical Systems (MEMS), Institute of Electrical and Electronics Engineers (IEEE), 2016, p. 577-580Conference paper (Refereed)
    Abstract [en]

    This work reports a parallelized magnetic assembly method for scalable and cost-effective through-silicon via (TSV) fabrication. Our fabrication approach achieves high throughput by utilizing multiple magnets below the substrate to assemble TSV structures on many dies in parallel. Experimental results show simultaneous filling of four arrays of TSVs on a single substrate, with 100 via-holes each, in less than 20 seconds. We demonstrate that increasing the degree of parallelization by employing more assembly magnets below the substrate has no negative effect on the TSV filling speed or yield, thus enabling scaled-up TSV fabrication on full wafer-level. This method shows potential for industrial application with an estimated throughput of more than 70 wafers per hour in one single fabrication module. Such a TSV fabrication process could offer shorter processing times as well as higher obtainable aspect ratios compared to conventional TSV filling methods.

  • 8.
    Bleiker, Simon J.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Shah, Umer
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Somjit, Nutapong
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Haraldsson, Tommy
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Oberhammer, Joachim
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    High-Aspect-Ratio Through Silicon Vias for High-Frequency Application Fabricated by Magnetic Assembly of Gold-Coated Nickel Wires2015In: IEEE Transactions on Components, Packaging, and Manufacturing Technology, ISSN 2156-3950, E-ISSN 2156-3985, Vol. 5, no 1, p. 21-27Article in journal (Refereed)
    Abstract [en]

    In this paper, we demonstrate a novel manufacturing technology for high-aspect-ratio vertical interconnects for high-frequency applications. This novel approach is based on magnetic self-assembly of prefabricated nickel wires that are subsequently insulated with a thermosetting polymer. The high-frequency performance of the through silicon vias (TSVs) is enhanced by depositing a gold layer on the outer surface of the nickel wires and by reducing capacitive parasitics through a low-k polymer liner. As compared with conventional TSV designs, this novel concept offers a more compact design and a simpler, potentially more cost-effective manufacturing process. Moreover, this fabrication concept is very versatile and adaptable to many different applications, such as interposer, micro electromechanical systems, or millimeter wave applications. For evaluation purposes, coplanar waveguides with incorporated TSV interconnections were fabricated and characterized. The experimental results reveal a high bandwidth from dc to 86 GHz and an insertion loss of <0.53 dB per single TSV interconnection for frequencies up to 75 GHz.

  • 9.
    Ericsson, Per
    et al.
    Acreo AB.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Forsberg, Fredrik
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Samel, Björn
    Acreo AB.
    Savage, Susan
    Acreo AB.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Wissmar, Stanley
    Acreo AB.
    Öberg, Olof
    Acreo AB.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Toward 17µm pitch heterogeneously integrated Si/SiGe quantum well bolometer focal plane arrays2011In: Infrared Technology and Applications XXXVII: Proc. of SPIE, Vol. 8012, SPIE - International Society for Optical Engineering, 2011, p. 801216-1-801216-9Conference paper (Refereed)
    Abstract [en]

    Most of today's commercial solutions for un-cooled IR imaging sensors are based on resistive bolometers using either Vanadium oxide (VOx) or amorphous Silicon (a-Si) as the thermistor material. Despite the long history for both concepts, market penetration outside high-end applications is still limited. By allowing actors in adjacent fields, such as those from the MEMS industry, to enter the market, this situation could change. This requires, however, that technologies fitting their tools and processes are developed. Heterogeneous integration of Si/SiGe quantum well bolometers on standard CMOS read out circuits is one approach that could easily be adopted by the MEMS industry. Due to its mono crystalline nature, the Si/SiGe thermistor material has excellent noise properties that result in a state-ofthe- art signal-to-noise ratio. The material is also stable at temperatures well above 450°C which offers great flexibility for both sensor integration and novel vacuum packaging concepts. We have previously reported on heterogeneous integration of Si/SiGe quantum well bolometers with pitches of 40μm x 40μm and 25μm x 25μm. The technology scales well to smaller pixel pitches and in this paper, we will report on our work on developing heterogeneous integration for Si/SiGe QW bolometers with a pixel pitch of 17μm x 17μm.

  • 10.
    Fan, Xuge
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Fredrik, Forsberg
    Scania Technical Centre.
    Smith, Anderson David
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Schröder, Stephan
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. Senseair AB.
    Wagner, Stefan
    AMO GmbH.
    Rödjegård, Henrik
    Senseair AB.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. Silex Microsystems AB, Järfälla, Sweden.
    Östling, Mikael
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits.
    Lemme, Max C.
    KTH, School of Electrical Engineering and Computer Science (EECS), Electronics, Integrated devices and circuits. RWTH Aachen University ; AMO GmbH.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Graphene ribbons with suspended masses as transducers in ultra-small nanoelectromechanical accelerometers2019In: Nature Electronics, ISSN 2520-1131, Vol. 2, no 9, p. 394-404Article in journal (Refereed)
    Abstract [eo]

    Nanoelectromechanical system (NEMS) sensors and actuators could be of use in the development of next-generation mobile, wearable and implantable devices. However, these NEMS devices require transducers that are ultra-small, sensitive and can be fabricated at low cost. Here, we show that suspended double-layer graphene ribbons with attached silicon proof masses can be used as combined spring–mass and piezoresistive transducers. The transducers, which are created using processes that are compatible with large-scale semiconductor manufacturing technologies, can yield NEMS accelerometers that occupy at least two orders of magnitude smaller die area than conventional state-of-the-art silicon accelerometers. With our devices, we also extract the Young’s modulus values of double-layer graphene and show that the graphene ribbons have significant built-in stresses.

  • 11.
    Fischer, Andreas C.
    KTH, Superseded Departments (pre-2005), Chemistry.
    "Competitive coordination of the uranyl ion by perchlorate and water - The crystal structures of UO2(ClO4)(2)center dot 3H(2)O and UO2(ClO4)(2)center dot 5H(2)O and a redetermination of UO2(ClO4)(2)center dot 7H(2)O" (vol 629, pg 1012, 2003)2005In: Zeitschrift für Anorganische und Allgemeines Chemie, ISSN 0044-2313, E-ISSN 1521-3749, Vol. 631, no 10, p. 1966-1966Article in journal (Refereed)
  • 12.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Integration and Fabrication Techniques for 3D Micro- and Nanodevices2012Doctoral thesis, comprehensive summary (Other academic)
    Abstract [en]

    The development of micro and nano-electromechanical systems (MEMS and NEMS) with entirely new or improved functionalities is typically based on novel or improved designs, materials and fabrication methods. However, today’s micro- and nano-fabrication is restrained by manufacturing paradigms that have been established by the integrated circuit (IC) industry over the past few decades. The exclusive use of IC manufacturing technologies leads to limited material choices, limited design flexibility and consequently to sub-optimal MEMS and NEMS devices. The work presented in this thesis breaks new ground with a multitude of novel approaches for the integration of non-standard materials that enable the fabrication of 3D micro and nanoelectromechanical systems. The objective of this thesis is to highlight methods that make use of non-standard materials with superior characteristics or methods that use standard materials and fabrication techniques in a novel context. The overall goal is to propose suitable and cost-efficient fabrication and integration methods, which can easily be made available to the industry.

    The first part of the thesis deals with the integration of bulk wire materials. A novel approach for the integration of at least partly ferromagnetic bulk wire materials has been implemented for the fabrication of high aspect ratio through silicon vias. Standard wire bonding technology, a very mature back-end technology, has been adapted for yet another through silicon via fabrication method and applications including liquid and vacuum packaging as well as microactuators based on shape memory alloy wires. As this thesis reveals, wire bonding, as a versatile and highly efficient technology, can be utilized for applications far beyond traditional interconnections in electronics packaging.

    The second part presents two approaches for the 3D heterogeneous integration based on layer transfer. Highly efficient monocrystalline silicon/ germanium is integrated on wafer-level for the fabrication of uncooled thermal image sensors and monolayer-graphene is integrated on chip-level for the use in diaphragm-based pressure sensors.

    The last part introduces a novel additive fabrication method for layer-bylayer printing of 3D silicon micro- and nano-structures. This method combines existing technologies, including focused ion beam implantation and chemical vapor deposition of silicon, in order to establish a high-resolution fabrication process that is related to popular 3D printing techniques.

  • 13.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Belova, Lyubov M.
    KTH, School of Industrial Engineering and Management (ITM), Materials Science and Engineering, Engineering Material Physics.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Gylfason, Kristinn B.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    3D Free-Form Patterning of Silicon by Ion Implantation, Silicon Deposition, and Selective Silicon Etching2012In: Advanced Functional Materials, ISSN 1616-301X, E-ISSN 1616-3028, Vol. 22, no 19, p. 4004-4008Article in journal (Refereed)
    Abstract [en]

    A method for additive layer-by-layer fabrication of arbitrarily shaped 3D silicon micro- and nanostructures is reported. The fabrication is based on alternating steps of chemical vapor deposition of silicon and local implantation of gallium ions by focused ion beam (FIB) writing. In a final step, the defined 3D structures are formed by etching the silicon in potassium hydroxide (KOH), in which the local ion implantation provides the etching selectivity. The method is demonstrated by fabricating 3D structures made of two and three silicon layers, including suspended beams that are 40 nm thick, 500 nm wide, and 4 μm long, and patterned lines that are 33 nm wide.

  • 14.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Haraldsson, Tommy
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Very high aspect ratio through-silicon vias (TSVs) fabricated using automated magnetic assembly of nickel wires2012In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 22, no 10, p. 105001-Article in journal (Refereed)
    Abstract [en]

    Through-silicon via (TSV) technology enables 3D-integrated devices with higher performance and lower cost as compared to 2D-integrated systems. This is mainly due to smaller dimensions of the package and shorter internal signal lengths with lower capacitive, resistive and inductive parasitics. This paper presents a novel low-cost fabrication technique for metal-filled TSVs with very high aspect ratios (>20). Nickel wires are placed in via holes of a silicon wafer by an automated magnetic assembly process and are used as a conductive path of the TSV. This metal filling technique enables the reliable fabrication of through-wafer vias with very high aspect ratios and potentially eliminates characteristic cost drivers in the TSV production such as advanced metallization processes, wafer thinning and general issues associated with thin-wafer handling.

  • 15.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Somjit, Nutapong
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Haraldsson, Tommy
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    high aspect ratio tsvs fabricated by magnetic self-assembly of gold-coated nickel wires2012In: Electronic Components and Technology Conference (ECTC), 2012 IEEE 62nd, IEEE conference proceedings, 2012, p. 541-547Conference paper (Refereed)
    Abstract [en]

    Three-dimensional (3D) integration is an emerging technologythat vertically interconnects stacked dies of electronics and/orMEMS-based transducers using through silicon vias (TSVs).TSVs enable the realization of devices with shorter signal lengths,smaller packages and lower parasitic capacitances, which can resultin higher performance and lower costs of the system. Inthis paper we demonstrate a new manufacturing technology forhigh-aspect ratio (> 8) through silicon metal vias using magneticself-assembly of gold-coated nickel rods inside etched throughsilicon-via holes. The presented TSV fabrication technique enablesthrough-wafer vias with high aspect ratios and superior electricalcharacteristics. This technique eliminates common issues inTSV fabrication using conventional approaches, such as the metaldeposition and via insulation and hence it has the potential to reducesignificantly the production costs of high-aspect ratio stateof-the-art TSVs for e.g. interposer, MEMS and RF applications.

  • 16.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Forsberg, Fredrik
    KTH, School of Electrical Engineering (EES).
    Lapisa, Martin
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Integrating MEMS and ICs2015In: Microsystems & Nanoengineering, ISSN 2055-7434, Vol. 1, no 1, p. 1-16, article id 15005Article, book review (Refereed)
    Abstract [en]

    The majority of microelectromechanical system (MEMS) devices must be combined with integrated circuits (ICs) for operation in larger electronic systems. While MEMS transducers sense or control physical, optical or chemical quantities, ICs typically provide functionalities related to the signals of these transducers, such as analog-to-digital conversion, amplification, filtering and information processing as well as communication between the MEMS transducer and the outside world. Thus, the vast majority of commercial MEMS products, such as accelerometers, gyroscopes and micro-mirror arrays, are integrated and packaged together with ICs. There are a variety of possible methods of integrating and packaging MEMS and IC components, and the technology of choice strongly depends on the device, the field of application and the commercial requirements. In this review paper, traditional as well as innovative and emerging approaches to MEMS and IC integration are reviewed. These include approaches based on the hybrid integration of multiple chips (multi-chip solutions) as well as system-on-chip solutions based on wafer-level monolithic integration and heterogeneous integration techniques. These are important technological building blocks for the ‘More-Than-Moore’ paradigm described in the International Technology Roadmap for Semiconductors. In this paper, the various approaches are categorized in a coherent manner, their merits are discussed, and suitable application areas and implementations are critically investigated. The implications of the different MEMS and IC integration approaches for packaging, testing and final system costs are reviewed.

  • 17.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Forsberg, Fredrik
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Lapisa, Martin
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Zimmer, F.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Heterogeneous Integration for Optical MEMS2010In: 2010 23RD ANNUAL MEETING OF THE IEEE PHOTONICS SOCIETY, NEW YORK: IEEE , 2010, p. 487-488Conference paper (Refereed)
    Abstract [en]

    In this paper we present different large-scale heterogeneous integration technologies for optical MEMS that enable the integration of optical MEMS with standard CMOS-based ICs. Examples that are presented include various monocrystalline silicon micro-mirror arrays and infrared bolometer arrays.

  • 18.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Gradin, Henrik
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Braun, Stefan
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Schröder, Stephan
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Wafer-level integration of NiTi shape memory alloy wires for the fabrication of microactuators using standard wire bonding technology2011In: 24th International Conference on Micro Electro Mechanical Systems (MEMS), 2011 IEEE, IEEE , 2011, p. 348-351Conference paper (Refereed)
    Abstract [en]

    This paper reports on the first integration of SMA wires into silicon based MEMS structures using a standard wire bonder. This approach allows fast and efficient placement, alignment and mechanical attachment of NiTi-based SMA wires to silicon-based MEMS. The wires are mechanically anchored and clamped into deep-etched silicon structures on a wafer. The placement precision is high with an average deviation of 4 #x03BC;m and the mechanical clamping is strong, allowing successful actuation of the SMA wires.

  • 19.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Gradin, Henrik
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Schröder, Stephan
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Braun, Stefan
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    van der Wijngaart, Wouter
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Wire-bonder-assisted integration of non-bondable SMA wires into MEMS substrates2012In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 22, no 5, p. 055025-Article in journal (Refereed)
    Abstract [en]

    This paper reports on a novel technique for the integration of NiTi shape memory alloy wires and other non-bondable wire materials into silicon-based microelectromechanical system structures using a standard wire-bonding tool. The efficient placement and alignment functions of the wire-bonding tool are used to mechanically attach the wire to deep-etched silicon anchoring and clamping structures. This approach enables a reliable and accurate integration of wire materials that cannot be wire bonded by traditional means.

  • 20.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Grange, M.
    Department of Engineering, Centre for Microsystems Engineering, Lancaster University, Lancaster LA1 4YW, UK.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Weerasekera, R.
    Department of Engineering, Centre for Microsystems Engineering, Lancaster University, Lancaster LA1 4YW, UK.
    Pamunuwa, D.
    Department of Engineering, Centre for Microsystems Engineering, Lancaster University, Lancaster LA1 4YW, UK.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Wire-bonded through-silicon vias with low capacitive substrate coupling2011In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 21, no 8, p. 085035-Article in journal (Refereed)
    Abstract [en]

    Three-dimensional integration of electronics and/or MEMS-based transducers is an emerging technology that vertically interconnects stacked dies with through-silicon vias (TSVs). They enable the realization of circuits with shorter signal path lengths, smaller packages and lower parasitic capacitances, which results in higher performance and lower costs. This paper presents a novel technique for fabricating TSVs from bonded gold wires. The wires are embedded in a polymer, which acts both as an electrical insulator, resulting in low capacitive coupling toward the substrate and as a buffer for thermo-mechanical stress.

  • 21.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Gylfason, Kristinn B.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Belova, Liubov M.
    KTH, School of Industrial Engineering and Management (ITM), Materials Science and Engineering, Applied Material Physics.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, Mohammadreza
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rikers, Yuri G.M.
    FEI Electron Optics.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    3D Patterning of Si Micro and Nano Structures by Focused Ion Beam Implantation, Si Deposition and Selective Si Etching2012Conference paper (Other academic)
  • 22.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Gylfason, Kristinn B.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Belova, Lyubov M.
    Malm, Gunnar B.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Kolahdouz, M.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Rikers, Y. G. M.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Layer-by-layer 3D printing of Si micro- and nanostructures by Si deposition, ion implantation and selective Si etching2012In: 12th IEEE Conference on Nanotechnology (IEEE-NANO), 2012, IEEE conference proceedings, 2012, p. 1-4Conference paper (Refereed)
    Abstract [en]

    In this paper we report a method for layer-by-layer printing of three-dimensional (3D) silicon (Si) micro- and nanostructures. This fabrication method is based on a sequence of alternating steps of chemical vapor deposition of Si and local implantation of gallium (Ga+) ions by focused ion beam (FIB) writing. The defined 3D structures are formed in a final step by selectively wet etching the non-implanted Si in potassium hydroxide (KOH). We demonstrate the viability of the method by fabricating 2 and 3-layer 3D Si structures, including suspended beams and patterned lines with dimensions on the nm-scale.

  • 23.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Korvink, Jan G.
    University of Freiburg, Freiburg, Germany .
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Wallrabe, Ulrike
    University of Freiburg, Freiburg, Germany .
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Unconventional applications of wire bonding create opportunities for microsystem integration2013In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 23, no 8, p. 083001-Article, review/survey (Refereed)
    Abstract [en]

    Automatic wire bonding is a highly mature, cost-efficient and broadly available back-endprocess, intended to create electrical interconnections in semiconductor chip packaging. Modern production wire-bonding tools can bond wires with speeds of up to 30 bonds per second with placement accuracies of better than 2 mu m, and the ability to form each wire individually into a desired shape. These features render wire bonding a versatile tool also for integrating wires in applications other than electrical interconnections. Wire bonding has been adapted and used to implement a variety of innovative microstructures. This paper reviews unconventional uses and applications of wire bonding that have been reported in the literature. The used wire-bonding techniques and materials are discussed, and the implemented applications are presented. They include the realization and integration of coils, transformers, inductors, antennas, electrodes, through silicon vias, plugs, liquid and vacuum seals, plastic fibers, shape memory alloy actuators, energy harvesters and sensors.

  • 24.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Lapisa, Martin
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Antelius, Mikael
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Selective electroless nickel plating on oxygen-plasma-activated gold seed-layers for the fabrication of low contact resistance vias and microstructures:  2010In: Proceedings: Micronano System Technology Event MSW 2010, Stockholm: - , 2010, , p. 86p. 86-Conference paper (Refereed)
  • 25.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Lapisa, Martin
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Selective electroless nickel plating on oxygen-plasma-activated gold seed-layers for the fabrication of low contact resistance vias and microstructures2010In: MEMS 2010: (MEMS), 2010 IEEE 23rd International Conference on Micro Electro Mechanical Systems, IEEE , 2010, p. 472-475Conference paper (Refereed)
    Abstract [en]

    This paper presents a novel technique to selectively deposit nickel by electroless plating on gold seed layers using an oxygen-plasma-activation step. No prior wet surface pre- treatments or metal oxide etches are required. This enables the manufacturing of low-resistance vias for heterogeneous three-dimensional (3D) integration of MEMS but it is also a suitable technique for the fabrication of arbitrary shaped nickel-microstructures using chemically stable and cost-effective electroless nickel plating baths.

  • 26.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Mäntysalo, M.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Inkjet Printing, Laser-Based Micromachining and Micro 3D Printing Technologies for MEMS2015In: Handbook of Silicon Based MEMS Materials and Technologies: Second Edition, Elsevier Inc. , 2015, p. 550-564Chapter in book (Other academic)
    Abstract [en]

    A number of unconventional micro-fabrication technologies are emerging that are suitable for micromachining of MEMS devices. These micromachining approaches typically are sequential processes in which devices on a substrate are formed one at a time, as opposed to conventional parallel and high-throughput semiconductor manufacturing processes. Nevertheless, many of the serial micromachining processes, including inkjet printing technologies and laser-based processes can be highly efficient and cost competitive, especially for low and medium sized manufacturing volumes as well as for prototyping purposes. The technologies presented in this chapter can be categorized as additive micromachining approaches (e.g., inkjet printing) and subtractive micromachining approaches (e.g., laser ablation). This chapter discusses the more mature technologies that are already being developed in a commercial context and a number of new and emerging micromachining approaches that are still in the early research and development stage. 

  • 27.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Free form printing of silicon micro- and nanostructures2010Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    The invention relates to a method of making a three-dimensional structure in semiconductor material. A substrate (20) is provided having at least a surface comprising semiconductor material. Selected areas of the surface of the substrate are to a focused ion beam whereby the ions are implanted in the semiconductor material in said selected areas. Several layers of a material selected from the group consisting of mono-crystalline, poly-crystalline or amorphous semiconductor material, are deposited on the substrate surface and between depositions focused ion beam is used to expose the surface so as to define a three-dimensional structure. Material not part of the final structure (30) defined by the focused ion beam is etched away so as to provide a three-dimensional structure on said substrate (20).

  • 28.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Gylfason, Kristinn Björgvin
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    3D printing of silicon micro and nano structures by ion implantation, silicon deposition, and selective silicon etching2013In: Technical Paper - Society of Manufacturing Engineers, 2013Conference paper (Refereed)
    Abstract [en]

    A method for additive layer-by-layer fabrication of arbitrarily shaped 3D silicon micro and nano structures is reported. The fabrication is based on alternating steps of chemical vapor deposition of silicon and local implantation of gallium ions by focused ion beam (FIB) writing. In a final step, the defined 3D structures are formed by etching the silicon in potassium hydroxide (KOH), in which the local ion implantation provides the etching selectivity. The proposed technology could change and greatly simplify the fabrication of many MEMS, NEMS, and silicon photonic devices without requiring a fully equipped semiconductor cleanroom. This layer-by-layer fabrication method is in principle also viable for the implementation of 3D structures in semiconductors other than silicon.

  • 29.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    A method and an apparatus for forming electrically conductive vias in a substrate, an automated robot-based manufacturing system, a component comprising a substrate with via holes, and an interposer device2010Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A method for forming conductive vias in a substrate (302) by filling preformed via holes (303-305), preferably through via holes, with conductive material, comprises providing a plurality of preformed objects at least partly comprising ferromagnetic material (301) on a surface of the substrate; providing a magnetic source (307) on an opposite side of the substrate with respect to the plurality of preformed objects, thereby at least partly aligning at least a portion of the preformed objects with a magnetic field associated with the magnetic source; and moving the magnetic source relative the substrate, or vice versa, thereby moving the at least portion of the preformed objects into at least a portion of the via holes.

  • 30.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Haraldsson, Tommy
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Heinig, Nora
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Fabrication of high aspect ratio through silicon vias (TSVs) by magnetic assembly of nickel wires2011In: Micro Electro Mechanical Systems (MEMS), 2011 IEEE 24th International Conference on, IEEE , 2011, p. 37-40Conference paper (Refereed)
    Abstract [en]

    Three-dimensional (3D) integration of electronics and/or MEMS-based transducers is an emerging technology that vertically interconnects stacked dies using through silicon vias (TSVs). They enable the realization of devices with shorter signal lengths, smaller packages and lower parasitic capacitances, which can result in higher performance and lower costs of the system. This paper presents a novel low-cost fabrication technique for solid metal-filled TSVs using nickel wires as conductive path. The wires are placed in the via hole of a silicon wafer by magnetic self-assembly. This metal filling technique enables through-wafer vias with high aspect ratios and potentially eliminates characteristic cost drivers of the TSV production such as metallization processes, wafer thinning and general issues associated with thin-wafer handling.

  • 31.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Method for plugging a hole and a plugged hole2009Patent (Other (popular science, discussion, etc.))
    Abstract [en]

    A method for at least partially inserting a plug into a hole, said method comprising the steps of a) providing a at least one substrate with at least one hole wherein said at least one hole has a largest dimension of from 1 μm to 300 μm, b) providing a piece of material, wherein said piece of material has a larger dimension than said at least one hole, c) pressing said piece of material against the hole with a tool so that a plug is formed, wherein at least a part of said piece of material is pressed into said hole, d) removing the tool from the piece of material. There is further disclosed a plugged hole manufactured with the method. One advantage of an embodiment is that an industrially available wire bonding technology can be used to seal various cavities. The existing wire bonding technology makes the plugging fast and cheap.

  • 32.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Low-cost Through Silicon Vias (Tsvs) with wire-bonded metal cores and low capacitive substratecoupling:  2010In: Proceedings: 8th Micronano System Technology Event (MSW 2010), Stockholm: - , 2010, , p. 30p. 30-30Conference paper (Refereed)
  • 33.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Low-Cost Through Silicon Vias (Tsvs) With Wire-Bonded Metal Cores And Low Capacitive Substrate-Coupling2010In: MEMS 2010: 23RD IEEE INTERNATIONAL CONFERENCE ON MICRO ELECTRO MECHANICAL SYSTEMS, TECHNICAL DIGEST, IEEE , 2010, p. 480-483Conference paper (Refereed)
    Abstract [en]

    The three-dimensional (3D) integration of electronics and/or MEMS-based transducers is an emerging technology that vertically interconnects stacked dies using through silicon vias (TSVs). They enable the realization of devices with shorter signal lengths, smaller packages and lower parasitic capacitances, which can result in higher performance and lower costs. This paper presents a novel low-cost fabrication technique for metal-filled TSVs using bonded gold-wires as conductive path. In this concept the wires are surrounded by polymer, which acts both as an electrical insulator causing low capacitive coupling towards the substrate and as a buffer for thermo-mechanical stress.

  • 34.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    KTH Introduces New TSV-Concept with Wire-Bonded Metal Cores2009Other (Other (popular science, discussion, etc.))
  • 35.
    Fischer, Andreas C.
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Toral, T. R.
    Lindberg, K. B.
    Wille-Haussmann, B.
    Madani, Hatef
    KTH, School of Industrial Engineering and Management (ITM), Energy Technology, Applied Thermodynamics and Refrigeration.
    Investigation of Thermal Storage Operation Strategies with Heat Pumps in German Multi Family Houses2014In: Energy Procedia, Elsevier, 2014, p. 137-144Conference paper (Refereed)
    Abstract [en]

    The use of air source heat pumps is an efficient method to provide heat for space heating and domestic hot water in residential buildings, which cover roughly one third of the German domestic energy use. Capacity controlled heat pumps are gaining increased market share and provide high flexibility in operation. The possibility to use thermal storage to decouple thermal production and electric load from the heat pump can be used for operation strategies, hereby increasing the possibility to integrate electricity production from renewable energy sources. In the work presented, a range of operational strategies for capacity controlled heat pumps connected to a thermal storage in German multifamily houses are introduced and evaluated. The use cases include maximization of energy performance, cost minimization and utilization of on-site photovoltaic production. For optimal storage operation a model predictive control (MPC) approach using quadratic programming is presented together with simplified models of the multi-family house, a thermal storage and a capacity controlled air-to-water heat pump, the MPC creates a control signal to the heat pump. The resulting control signal is then applied to a detailed heat pump model to investigate the impact on the efficiency of the heat pump unit and thereby its electric energy consumption with different storage options.Results show that the MPC strategy is able to adapt to different objectives. One of the most important findings is that changing the objective towards a variable day-ahead-price-based operation leads to decreased heat pump efficiency but increases revenue. The sensitivity analysis towards storage size shows little influence in the range of sizes investigated.

  • 36.
    Forsberg, Fredrik
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Samel, Björn
    Acreo AB.
    Eriksson, Per
    Acreo AB.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Heterogeneous 3D integration of 17 mu m pitch Si/SiGe quantum well bolometer arrays for infrared imaging systems2013In: Journal of Micromechanics and Microengineering, ISSN 0960-1317, E-ISSN 1361-6439, Vol. 23, no 4, p. 045017-Article in journal (Refereed)
    Abstract [en]

    This paper reports on the realization of 17 mu m x 17 mu m pitch bolometer arrays for uncooled infrared imagers. Microbolometer arrays have been available in primarily defense applications since the mid-1980s and are typically based on deposited thin films on top of CMOS wafers that are surface-machined into sensor pixels. This paper instead focuses on the heterogeneous integration of monocrystalline Si/SiGe quantum-well-based thermistor material in a CMOS-compliant process using adhesive wafer bonding. The high-quality monocrystalline thermistor material opens up for potentially lower noise compared to commercially available uncooled microbolometer arrays together with a competitive temperature coefficient of resistance (TCR). Characterized bolometers had a TCR of -2.9% K-1 in vacuum, measured thermal conductances around 5 x 10(-8) WK-1 and thermal time constants between 4.9 and 8.5 ms, depending on the design. Complications in the fabrication of stress-free bolometer legs and low-noise contacts are discussed and analyzed.

  • 37.
    Forsberg, Fredrik
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology.
    Ericsson, Per
    Acreo AB.
    Samel, Björn
    Acreo AB.
    High-Performance Infrared Micro-Bolometer Arrays Manufactured Using Very Large Scale Heterogeneous Integration2011In: OMN2011: 16TH INTERNATIONAL CONFERENCE ON OPTICAL MEMS AND NANOPHOTONICS, 2011, p. 9-10Conference paper (Refereed)
    Abstract [en]

    This paper reports on the implementation and characterization of arrays of uncooled infrared bolometers containing mono-crystalline Si/SiGe quantum well (QW) thermistors. The bolometer arrays are integrated on silicon fan-out wafers using very-large scale heterogeneous integration that is compatible with standard CMOS wafers. Infrared bolometer arrays with 320x240 pixels and pixel pitches of 25 mu m x 25 mu m and 17 mu m x 17 mu m have been implemented, respectively.

  • 38.
    Forsberg, Fredrik
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Samel, Björn
    Acreo AB.
    Ericsson, Per
    Acreo AB.
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Very Large Scale Heterogeneous Integration (VLSHI) and Wafer-Level Vacuum Packaging for Infrared Bolometer Focal Plane Arrays2013In: Infrared physics & technology, ISSN 1350-4495, E-ISSN 1879-0275, Vol. 60, p. 251-259Article in journal (Refereed)
    Abstract [en]

    Imaging in the long wavelength infrared (LWIR) range from 8 to 14 μm is an extremely useful tool for non-contact measurement and imaging of temperature in many industrial, automotive and security applications. However, the cost of the infrared (IR) imaging components has to be significantly reduced to make IR imaging a viable technology for many cost-sensitive applications. This paper demonstrates new and improved fabrication and packaging technologies for next-generation IR imaging detectors based on uncooled IR bolometer focal plane arrays. The proposed technologies include very large scale heterogeneous integration for combining high-performance, SiGe quantum-well bolometers with electronic integrated read-out circuits and CMOS compatible wafer-level vacuum packing. The fabrication and characterization of bolometers with a pitch of 25 μm × 25 μm that are arranged on read-out-wafers in arrays with 320 × 240 pixels are presented. The bolometers contain a multi-layer quantum well SiGe thermistor with a temperature coefficient of resistance of −3.0%/K. The proposed CMOS compatible wafer-level vacuum packaging technology uses Cu–Sn solid–liquid interdiffusion (SLID) bonding. The presented technologies are suitable for implementation in cost-efficient fabless business models with the potential to bring about the cost reduction needed to enable low-cost IR imaging products for industrial, security and automotive applications.

  • 39.
    Gao, Jiajia
    et al.
    KTH, School of Chemical Science and Engineering (CHE), Chemistry, Applied Physical Chemistry.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Svensson, Per H.
    KTH, School of Chemical Science and Engineering (CHE), Chemistry, Organic Chemistry.
    Kloo, Lars
    KTH, School of Chemical Science and Engineering (CHE), Chemistry, Applied Physical Chemistry.
    Crystallography as Forensic Tool for Understanding Electrolyte Degradation in Dye-sensitized Solar Cells2017In: CHEMISTRYSELECT, ISSN 2365-6549, Vol. 2, no 4, p. 1675-1680Article in journal (Refereed)
    Abstract [en]

    The precipitation of solid compounds from model electrolytes for liquid dye-sensitized solar cells has a story to tell regarding decomposition processes to be expected in such systems. Of course, the crystal lattice energy for a specific crystalline compounds plays a role in what compound that will eventually precipitate, but the compounds nevertheless serve as indicators for what type of processes that take place in the solar cell electrolytes upon ageing. From the compounds isolated in this study we learn that both ligand exchange processes, double-salt precipitation and oxidation are degradation processes that should not be overlooked when formulating efficient and stable electrolytes for this type of electrochemical system.

  • 40.
    Gylfason, Kristinn B.
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Gunnar Malm, B. Gunnar
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Radamson, Henry H.
    KTH, School of Information and Communication Technology (ICT), Integrated Devices and Circuits.
    Belova, Lyubov M.
    KTH, School of Industrial Engineering and Management (ITM), Materials Science and Engineering, Engineering Material Physics.
    Niklaus, Frank
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Process considerations for layer-by-layer 3D patterning of silicon, using ion implantation, silicon deposition, and selective silicon etching2012In: Journal of Vacuum Science & Technology B, ISSN 1071-1023, E-ISSN 1520-8567, Vol. 30, no 6, p. 06FF05-Article in journal (Refereed)
    Abstract [en]

    The authors study suitable process parameters, and the resulting pattern formation, in additive layer-by-layer fabrication of arbitrarily shaped three-dimensional (3D) silicon (Si) micro- and nanostructures. The layer-by-layer fabrication process investigated is based on alternating steps of chemical vapor deposition of Si and local implantation of gallium ions by focused ion beam writing. In a final step, the defined 3D structures are formed by etching the Si in potassium hydroxide, where the ion implantation provides the etching selectivity.

  • 41.
    Iovan, Adrian
    et al.
    KTH.
    Fischer, Marco
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Lo Conte, Roberto
    KTH.
    Korenivski, Vladislav
    KTH, School of Engineering Sciences (SCI), Applied Physics, Nanostructure Physics.
    Sub-10 nm colloidal lithography for circuit-integrated spin-photo-electronic devices2012In: Beilstein Journal of Nanotechnology, ISSN 2190-4286, Vol. 3, p. 884-892Article in journal (Refereed)
    Abstract [en]

    Patterning of materials at sub-10 nm dimensions is at the forefront of nanotechnology and employs techniques of various complexity, efficiency, areal scale, and cost. Colloid-based patterning is known to be capable of producing individual sub-10 nm objects. However, ordered, large-area nano-arrays, fully integrated into photonic or electronic devices have remained a challenging task. In this work, we extend the practice of colloidal lithography to producing large-area sub-10 nm point-contact arrays and demonstrate their circuit integration into spin-photo-electronic devices. The reported nanofabrication method should have broad application areas in nanotechnology as it allows ballistic-injection devices, even for metallic materials with relatively short characteristic relaxation lengths.

  • 42.
    Laakso, Miku
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Bleiker, Simon J.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Liljeholm, Jessica
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. Silex Microsystems AB.
    Mårtensson, Gustaf
    Mycronic AB.
    Asiatici, Mikhail
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. EPFL École polytechnique fédérale de Lausanne, Processor Architecture Laboratory.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. Silex Microsystems AB.
    Stemme, Göran
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Ebefors, Thorbjörn
    Silex Microsystems AB.
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Through-Glass Vias for MEMS Packaging2018Conference paper (Other academic)
    Abstract [en]

    Novelty / Progress Claims We have developed a new method for fabrication of through-glass vias (TGVs). The method allows rapid filling of via holes with metal rods both in thin and thick glass substrates.

    Background Vertical electrical feedthroughs in glass substrates, i.e. TGVs, are often required in wafer-scale packaging of MEMS that utilizes glass lids. The current methods of making TGVs have drawbacks that prevent the full utilization of the excellent properties of glass as a package material, e.g. low RF losses. Magnetic assembly has been used earlier to fabricate through-silicon vias (TSVs), and in this work we extend this method to realize TGVs [1].

    Methods The entire TGV fabrication process is maskless, and the processes used include: direct patterning of wafer metallization using femtosecond laser ablation, magnetic-fieldassisted self-assembly of metal wires into via holes, and solder-paste jetting of bump bonds on TGVs.

    Results We demonstrate that: (1) the magnetically assembled TGVs have a low resistance, which makes them suitable even for low-loss and high-current applications; (2) the magneticassembly process can be parallelized in order to increase the wafer-scale fabrication speed; (3) the magnetic assembly produces void-free metal filling for TGVs, which allows solder placement directly on top of the TGV for the purpose of high integration density; and (4) good thermal-expansion compatibility between TGV metals and glass substrates is possible with the right choice of materials, and several suitable metals-glass pairs are identified for possible improvement of package reliability [2].

    [1] M. Laakso et al., IEEE 30th Int. Conf. on MEMS, 2017. DOI:10.1109/MEMSYS.2017.7863517

    [2] M. Laakso et al., “Through-Glass Vias for Glass Interposers and MEMS Packaging Utilizing Magnetic Assembly of Microscale Metal Wires,” manuscript in preparatio

  • 43.
    Laakso, Miku J.
    et al.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Bleiker, Simon J.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Liljeholm, Jessica
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Mårtensson, Gustaf E.
    Mycronic AB, S-18353 Taby, Sweden..
    Asiatici, Mikhail
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems. Ecole Polytech Fed Lausanne, Sch Comp & Commun Sci, CH-1015 Lausanne, Switzerland..
    Fischer, Andreas C.
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Stemme, Göran
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Ebefors, Thorbjorn
    Silex Microsyst AB, S-17543 Jarfalla, Sweden.;MyVox AB, S-12938 Hagersten, Sweden..
    Niklaus, Frank
    KTH, School of Electrical Engineering and Computer Science (EECS), Micro and Nanosystems.
    Through-Glass Vias for Glass Interposers and MEMS Packaging Applications Fabricated Using Magnetic Assembly of Microscale Metal Wires2018In: IEEE Access, E-ISSN 2169-3536, Vol. 6, p. 44306-44317Article in journal (Refereed)
    Abstract [en]

    A through-glass via (TGV) provides a vertical electrical connection through a glass substrate. TGVs are used in advanced packaging solutions, such as glass interposers and wafer-level packaging of microelectromechanical systems (MEMS). However, TGVs are challenging to realize because via holes in glass typically do not have a sufficiently high-quality sidewall profile for super-conformal electroplating of metal into the via holes. To overcome this problem, we demonstrate here that the via holes can instead be filled by magnetically assembling metal wires into them. This method was used to produce TGVs with a typical resistance of 64 m Omega, which is comparable with other metal TGV types reported in the literature. In contrast to many TGV designs with a hollow center, the proposed TGVs can be more area efficient by allowing solder bump placement directly on top of the TGVs, which was demonstrated here using solder-paste jetting. The magnetic assembly process can be parallelized using an assembly robot, which was found to provide an opportunity for increased wafer-scale assembly speed. The aforementioned qualities of the magnetically assembled TGVs allow the realization of glass interposers and MEMS packages in different thicknesses without the drawbacks associated with the current TGV fabrication methods.

  • 44.
    Niklaus, Frank
    et al.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Fischer, Andreas C.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Heterogeneous 3D integration of MOEMS and ICs2016In: International Conference on Optical MEMS and Nanophotonics, IEEE Computer Society, 2016Conference paper (Refereed)
    Abstract [en]

    Heterogeneous integration of micro-opto-electromechanical systems (MOEMS) and integrated circuits (ICs) allows the combination of high-quality optical and photonic MOEMS materials such as monocrystalline silicon (Si) with standard CMOS-based electronic circuits in order to realize complex optical systems. In this paper, we will present examples of such heterogeneous optical systems, including CMOS-integrated SiGe bolometer arrays and CMOS-integrated Si micro-mirror arrays.

  • 45.
    Niklaus, Frank
    et al.
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Lapisa, Martin
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Bleiker, Simon J.
    KTH, School of Electrical Engineering (EES), Micro and Nanosystems.
    Dubois, Valentin
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Roxhed, Niclas
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Fischer, Andreas
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Forsberg, Fredrik
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Stemme, Göran
    KTH, School of Electrical Engineering (EES), Microsystem Technology (Changed name 20121201).
    Grogg, Daniel
    Despont, Michel
    Wafer-level heterogeneous 3D integration for MEMS and NEMS2012In: Proceedings of 2012 3rd IEEE International Workshop on Low Temperature Bonding for 3D Integration, LTB-3D 2012, IEEE conference proceedings, 2012, p. 247-252Conference paper (Refereed)