Neuromorphic computing is a relatively new discipline of computer science, where the principles of biological brain’s computation and memory are used to create a new way of processing information, based on networks of spiking neurons. Those networks can be implemented as both analog and digital implementations, where for the latter, the Field Programmable Gate Arrays (FPGAs) are a frequent choice, due to their inherent flexibility, allowing the researchers to easily design hardware neuromorphic architecture (NMAs). Moreover, digital NMAs show good promise in simulating various spiking neural networks because of their inherent accuracy and resilience to noise, as opposed to analog implementations. This paper presents an overview of digital NMAs implemented on FPGAs, with a goal of providing useful references to various architectural design choices to the researchers interested in digital neuromorphic systems. We present a taxonomy of NMAs that highlights groups of distinct architectural features, their advantages and disadvantages and identify trends and predictions for the future of those architectures. 

Recent advances in solar physics increasingly rely on automated identification of coronal structures using machine learning. Yet most studies emphasize scientific performance without evaluating feasibility for onboard deployment to prioritize downlink observations. This work investigates the automated identification of active regions and coronal holes by applying segmentation and detection techniques to Solar Dynamics Observatory (SDO) data. We compare three approaches: SCSS-Net, a deep learning model for semantic segmentation; YOLOv8n, a lightweight object detector; and a traditional pipeline based on basic computer vision operations (BCVO). Each method is assessed for its scientific accuracy and its suitability for deployment in future resource-limited missions. While no direct hardware benchmarking is performed in this study, we assess the feasibility of onboard implementation based on the associated number of trainable parameters, architecture and hardware requirements. Training and evaluation are first conducted on well-calibrated SDO images. We then extend the evaluation to raw and uncalibrated SDO images affected by instrumental artifacts. Performance is measured using the Intersection over Union (IoU) and Dice score. Results show that while SCSS-Net achieves the highest segmentation quality, YOLOv8n offers a strong balance between accuracy and efficiency. The BCVO pipeline remains viable under strict hardware limitations. Interestingly, our models retain compatibility on Level-0 observations. This is the first study comparing these widely used methods from the perspective of onboard deployment. Our findings provide a foundation for designing frameworks tailored to onboard hardware configurations.

Output-intensive scientific applications are highly sensitive to low storage throughput. While existing scientific application stacks are optimized for traditional High-Performance Computing (HPC) environments with high remote storage and network bandwidth, these assumptions often fail in modern settings like cloud deployment. This is because the existing scientific application I/O stack fails to leverage the available resources. At the same time, scientific applications exhibit special synchronization and data output requirements that are difficult to satisfy using traditional approaches such as block-level or filesystem-level caching. We introduce ParaLog, a distributed host-side logging approach designed to accelerate scientific applications transparently. ParaLog emphasizes deployability, enabling support for unmodified message passing interface (MPI) applications and implementations while preserving crash consistency semantics. We evaluate ParaLog across traditional HPC, cloud HPC, local clusters, and hybrid environments, demonstrating its capability to reduce end-to-end execution time by 13-26% for popular scientific applications in cloud settings.

Brain-like algorithms are attractive and emerging alternatives to classical deep learning methods for use in various machine learning applications. Brain-like systems can feature local learning rules, both unsupervised/semi-supervised learning and different types of plasticity (structural/synaptic), allowing them to potentially be faster and more energy-efficient than traditional machine learning alternatives. Among the more salient brain-like algorithms are Bayesian Confidence Propagation Neural Networks (BCPNNs). BCPNN is an important tool for both machine learning and computational neuroscience research, and recent work shows that BCPNN can reach state-of-the-art performance in tasks such as learning and memory recall compared to other models. Unfortunately, BCPNN is primarily executed on slow general-purpose processors (CPUs) or power-hungry graphics processing units (GPUs), reducing the applicability of using BCPNN in Edge systems, among others. In this work, we design a reconfigurable stream-based accelerator for BCPNN using Field-Programmable Gate Arrays (FPGA) using Xilinx Vitis High-Level Synthesis (HLS) flow. Furthermore, we model our accelerator’s performance using first principles, and we empirically show that our proposed accelerator (full-featured kernel non-structural plasticity) is between 1.3x - 5.3x faster than an Nvidia A100 GPU while at the same time consuming between 2.62x - 3.19x less power and 5.8x - 16.5x less energy without any degradation in performance.

Edge AI increasingly requires models that learn and adapt on-device under a tight energy budget. Mainstream deep learning models, while powerful, are often overparameterized, energy-hungry and dependent on cloud connectivity. Brain-Like Neural Networks (BLNNs), such as the Bayesian Confidence Propagation Neural Network (BCPNN), propose a neuromorphic alternative by mimicking cortical architecture and biologicallyconstrained learning. They offer sparse architectures with local learning rules and unsupervised/semi-supervised learning, making them well-suited for low-power edge intelligence. However, existing BCPNN implementations rely on GPUs or datacenter FPGAs. This work presents the first embedded FPGA accelerator for BCPNN on a Zynq UltraScale+ SoC (ZCU104) using High-Level Synthesis. We implement both online learning and inference-only kernels with configurable precision (FP32, FP16, and mixed FP16/FXP16). Evaluated on MNIST, Pneumonia, and Breast Cancer datasets, our accelerator delivers up to 17.55% lower latency and 94.1% energy savings over ARM baselines. Our work brings practical, brain-like online learning and scalable inference to edge devices.

Space missions increasingly deploy high-fidelity sensors that produce data volumes exceeding onboard buffering and downlink capacity. This work evaluates FPGA acceleration of neural networks (NNs) across four space use cases on the AMD ZCU104 board. We use Vitis AI (AMD DPU) and Vitis HLS to implement inference, quantify throughput and energy, and expose toolchain and architectural constraints relevant to deployment. Vitis AI achieves up to 34.16 × higher inference rate than the embedded ARM CPU baseline, while custom HLS designs reach up to 5.4 × speedup and add support for operators (e.g., sigmoids, 3D layers) absent in the DPU. For these implementations, measured MPSoC inference power spans 1.56.75 W, reducing energy per inference versus CPU execution in all use cases. These results show that NN FPGA acceleration can enable onboard filtering, compression, and event detection, easing downlink pressure in future missions. 

Spiking Neural Networks (SNNs) are a promising alternative to conventional Artificial Neural Networks (ANNs) due to their biological interpretability and capability to exploit sparse computation. Specialized hardware for SNNs has potential advantages over general-purpose devices in terms of power and performance. However, the computational requirements of modern Spiking Convolutional Neural Networks (SCNNs) renders most SNN hardware inefficient for SCNN acceleration. As a step towards efficient SCNN acceleration, we present IncineRate, a flexible FPGA-based SCNN accelerator architecture. IncineRate has built-in support for many SCNNs, such as AlexNet, VGG16, and ResNets, and can be extended to support other network models. The number of simulation time steps, the network architecture, and other settings are specified at run time, so an already deployed device can execute multiple networks without reconfiguration. Our results show that IncineRate achieves state-of-the-art classification accuracy among FPGA-based SCNNs on CIFAR10 and CIFAR100.

Spiking Neural Network processing promises to provide high energy efficiency due to the sparsity of the spiking events. However, when realized on general-purpose hardware – such as a RISC-V processor – this promise can be undermined and overshadowed by the inefficient code, stemming from repeated usage of basic instructions for updating all the neurons in the network. One of the possible solutions to this issue is the introduction of a custom ISA extension with neuromorphic instructions for spiking neuron updating, and realizing those instructions in bespoke hardware expansion to the existing ALU. In this paper, we present the first step towards realizing a large-scale system based on the RISC-V-compliant processor called IzhiRISC-V, supporting the custom neuromorphic ISA extension.

Spiking Neural Networks (SNNs) are models that mimic and replicate the computational properties of the biological brain. Computation is performed using neurons that transmit information on axons between each other via synapses. SNNs have several important application areas, ranging from (brain-like) artificial intelligence to complex brain simulations. Most SNN simulations today are carried out on systems such as CPUs and GPUs, which fit SNNs poorly and often yield slow solutions that consume needlessly much energy. In this work, we present algorithms for efficient simulation of SNNs on Field-Programmable Gate Arrays (FPGAs), which is driven by our hypothesis that said devices can be much more power-efficient without sacrificing execution performance. We also provide an in-depth analysis and discussion of our algorithms and techniques. We target the important Potjans-Diesmann model, a well-known cortical microcircuit often used for assessing SNN simulation performance. Using high-level synthesis (HLS) targeting the latest Intel Agilex 7 FPGA, we show that our best simulator can execute the microcircuit 25% faster than real-time and require only 21 nJ per synaptic event. Our result surpasses the state-of-the-art for single-device simulation, and the energy use is the lowest among published results.