A power flow controller (PFC) may be needed to control the currents and power transmitted in the transmission lines in a highly meshed HVDC system. The paper presents a new and simple topology for series interline PFC for a simple 3 terminal HVDC system. Interline PFCs do not need an external power supply to change the current distribution in the HVDC system. The performance of the proposed PFC during steady state operation and ground faults is analyzed in detail using PLECS software. A protection circuit and its design aspects are also proposed for ground faults on one of the cables.

Power flow controllers (PFCs) might be needed in highly meshed High-voltage direct current (HVDC) systems to redistribute the current and power in the various cables. This paper introduces two new unidirectional topologies, which are among the most simple PFC topologies. It describes the working principle, electrical characteristics, various fault cases, and the corresponding protection circuits in detail. Experiments have been conducted on a scaled-down prototype to verify the full-scale HVDC system simulations. Discussion and extension of the PFC with more than two transmission lines are provided.

Power flow controllers (PFCs) can give added benefits in meshed High-Voltage Direct Current (HVDC) grids to increase renewables integration. Interline PFCs have been gaining attention for the last decade due to their easy structure and no need for an external power supply. This paper discusses various interline PFC topologies along with their advantages and disadvantages. The existing topologies are compared with respect to several aspects. These aspects include, for instance, modularity, the number of capacitors, the control range of the PFC, the shape of voltage waveforms inserted by the PFC on the lines, number of devices, the directionality of the current, simplicity of the topology, total power semiconductor rating and losses, and protection of the topologies for external faults. It is concluded that the topology of a PFC for a particular application can be chosen depending on the main goal since the topologies come with their advantages and disadvantages when classified based on various aspects.

With the increase in renewables integration in power systems, the demand for over current (OC) capability is increased. Until the fault clearance, converters in the power system must be able to withstand the increased currents without getting tripped by their internal protection based on thermal limits. This duration is typically 200 ms. In this thesis, various techniques have been proposed to remove the heat generated during OCs as soon as possible fromSilicon-Carbide (SiC) devices, hence increasing the OC duration. These techniques include implementing heat-absorbing materials, microchannel (MC) cooling on the top and bottom of the chip, and gate voltage augmentation during OCs. It is concluded that any cooling method (except gate voltage augmentation) gives the highest OC capability when it is implemented on top of the chip. MC cooling has the potential to increase OC capability duration until a few seconds, depending on the design of the MC block. Similarly, OC capability is significantly improved by using copper as heat-absorbing material on top and bottom (with a comparatively large block of copper) of the chip up to a few seconds, depending on the amount of OC. Even increasing the thickness of metallization on top of the chip can lead to increased OC capability. One application of the power modules with increased OC capability is in power flow controllers (PFCs). With the increase in meshing, controllability and flexibility to control the current and power in a high-voltage direct current (HVDC) system are reduced. By injecting a small amount of voltage, a PFC can change the current distribution. Existing topologies have been studied in detail by PLECS simulations and compared with respect to the number of capacitors, the control range of the PFC, the shape of voltage waveforms inserted by the PFC on the lines, number of devices, the directionality of the current, simplicity of the topology, total power semiconductor rating and losses, and protection of the topologies for external faults. A new topology, which is among the most simple topologies, has been proposed. Further, internal and external fault cases for the proposed topology have been investigated in detail. The simulations are verified by a scaled-down prototype in the lab. Simulations and experiments have been compared with respect to their per unit (pu) system and the experimental results are aligned with the simulation results.

Med den ökande integrationen av förnybar energi i elsystemet ökar behovet på överströmstålighet. Fram till att ett fel i nätet har avhjälpts måste effektomvandlare i elsystemet kunna tåla överströmmar utan att bortkopplas av sina interna skydd. Denna tid är vanligtvis 200 ms. I denna avhandling föreslås olika tekniker att snabbt leda bort den av överströmmar generade värmen från kiselkarbid (SiC)-enheter. Detta förlänger den tid enheten kan hantera överström. Nämnda tekniker inkluderar användning av värmeabsorberande material, mikrokanalkylning (MC) på chipets ovansida och undersida samt intermittent höjning av gate-spänningen. Slutsatsen är att vilken kylmetod som helst (förutom gate-spänningshöjning) ger högst överströmstålighet när den implementeras på chipets ovansida. Mikrokanalkylning har potential att höja tillåten överströmsvaraktighet till några sekunder, beroende på konstruktionen av MC-blocket. På samma sätt förbättras överströmståligheten avsevärt genom att använda koppar som värmeabsorberande material på chipets ovansida och undersida (med ett stort kopparblock), upp till några sekunder, beroende på överströmmens storlek. Även en ökning av metalliseringens tjocklek på chipets ovansida kan leda till en förbättrad överströmstålighet. Implementering av kylning på ovansidan kan dock kräva särskilda modifieringar av kraftmodulen.

En tillämpning för kraftmoduler med förbättrad överströmstålighet är effektflödesstyrdon (PFC) i högspända likströmsnät (HVDC-nät). Med en ökande maskning i nätet minskar styrbarheten och flexibiliteten att styra ström och effekt i ett HVDC-system. Genom att injicera än förhållandevis låg spänning kan ett effektflödesstyrdon förändra strömfördelningen i ett maskar HVDC-nät. Existerande topologier har studerats i detalj med hjälp av PLECS-simuleringar och jämförts med avseende på antal kondensatorer, styrningsbegränsningar, kurvformer för de spänningar som injiceras av effektflödesstyrdonet i ledningarna, antal komponenter, strömriktning, topologins enkelhet, total effekthalvledar-märkeffekt och förluster samt skydd av topologierna mot externa fel. En ny kretstopologi har föreslagits. Dessutom har interna och externa felfall för den föreslagna topologin och dess skyddskretsar undersökts i detalj med hjälp av PLECS-simuleringar. Simuleringarna har verifierats med en nedskalad prototyp i laboratoriet. Simuleringar och experiment har jämförts genom användning av ett per-unit-system, och de experimentella resultaten överensstämmer med simuleringsresultaten.

The typical fault clearance time in an AC grid is approximately 200 ms. Grid-connected power converters should be able to deliver increased currents during this time. This paper investigates the over-current (OC) capability using microchannel (MC) cooling below the chip using COMSOL simulations with SiC MOSFETs. The paper also compares thermal performance of MCs above and below the chip. The maximum allowable chip temperature is assumed to be 250 °C since SiC devices do not fail up to this temperature if the package is adapted for such operation. OC durations is from a few milliseconds to a few seconds. It is concluded that MC cooling below the chip can potentially increase the OC capability. However, the OC capability is significantly superior when MC cooling is applied on top of chip.

The fault clearance time in the power system can vary from a few milliseconds to a few hundred milliseconds. Power electronics converters should be able to provide the increased current during faults without failing due to thermal limits. Hence, the heat generated in the semiconductor chip due to the over-current (OC) should be removed as soon as it is generated. In this paper, cooling by heat-absorbing material has been investigated on the top, bottom, and top + bottom of the SiC MOSFET chip using COMSOL simulations for OCs. The heat-absorbing materials considered in the paper are copper, graphite, and aluminum. The maximum allowed chip temperature is assumed to be 250 ˆC since SiC devices do not fail in this range of temperature. It is concluded that the cooling on the top of the chip has the best performance among the three arrangements discussed in the paper in terms of OC duration and steady-state temperature. Another conclusion is that copper has the best performance due to higher thermal capacity for the same volume of the heat-absorbing material.

An increasing share of fluctuating and intermittent renewable energy sources can cause over-currents (OCs) in the power system. The heat generated during OCs increases the junction temperature of semiconductor devices and could even lead to thermal runaway if thermal limits are reached. In order to keep the junction temperature within the thermal limit of the semiconductor, the power module structure with heat-absorbing material below the chip is investigated through COMSOL Multiphysics simulations. The upper limits of the junction temperature for Silicon (Si) and Silicon Carbide (SiC) are assumed to be 175 and 250 ∘∘C, respectively. The heat-absorbing materials considered for analysis are a copper block and a copper block with phase change materials (PCMs). Two times, three times, and four times of OCs would be discussed for durations of a few hundred milliseconds and seconds. This article also discusses the thermal performance of a copper block and a copper block with PCMs. PCMs used for Si and SiC are LM108 and Lithium, respectively. It is concluded that the copper block just below the semiconductor chip would enable OC capability in Si and SiC devices and would be more convenient to manufacture as compared to the copper block with PCM.

With the increase in high-voltage direct current (HVDC) systems, the need for power flow controllers (PFCs) has been identified recently to avoid overloads in the cables. An interline PFC has gained attention because of no need for an external power source. The paper presents an analysis to decide the best location in terms of the maximum current variation. A particular case study of a 3-terminal HVDC system has been presented with PFCs at different nodes. The analysis uses a PFC which has been tested experimentally in previous work. Simulations are performed using the PLECS software to extend the studies further for wider applications and make a well-informed choice about the location of PFCs. It is concluded that the maximum current variation is possible when the PFC is applied at the slack node (the node with fixed voltage)

An increasing share of fluctuating and intermittent renewable energy sources can cause over-currents (OCs) in the power system. The heat generated during OCs increases the junction temperature of semiconductor devices and could even lead to thermal runaway if thermal limits are reached. In order to keep the junction temperature within the thermal limit of the semiconductor, the power module structure with heat-absorbing material below the chip is investigated through COMSOL Multiphysics simulations. The upper limits of the junction temperature for Silicon (Si) and Silicon Carbide (SiC) are assumed to be 175 and 250 ∘∘C, respectively. The heat-absorbing materials considered for analysis are a copper block and a copper block with phase change materials (PCMs). Two times, three times, and four times of OCs would be discussed for durations of a few hundred milliseconds and seconds. This article also discusses the thermal performance of a copper block and a copper block with PCMs. PCMs used for Si and SiC are LM108 and Lithium, respectively. It is concluded that the copper block just below the semiconductor chip would enable OC capability in Si and SiC devices and would be more convenient to manufacture as compared to the copper block with PCM.