This study analyzes the sequential failure and remaining useful life (RUL) of a multi-chip power module (MCPM) using finite element (FE) simulation, an empirical lifetime model, and recursive deconvolution. The FE model captures electro-thermal interactions, while the empirical model estimates failure probabilities from power cycling test data. The deconvolution method refines the probability density function of the first failure, providing deeper insights into degradation trends. Results show that the first die in an MCPM can fail significantly earlier than the last, with temperature imbalances contributing to this variation. Despite early failures, the system can continue operating with minor thermal impacts. These findings highlight the need for adaptive failure management and improved thermal design to enhance reliability and system life time.

Double-sided cooled (DSC) power semiconductor modules have garnered increased interest over the past decade due to their ability to offer an additional path for heat removal, facilitating higher power density operation while reducing junction temperatures and thermal stresses. Nevertheless, when operating at similar junction temperatures, DSC modules might exhibit elevated thermo-mechanical stress compared to single-sided cooled (SSC) modules. This increase can be attributed to restricted vertical movement within the DSC modules. Furthermore, the integration of various spacers within the DSC modules, which enable bond wire connections to gate terminals, can significantly influence both the thermal performance and induced thermo-mechanical stresses. Depending on the materials used in the spacer, the thermal performance and thermo-mechanical stresses inside the module can vary. In this study, we have first analysed the thermal performance of the DSC power modules employing different spacers. Following that, we have also performed thermo-mechanical analysis in different solder layers. Finally, fatigue analysis is done to demonstrate the weakest solder layer inside the package.

Accurate estimation of losses in high-power traction converters is essential for an effective design. Precise estimation of switching and conduction losses is crucial for this purpose. In this paper, the widely recognized Double Pulse Test (DPT) is employed to determine these losses. However, time-shift errors and misalignments in measurements can lead to significant deviations in loss estimation of the actual setup. This paper introduces a postprocessing method aimed at mitigating time-shift and misalignment issues in voltage and current waveforms. The proposed method is validated through simulation, demonstrating its effectiveness in improving the accuracy of loss estimation for high-power traction converters.

The semiconductor industry plays a critical role in numerous sectors, yet faces vulnerability in its supply chains. The recent global semiconductor shortage highlighted the risks of relying on a single supplier. To mitigate this, companies adopt dualsourcing strategies, but power devices like silicon carbide (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs) pose challenges due to manufacturing nuances. Configurable gate-drive units (GDUs) offer flexibility but often require external input for device recognition. This paper introduces a method to achieve a self-configurable gate-drive unit based on measuring the gate step-response for power device identification. The proposed method enhances safety, ensures seamless integration, and offers adaptability in full-bridge or multi-phase systems. Experimental results demonstrate component uniformity, emphasize the importance of interval selection, and showcase the impact of external gate resistors on rise and fall times. Estimations of input capacitance using different methods highlight their effectiveness in distinguishing among devices. The practical implementation of the proposed method contributes to the efficiency, reliability, and cost-effectiveness of self-configurable GDUs.

Silicon carbide (SiC)-based metal-oxide-semiconductor field-effect transistors (MOSFETs) hold promising application prospects in future high-capacity high-power converters due to their excellent electrothermal characteristics. However, as nascent power electronic devices, their long-term operational reliability lacks sufficient field data. The power cycling test is an important experimental method to assess packaging-related reliability. In order to obtain data closest to actual working conditions, forward power cycling is utilized to carry out SiC MOSFET degradation experiments. Due to the wide bandgap characteristics of SiC MOSFETs, the short-term drift of the threshold voltage is much more serious than that of silicon (Si)-based devices. Therefore, an offline threshold voltage measurement circuit is implemented during power cycling tests to minimize errors arising from this short-term drift. Different characterizations are performed based on power cycling tests, focused on measuring the on-state resistance, thermal impedance, and threshold voltage of the devices. The findings reveal that the primary failure mode under forward power cycling tests, with a maximum junction temperature of 130 degrees C, is bond-wire degradation. Conversely, the solder layer and gate oxide exhibit minimal degradation tendencies under these conditions.

Commercialization of SiC MOSFETs and electrification of the automotive sector has resulted in the accelerated development of power semiconductor devices. To take the most advantage of the SiC properties and make the power semiconductor modules automotive graded, the power module packaging technologies are developing at a rapid pace. New materials are being introduced and more innovative ways are being investigated to operate the SiC die at high temperatures while maintaining high reliability. Silver (Ag) sinter, due to its superior properties, has been introduced as a state-of-the-art die-attaching technology, while different ways are being investigated to either eliminate the aluminium (Al) bondwires or replace them with copper (Cu) counterparts. In this study, we will use the Finite Element (FE) method to investigate the impact of different packaging aspects like using copper foil and Ag sinter on thermal and mechanical performance of the power module. We will also investigate the effect of different packaging on power module reliability.

Solder layers, used as bonding material inside the power module to attach the semiconductor die on Direct Bond Copper (DBC) substrate and DBC substrate on baseplate, are one of the regions most prone to failure. The failure usually occurs in the form of solder cracks and depends on various operating conditions, such as-maximum temperature, temperature swing, and heating time. The cracks generated inside the solder layers can eventually result in its delamination. Power modules are usually power cycled to estimate the failure sites and mechanisms. However, the failure mechanisms can vary depending on the frequency, amplitude, and range of the temperature in the Power Cycling Tests (PCT). In this study, we have used the Finite Element Method (FEM) in COMSOL Multiphysics to analyse the impact of the PCT on both die attach, and baseplate attach solder layers. Additionally, the effect of the degree of asymmetry in the die position on the reliability of both the solder layers are analysed. The FEA (Finite Element Analysis) results are analysed to have a better understanding about the aspects impacting the lifetime of the power module.

Body-diode voltage drop has been identified as a reliable parameter for both as a temperature-sensitive electrical parameter (TSEP) to estimate the SiC MOSFET junction temperature and as a failure precursor to identify any package related degradation. However, in the inverse-mode power-cycling test (PCT), it is found that the body-diode voltage drop changes at a fixed temperature. It is known from the previous research that the increase in a body-diode voltage drop at heating current acts as a failure precursor, indicating package related degradation. However, the change in the voltage drop at a low measurement current, due to degradation, is not well investigated. This study aims to analyse how the body-diode voltage drop at low current changes in TO-247 packaged SiC MOSFETs during inverse and forward-mode PCT.