A 27-47-GHz differential cascode power amplifier for millimeter-wave 5G new radio applications is presented. The PA is a three-stage design using inductively coupled impedance transformers with 31-dB nominal power gain. A device periphery ratio of 1:2:6 is adopted for predriver, driver, and final stage, respectively. A gain equalization technique was used in the interstage transformers to obtain the required bandwidth with high gain flatness. To enable the use of 2.7-V supply, a cascode topology was employed in all three stages. A small signal gain of 31 dB was achieved with a 3-dB bandwidth of 20 GHz, equivalent to a 54% fractional bandwidth centered at 37 GHz. A saturated output power of 20.6 dBm was measured at 38.5 GHz. With a 100-MHz 64-QAM OFDM modulated signal at 37 GHz and at EVM =-25 dB, an output power of 11.6 dBm and an ACLR1 of-32/-30.8 dBc were obtained. An SiGe HBT BiCMOS process with f_{\mathrm{ MAX}} = 330 GHz was used for fabrication. The PA has an active area of 0.28 mm2 and is measured to a best in class FOM of 94.7 dB.

The performance of broadband microwave 40 W and 55 W LDMOS integrated power amplifiers is reported. A 30 V LDMOS process with 500 nm gate length was used for the design. Single and dual die packages were evaluated. A dual die package provides flexibility in output power and efficiency depending on combiner topology at the input and output of the circuit. Different saturated power and efficiency are obtained for different classes, Class A, AB and B operation and for different combiners, Wilkinson, quadrature or balun. Moreover, dual die in Doherty configuration provides a compact solution for better back-off efficiency in a symmetrical / asymmetrical topology. The 40 W design demonstrates 24 %, 1 dB fractional bandwidth around 2.1 GHz, and power added efficiency of 48 % at P-1 dB of 50 W. It showed excellent back-off linearity and best in class memory effect over frequency and temperature. The 55 W design has 28 %, 1 dB fractional bandwidth around 2.2 GHz, and power added efficiency of 49 % at P-1 dB equal to 63 W.

The performance of broadband microwave 40 W and 55 W LDMOS integrated power amplifiers is reported. A 30 V LDMOS process with 500 nm gate length was used for the design. Single and dual die packages were evaluated. A dual die package provides flexibility in output power and efficiency depending on combiner topology at the input and output of the circuit. Different saturated power and efficiency are obtained for different classes, Class A, AB and B operation and for different combiners, Wilkinson, quadrature or balun. Moreover, dual die in Doherty configuration provides a compact solution for better back-off efficiency in a symmetrical / asymmetrical topology. The 40 W design demonstrates 24 %, 1 dB fractional bandwidth around 2.1 GHz, and power added efficiency of 48 % at P-1 dB of 50 W. It showed excellent back-off linearity and best in class memory effect over frequency and temperature. The 55 W design has 28 %, 1 dB fractional bandwidth around 2.2 GHz, and power added efficiency of 49 % at P-1 dB equal to 63 W.

It is presented a signal generator for providing a first signal on a first output and a second signal on a second output wherein the first signal and the second signal are provided with phase shift relative to each other. The signal generator comprises: a control loop controller; a comparator; a phase shifter, the phase shifter being arranged to provide the first signal on the first output and the second signal on the second output; and a phase error detector, the inputs of which are connected to the outputs of the phase shifter and the output of which is connected to an input of the control loop controller. The output of the control loop controller is connected in a feedback loop to a first input of the comparator, and a second input of the comparator is arranged to be connected to an alternating current source.

The noise response in a passive mixer circuit is improved by discharging the switching transistors in the mixer circuit in an appropriate time slot prior to activation. In addition to improving the noise response, tilt in conversion gains and linearity can be reduced. A passive mixer circuit includes bypass switches arranged in proximity to the switching transistors that make up the mixer core. These bypass switches, which are activated in intervals just prior to the active intervals of their neighboring switching transistors, discharge to ground accumulated charges on the switching transistors or on reactive components around switches.