Nanoelectromechanical (NEM) switches have near vertical turn-off transient, zero off-state leakage, and non-volatile behavior, ideal qualities for low power computing and memory applications. To realize this potential, large-scale integration of NEM switches is required. Here we introduce a three-dimensional (3-D) heterogeneous integration platform that leverages a standard silicon-on-insulator (SOI) CMOS foundry process, combined with post-processing of the foundry wafers to integrate silicon NEM switches. Within this platform, we seamlessly integrated both volatile 3-terminal (3-T) and nonvolatile 7-terminal (7-T) NEM switches. We demonstrate successful electrical programming and reprogramming of both switch types, validating the platform’s functionality and its potential for constructing densely integrated NEM switch-based logic circuits and non-volatile memories.

The rapid growth of data-intensive applications such as edge computing, artificial intelligence and the Internet of Things is pushing the limits of conventional CMOS electronics. In these systems, static leakage currents increasingly dominate power consumption. Nanoelectro-mechanical (NEM) switches are promising candidates for beyond-CMOS electronics due to their near-zero off-state leakage, abrupt switching characteristics, and robustness under extreme operating conditions, offering a route to dramatically reduce static power dissipation in future integrated circuits. However, practical NEM-based systems require scalable device architectures, reliable switch contacts, and CMOS-compatible integration strategies. This thesis addresses these challenges through the realization and integration of a CMOS-compatible NEM switch device library within commercial CMOS foundry platforms. The work investigates three complementary NEM switch architectures for logic and memory applications: a volatile three-terminal (3-T) switch, a volatile four-terminal (4-T) switch with decoupled actuation and signal paths, and a non-volatile seventerminal (7-T) switch. Building upon concepts established in earlier research within our group, the 3-T and 7-T devices are miniaturized and optimized through systematic studies of beam geometry and contact materials for low-voltage operation and improved switching behavior. A major contribution of this thesis is the optimization and experimental realization of the 4-T architecture, enabling body-bias-assisted reduction of the pull-in voltage and advanced circuit configurations. Two CMOS-compatible integration approaches are developed and experimentally validated: (1) Monolithic integration within the IMEC iSiPP50G silicon photonics SOI foundry platform, and (2) heterogeneous 3-D integration within the X-FAB XI10 SOI CMOS process. The first method enabled co-fabrication of all three NEM switch architectures on a single commercial foundry chip for the first time. Electrical characterization confirms volatile switching in the 3-T and 4-T devices, pull-in voltage reduction in the 4-T switch through body biasing, and both volatile and nonvolatile operation in the 7-T switch through contact engineering. However, in this approach, circuit scalability is limited by routing density inherent to planar integration, while Au contact stiction constrains switch reliability. The second approach addresses these limitations by vertically integrating the NEM device layer above the completed back-end-of-line (BEOL) through heterogeneously 3-D integration. This architecture alleviates routing constraints and improves device reliability using Ruthenium (Ru) switch contacts. Ru-coated devices demonstrate substantially improved cycling endurance, and a complementary inverter implemented with Ru-coated 3-T switches validates the feasibility of functional BEOL-integrated NEM circuits.

Nanoelectromechanical (NEM) switches are promising for ultra-low-power electronics in harsh environments due to their zero leakage current and radiation hardness. However, their mechanical robustness under extreme loads remains insufficiently studied. This work investigates the performance of 3-terminal and 7-terminal NEM relays subjected to mechanical shocks up to 5000 g and vibrations up to 70 g. All tested devices retained mechanical functionality, confirming excellent structural integrity. Electrical characterisation revealed variations in pull-in and pull-out voltages and loss of programmed states in 7T relays, although their non-volatile capability remained intact. These instabilities are primarily attributed to the soft Au contact coating, which is prone to wear and deformation. The findings highlight the suitability of NEM technology for harsh environments and point to future improvements through more suitable contact materials and device miniaturization.

Nanoelectromechanical (NEM) relays have emerged as a compelling alternative to solid-state switches for digital logic and power gating due to their near-zero off-state leakage and abrupt turn on/off characteristics. Here, we demonstrate a novel application of a dual-beam, 4-terminal NEM relay to function as a direct voltage comparator for Pulse-Width-Modulation (PWM) encoding in Voltage-to-Time converter (VTC) applications. A prototype device with an actuation airgap of 400nm was fabricated on a silicon-on-insulator substrate and the switch contact features were coated with ruthenium to improve the cycling lifetime. The pull-in and pull-out voltages of the relay were measured to be 13.21 V and 10.22 V, respectively. In subsequent experiments the relay successfully converted a slow sinusoidal signal into a duty-cycle-modulated output. Although the input frequency was deliberately kept low to accommodate reliability issues in the prototype, this work serves as a proof-of-concept to showcase the potential of using our 4-T NEM relay as a building block in VTC applications at the edge of the network.

Electrostatically operated micro- and nanoelectromechanical (MEM/NEM) relays have been proposed as digital switches to replace transistors due to their sharp turn-on/off transient, zero leakage current between drain and source in the OFF-state, and capability to operate at far higher temperatures and radiation levels than CMOS. However, the different components associated with energy consumption in MEM/NEM relays, including the dynamic energy associated with charging the gate capacitance and static energy lost through substrate leakage, have not been investigated to date. Here, we present a detailed analysis of the energy consumption of NEM/MEM relays starting from first principles and compare against measurements carried out on silicon MEM relay prototypes. The dynamic energy consumed by a transistor in a binary switching transfer is accurately captured by 0.5CV2. This expression, which has also been used for relays, is only valid under the approximation of an unvarying capacitance C. However, the gate capacitance of an MEM/NEM relay varies as a function of gate voltage, as it is determined by the airgap between the gate electrode and the moving beam. We show how including this effect adds an extra term to the dynamic energy consumption expression. Furthermore, we investigate different current leakage mechanisms and devise a new method to estimate the substrate leakage current based on using the switching hysteresis of relays. The models, analyses, and measurement methodologies presented here constitute a set of essential techniques for accurate estimation of the energy consumption of MEM/NEM relays in ultralow power circuit applications.

Electrostatically operated micro and nanoelectromechanical (MEM/NEM) relays have been proposed as digital switches to replace transistors due to their sharp turn-on/off transient, zero leakage current between drain and source in the off state, and capability to operate at far higher temperatures and radiation levels than CMOS. However, the dynamic energy associated with charging the gate capacitance have not been investigated or verified to date. Here, we present a detailed analysis starting from first principle formulations and derive a new closed form formula for the dynamic energy consumption of MEM/NEM relays as a function of the pull-in voltage, and open-state and closed-state gate capacitances. We compare against measurements carried out on prototype silicon MEM relays to verify our analysis. We also use the derived analytic model for energy consumption to carry out a scaling study, and compare against CMOS for room temperature and high temperature operation, and show that significant energy savings are possible. The models, analyses and measurement methodologies presented here constitute a set of essential techniques for accurate estimation of the energy consumption of MEM relays in ultra-low power circuit applications.

Nanoelectromechanical (NEM) switches havepromising applications as volatile or non-volatileelectronic switching elements in areas such as low-powerlogic, memory, and reconfigurable circuits. However, thereliability of nano-scale contacts in NEM switches remainsa major challenge. While ruthenium (Ru) has beensuccessfully used for micro-scale contacts in radiofrequency (RF) MEMS switches with relatively largedimensions, Ru has not been explored as contact coating inNEM switches. Here, we investigate and demonstrate theeffectiveness of Ru-coated nano-contacts in silicon NEMswitches, enabling both volatile and non-volatile switchingof NEM switches fabricated within the same NEM devicelayer. These findings have the potential to advance NEMswitch technology for low-power and reconfigurablecomputing applications.

Nanoelectromechanical (NEM) switches have the advantages of zero leakage current, abrupt switching characteristics, and harsh environmental capabilities. This makes them a promising component for digital computing circuits when high energy efficiency under extreme environmental conditions is important. However, to make NEM-based logic circuits commercially viable, NEM switches must be manufacturable in existing semiconductor foundry platforms to guarantee reliable switch fabrication and very large-scale integration densities, which remains a big challenge. Here, we demonstrate the use of a commercial silicon-on-insulator (SOI) foundry platform (iSiPP50G by IMEC, Belgium) to implement monolithically integrated silicon (Si) NEM switches. Using this SOI foundry platform featuring sub-200 nm lithography technology, we implemented two different types of NEM switches: (1) a volatile 3-terminal (3-T) NEM switch with a low actuation voltage of 5.6 V and (2) a bi-stable 7-terminal (7-T) NEM switch, featuring either volatile or non-volatile switching behavior, depending on the switch contact design. The experimental results presented here show how an established CMOS-compatible SOI foundry process can be utilized to realize highly integrated Si NEM switches, removing a significant barrier towards scalable manufacturing of high performance and high-density NEM-based programmable logic circuits and non-volatile memories.

Nanoelectromechanical relays are inherently radiation hard and can operate at high temperatures. Thus, they have potential to serve as the building blocks in non-volatile memory that can be used in harsh environments with zero standby power. However, a reprogrammable memory cell built entirely from relays that can be operated with a digital protocol has not yet been demonstrated. Here, we demonstrate a fully mechanical digital non-volatile memory cell built from in-plane silicon nanoelectromechanical relays; a 7-terminal bistable relay utilizes surface adhesion forces to store binary data without consuming any energy, while 3-terminal relays are used for read and write access without the need for CMOS. We have optimized the designs to prevent collapse to the substrate under actuation and recorded voltages of 13, 13.2 and 27V for programming, read and reprogramming operations. This non-volatile memory cell can potentially be used to build embedded memories for edge applications that have stringent temperature, radiation and energy constraints.

We present 4-terminal (4-T) silicon (Si) nanoelectronmechanical (NEM) relays fabricated on silicon-oninsulator (SOI) wafers. We demonstrate true 4-T switching behavior with isolated control and signal paths. A pull-in voltage as low as 11.6 V is achieved with the miniaturized design. 4-T NEM relays are a very promising candidate for building ultra-low-power logic circuits since they enable novel circuit architectures to realize logic functions with far fewer devices than CMOS implementations, while also allowing the dynamic power consumption to be reduced by body-biasing.