The typical fault clearance time in an AC grid is approximately 200 ms. Grid-connected power converters should be able to deliver increased currents during this time. This paper investigates the over-current (OC) capability using microchannel (MC) cooling below the chip using COMSOL simulations with SiC MOSFETs. The paper also compares thermal performance of MCs above and below the chip. The maximum allowable chip temperature is assumed to be 250 °C since SiC devices do not fail up to this temperature if the package is adapted for such operation. OC durations is from a few milliseconds to a few seconds. It is concluded that MC cooling below the chip can potentially increase the OC capability. However, the OC capability is significantly superior when MC cooling is applied on top of chip.

The fault clearance time in the power system can vary from a few milliseconds to a few hundred milliseconds. Power electronics converters should be able to provide the increased current during faults without failing due to thermal limits. Hence, the heat generated in the semiconductor chip due to the over-current (OC) should be removed as soon as it is generated. In this paper, cooling by heat-absorbing material has been investigated on the top, bottom, and top + bottom of the SiC MOSFET chip using COMSOL simulations for OCs. The heat-absorbing materials considered in the paper are copper, graphite, and aluminum. The maximum allowed chip temperature is assumed to be 250 ˆC since SiC devices do not fail in this range of temperature. It is concluded that the cooling on the top of the chip has the best performance among the three arrangements discussed in the paper in terms of OC duration and steady-state temperature. Another conclusion is that copper has the best performance due to higher thermal capacity for the same volume of the heat-absorbing material.

Over-currents (OCs) in the power system could be caused by fluctuations in the load, bus voltage, etc. In this article, TO-247 MOSFETs have been stressed for over-currents with a pulse duration of approximately 1 ms for two times OCs (2 OCs) to five times OCs (5 OCs). The junction temperature has been estimated and the failure modes are discussed. It has been observed that the devices do not show degraded behavior (change in on-state resistance and threshold voltage) for 100 cycles until 4.5 OCs. The devices failed anywhere between the first cycle to seven cycles for 4.8 OC and the devices always failed in the first cycle for 5 OCs. This observation gives an estimation of the limit of stressing the devices for short pulses of a few milliseconds.

Fault clearance time in the power system with renewables generally varies from 0.5-10 cycles (10-667 ms for 50 Hz). Power electronic converters should be able to provide an increased current without exceeding the thermal limits during faults. Accordingly, the heat generated in the semiconductor chip during over-current (OCs) should be removed from the chip as soon as it is generated. In this paper, microchannel (MC) cooling has been investigated through COMSOL simulations for OCs with SiC MOSFETs. The upper limit of the chip temperature has been assumed to be 250 °C as SiC devices do not fail in this temperature range. The duration of OCs is from a few tens of milliseconds to a few seconds. It is concluded that MC cooling has the potential to increase the duration of OC without reaching the assumed upper limit of the temperature.