Spiking Neural Networks (SNNs) are a promising alternative to conventional Artificial Neural Networks (ANNs) due to their biological interpretability and capability to exploit sparse computation. Specialized hardware for SNNs has potential advantages over general-purpose devices in terms of power and performance. However, the computational requirements of modern Spiking Convolutional Neural Networks (SCNNs) renders most SNN hardware inefficient for SCNN acceleration. As a step towards efficient SCNN acceleration, we present IncineRate, a flexible FPGA-based SCNN accelerator architecture. IncineRate has built-in support for many SCNNs, such as AlexNet, VGG16, and ResNets, and can be extended to support other network models. The number of simulation time steps, the network architecture, and other settings are specified at run time, so an already deployed device can execute multiple networks without reconfiguration. Our results show that IncineRate achieves state-of-the-art classification accuracy among FPGA-based SCNNs on CIFAR10 and CIFAR100.

Spiking Neural Networks (SNNs) are models that mimic and replicate the computational properties of the biological brain. Computation is performed using neurons that transmit information on axons between each other via synapses. SNNs have several important application areas, ranging from (brain-like) artificial intelligence to complex brain simulations. Most SNN simulations today are carried out on systems such as CPUs and GPUs, which fit SNNs poorly and often yield slow solutions that consume needlessly much energy. In this work, we present algorithms for efficient simulation of SNNs on Field-Programmable Gate Arrays (FPGAs), which is driven by our hypothesis that said devices can be much more power-efficient without sacrificing execution performance. We also provide an in-depth analysis and discussion of our algorithms and techniques. We target the important Potjans-Diesmann model, a well-known cortical microcircuit often used for assessing SNN simulation performance. Using high-level synthesis (HLS) targeting the latest Intel Agilex 7 FPGA, we show that our best simulator can execute the microcircuit 25% faster than real-time and require only 21 nJ per synaptic event. Our result surpasses the state-of-the-art for single-device simulation, and the energy use is the lowest among published results.

Motivated by the difficulties in training Spiking Neural Networks  (SNNs), ANN-to-SNN conversion converts an existing Artificial Neural  Network (ANN) into its spiking analog. Conversion facilitates reuse  of mature ANN training pipelines, but SNN inference introduces an  accuracy-latency trade-off. This trade-off is the central challenge  of conversion: maximizing accuracy while minimizing latency. Since  conversion was first proposed in 2015, the field has flourished and  today comprises about a hundred articles. Beyond the  accuracy-latency trade-off, many conversion methods tackle  operations in vision architectures that are nontrivial in SNNs, such  as max pooling, batch normalization, and residual connections. This  guide teaches ANN-to-SNN conversion for vision---from core  principles to the state-of-the-art---through a common analytical  framework. It characterizes most published ANN-to-SNN conversion  methods from 2015 to 2025, compares them both quantitatively and  qualitatively, and critically analyzes the field as a whole. It  serves as an accessible introduction for beginners and as a  consolidated reference for researchers.