In this paper, we present a parallel hybrid decoder for decoding primitive rateless (PR) codes. The proposed decoder integrates multiple-bases belief propagation (MBBP) with low-order ordered-statistics decoding (OSD), effectively reducing the complexity associated with high-order OSD, especially for low-rate codes operating in low signal-to-noise ratio (SNR) regimes. We evaluate the block error rate (BLER) performance of the decoder and propose an optimization method using a genetic algorithm to generate diverse parity-check matrices that further minimize the BLER. Simulation results demonstrate that PR codes decoded with the proposed low-complexity parallel hybrid decoder achieve performance very close to the normal approximation (NA) benchmark. PR codes, being adaptable to any desired length and rate, coupled with the proposed decoder, emerge as a promising solution for short-packet communication scenarios demanding stringent latency and reliability.

In this letter, we propose a novel decoding scheme for primitive rateless (PR) codes to improve belief propagation (BP) performance in the short blocklength regime. We first design the PR codes using primitive polynomials whose supports form a Golomb ruler, enabling the construction of a 4-cycle-free parity-check matrix (PCM) without the need for auxiliary variable nodes. We introduce a second PCM derived by sorting channel log-likelihood ratios and applying Gaussian elimination. The double-bases decoder operates by running BP decoding in parallel on both PCMs, and selecting the candidate codeword with the shorter Euclidean distance to the received signal. Simulation results show that the proposed double-bases BP approach can outperform the multiple-bases BP decoder while reducing the number of required PCMs and complexity. The PR code paired with the proposed decoder offers competitive performance compared to 5G-polar, RM, and LDPC codes in the short blocklength regime.

This paper presents the analysis and a proof-of-concept design of the low-complexity early termination hybrid automatic repeat request (ET-HARQ) for ultra-reliable low-latency communication (URLLC). In ET-HARQ, unfit packets are flagged for retransmission prior to decoding, a process that significantly diminishes decoding complexity and facilitates swift HARQ reporting. This characteristic makes ET-HARQ well-suited for URLLC applications. We analyze the impact of ET-HARQ on the packet error rate (PER), throughput, and complexity performance in the finite block length regime, taking into consideration cyclic redundancy check (CRC) limitations. Numerical results indicate that ET-HARQ significantly reduces the decoding complexity and improves throughput with little to no loss in the PER. In addition, ET-HARQ demonstrates resilience even with a short CRC, whereas the imperfections of a short CRC significantly impact PER reliability in standard HARQ. To validate our analysis, we also design a practical early termination mechanism involving belief propagation and neural network (BP-NN) to predict the decodability of the received packet. Testing with BCH and CRC-polar codes shows that it can reach up to a 70 %similar to 80 % prediction accuracy with packet lengths less than 128 bits encoded with high-density linear block codes. Simulation shows that the BP-NN-based ET-HARQ has significantly lower complexity at this accuracy level than the standard HARQ with similar reliability.

We investigate the performance of primitive rateless (PR) codes and introduce an enhanced ordered statistics decoder (OSD) designed for decoding them. We demonstrate that constructing PR codes using linear Boolean functions simplifies decoding to identifying dual bases over GF(2^k). By leveraging self-dual bases over GF(2^k), the decoding process for high-rate PR codes is simplified, contributing to a reduced complexity OSD algorithm. Through simulations, we establish that high-rate PR codes can achieve block error rates comparable to their BCH counterparts across various signal-to-noise ratios (SNRs) and code rates. The PR code can be tailored to any rate and block length, and the proposed OSD algorithm makes it well-suited for low-latency applications.