Not AND (NAND) flash memory has been widely used in consumer electronics in recent years. Due to various interferences faced by NAND flash memory, data reliability has severely declined. Low-density parity-check (LDPC) codes are leveraged for popular triple-level cell (TLC) NAND flash due to their strong error correction capability. LDPC decoding is an iterative procedure of log-likelihood ratio (LLR). The absorbing sets cause inaccurate LLRs to continuously propagate, making decoding difficult to converge, and severely affecting decoding performance. To improve decoding performance after LLR quantization, we propose an absorbing set characteristic aware LDPC algorithm, called AsLDPC, which modifies the LLR of some nodes in the absorbing sets through two Steps. For Step One, we select variable nodes that fall into absorbing sets based on sign characteristics of LLR at the late iteration and modify the initial prior message. For Step Two, we adjust the LLR of check nodes that satisfy the variable nodes and utilize the revised LLR to continue iteration. AsLDPC abstracts the process of finding the node locations in absorbing sets into formulas, finds the erroneous nodes through calculation, and then modifies their LLR messages. Simulation results demonstrate that AsLDPC significantly reduces the frame error rate (FER) by 58% and 48.1% for two LDPC codes, respectively, when compared to the quasi-uniform quantization scheme, while also reducing decoding latency. Additionally, AsLDPC outperforms the uniform algorithm in terms of storage space efficiency and maintains accurate decoding capabilities for raw bit error rate (RBER) below 1.2e - 2.

Due to the complexity and diversity of deep convolutional neural networks (CNNs), Network-on-chip (NoC) based CNN accelerators have grown in popularity to improve inference efficiency and flexibility. Current optimization approaches focus on computational-heavy layers. Therefore, pooling layers are often ignored and processed individually using general processing units. In this work, we explore the acceleration of pooling layers by in-network processing. We propose a pooling on-the-go method to do the pooling operations while transmitting its prior layer outputs. Consequently, we combine the pooling layer with its prior convolution layer to remove unnecessary data movements. We demonstrate our method on a cycle-accurate NoC-CNN accelerator simulator on two CNN models, LeNet and VGG16. The results show that the processing time of individual pooling layers is almost eliminated by around 99%. Compared with the pooling standalone baseline, we can achieve 1.09x speedup in the full LeNet model, and up to 1.16x speedup in the combined layers that our approach applies.

Network-on-Chip (NoC) based architectures are recently proposed to accelerate deep neural networks in specialized hardware. Given that the hardware configuration is fixed post-manufacture, proper task mapping attracts researchers’ interest. We propose a travel time-based task mapping method that allocates uneven counts of tasks across different Processing Elements (PEs). This approach utilizes the travel time recorded in the sampling window and implicitly makes use of static NoC architecture information and dynamic NoC congestion status. Furthermore, we examine the effectiveness of our method under various configurations, including different mapping iterations, flit sizes, and NoC architectures. Our method achieves up to 12.1% improvement compared with even mapping and static distance mapping for one layer. For a complete NN example, our method achieves 10.37% and 13.75% overall improvements to row-major mapping and distance-based mapping, respectively. While ideal travel time-based mapping (post-run) achieves 10.37% overall improvements to row-major mapping, we adopt a sampling window to efficiently map tasks during the running, achieving 8.17% (sampling window 10) improvement.

Network-on-Chip (NoC) based Deep Neural Net-work (DNN) accelerators are widely adopted, but their performance is still not satisfactory as the network congestion may enlarge the inference latency. In this work, we leverage the idea of in-network processing and propose a computation-while-blocking method to conduct activation in network that improves inference latency for NoC-based DNN accelerators. Our approach offloads the non-linear activation from processing elements (PEs) to network routers. Based on a cycle-accurate NoC-DNN simulator, we experiment on a popular neural network model LeNet. The proposed approach can achieve up to 12% speedup in the first layer, and an overall around 6% decrease in total cycles compared to the baseline.

Gait analysis helps clinical assessment and achieves comfortable prosthetic designs for lower limb amputees, in which accurate gait phase recognition is a key component. However, gait phase detection remains a challenge due to the individual nature of prosthetic sockets and limbs. For the first time, we present a gait phase recognition approach for transfemoral amputees based on intra-socket pressure measurement. We proposed a multiple GMM-HMM (Hidden Markov Model with Gaussian Mixture Model emissions) method to label the gait events during walking. For each of the gait phases in the gait cycle, a separate GMM-HMM model is trained from the collected pressure data. We use gait phase recognition accuracy as a primary metric. The evaluation of six human subjects during walking shows a high accuracy of over 99% for single-subject, around 97.4% for multiple-subject, and up to 84.5% for unseen-subject scenarios. We compare our approach with the widely used CHMM (Continuous HMM) and LSTM (Long Short-term Memory) based methods, demonstrating better recognition accuracy performance across all scenarios.

Choices of dataflows, which are known as intra-core neural network (NN) computation loop nest scheduling and inter-core hardware mapping strategies, play a critical role in the performance and energy efficiency of NoC-based neural network accelerators. Confronted with an enormous dataflow exploration space, this paper proposes an automatic framework for generating and optimizing the full-layer-mappings based on two reinforcement learning algorithms including A2C and PPO. Combining soft and hard constraints, this work transforms the mapping configuration into a sequential decision problem and aims to explore the performance and energy efficient hardware mapping for NoC systems. We evaluate the performance of the proposed framework on 10 experimental neural networks. The results show that compared with the direct-X mapping, the direct-Y mapping, GA-base mapping, and NN-aware mapping, our optimization framework reduces the average execution time of 10 experimental NNs by 9.09%, improves the throughput by 11.27%, reduces the energy by 12.62%, and reduces the time-energy-product (TEP) by 14.49%. The results also show that the performance enhancement is related to the coefficient of variation of the neural network to be computed.

In NoC-based neural network accelerators, many-to-one and many-to-many are prevalent traffic patterns. In these traffic patterns, there exists a need for communication synchronization between Processing Elements (PEs) of adjacent layers to optimize latency. The last received packet will determine the end time of a layer's computation. The Communication Synchronization-aware Arbitration Policy (CSAP) is proposed in this brief to handle this problem, which uses a negative feedback mechanism to regulate the packet sending rate of each source node. Compared with the local-age-based policy, CSAP decreases the execution by 4.69% $\sim$ 12.55% across neural networks of different scales. The proposed policy only incurs 1.06% additional hardware overhead in the router compared with the local-age-based policy.

Inspired by PiN, Processing in Network-on-Chip (NoC), we propose a computational NoC as a convolution engine for accelerating convolutional neural networks in hardware. In contrast to traditional compute architectures where computation and communication are conducted serially and in separation, our computational NoC enables in-transit computation, meaning that computation is performed while packets are transferred in the network. In the paper, we present the router architecture that supports the novel in-transit computation concept, and use a running example to detail the entire convolution process in the computational NoC. Finally, we show simulated performance results in comparison with traditional NoC-based convolution engine.

This paper proposes a gait recognition method based on the modified OVR-CSP fusion feature of plantar pressure and Long Short-Term Memory classification (referred to as the OVR-CSP-LSTM model). 10 subjects conducted 4 type of gait experiments including normal speed walking, fast walking, slow walking, imitating stroke gait walking in this paper. Transfer the commonly used Common Spatial Pattern (CSP) feature extraction method for EEG to plantar pressure signals, and splice the OVR-CSP features of 2-class, 3-class and 4-class, adopting Long Short Term Memory Network (LSTM) for classification. In this paper, the Intra-patient mode and Inter-patient mode of 10 people are modeled and compared respectively, and the recognition effects under different sensor number and different position sensors' combination are also studied. The experimental results show that the proposed model has good performance for both modes. The method proposed in this article is expected to be applied to multi-sensor signal processing and classification with spatial characteristics.

Health Condition (HC) estimation of discrete power electronic devices is an important task for ensuring their reliable operation in mission-critical applications. Assuming bond-wire failure as a specific type of package failure, we take a direct approach to address the HC estimation problem using a dataset from accelerated aging tests. We first present a new concept of HC reference curve, which intends to represent the general health status over the device's lifetime using a health score. In particular, it is defined in relation to the device's Remaining Useful Lifetime (RUL) and captures the nonlinear health degradation status. Based on the HC reference curve, we mathematically formulate the HC estimation problem, and then develop an HC estimation flow using random forest algorithm. Finally, in our experiments, we demonstrate the effectiveness of our HC estimation method and the suitability of estimating the device's health status in comparison with the RUL estimation, which is a common yet indirect approach.