The electrification of heavy-duty vehicles (HDVs) is essential for achieving zero-emission freight transport. Conventional 400–800 V powertrains face limitations in supporting megawatt-level fast charging and high continuous power due to excessive current, cable losses, and thermal stress. Recent advances in high voltage (i.e., 1.7 kV, 2 kV, 3.3 kV) silicon-carbide (SiC) power modules and charging standards such as the Megawatt Charging System (MCS, up to 1250 V) have enabled a new generation of 1.2 kV dc-link architectures for HDVs. This paper presents a comprehensive system-level evaluation of increasing the dc-link voltage from 800 V to 1.2 kV, covering the battery, inverter, and motor subsystems. The battery/charging and motor-level results are presented as analytical first-order assessments, whereas the inverter-level loss-modelling methodology is experimentally validated on a 250 kW, 1.2 kV dc-link SiC prototype. A virtual-prototyping framework is used to quantify inverter losses, thermal behavior, and volume trade-offs, and the switching frequency is optimized by jointly considering inverter and motor harmonic losses. Experimental results showthat the analytical models predict measured inverter losses within approximately 10% over the tested operating range. Under the representative charging assumptions adopted in this study, 1.2 kV dc-link voltage enables either an∼56% reduction in cable conduction losses or an∼33% reduction in cable mass, while the prototype achieves an efficiency of ∼99.12%, a specific power density of 49.4 kW/L, and a bounding-box-based volumetric power density of 20.83 kW/L. The results provide system-level assessment and experimentally supported inverter-level design guidance for 1.2 kV HDV powertrains.

This article presents a novel bipolar field excitation system for pole-changing electrically excited synchronous machines. Conventional wireless power transfer (WPT)-based systems realize bipolar field current through receiver-side active converters and wireless gate-signal transmission, which increases complexity and reduces reliability. The proposed approach employs a dual-input, dual-output WPT system with anti-parallel outputs and a self-driven MOSFET-diode configuration, enabling bipolar current flow without rotor-side active converters or control signals. This simplifies the system, reduces control complexity, and enhances reliability. A small-scale proof-of-concept prototype has been experimentally validated, demonstrating bipolar current reversal up to 2.88 A (118 W) with a self-driven rectifier efficiency of 99% under an inductive load emulating the field windings.

Two-level voltage source inverters (2L-VSIs) are widely used in industrial motor drives due to their simplicity and cost-effectiveness. However, their pulsating output voltages introduce common-mode voltage (CMV) issues, leading to challenges such as electromagnetic interference (EMI), winding insulation stress, and bearing currents. While adopting an advanced topology or employing common-mode filters can mitigate CMV-based problems, these solutions often increase system complexity and cost. Alternatively, modulation-based techniques offer a simpler, hardware-free approach to reduce CMV. This paper proposes a modulation-based technique that introduces an adaptive carrier phase shift for sinusoidal pulse width modulation (SPWM) to address CMV issues in 2L-VSIs. Unlike conventional methods that rely on fixed carrier phase shifts (e.g., interleaved 0°, 120°, and 240°), the proposed approach dynamically adjusts the phase shift within each switching interval to effectively suppress CMV. The proposed technique was validated through both experimental testing and analytical modeling to demonstrate CMV reduction. This approach offers a practical and scalable solution for industrial motor drives, still having the inherent simplicity and cost-effectiveness of two-level VSIs.

The demand for robust and energy-efficient traction inverters in heavy-duty electric vehicles (HDVs) has accelerated the development of advanced Power-Hardware-in-the-Loop (PHIL) testbeds that enable realistic and repeatable validation scenarios. This paper proposes an improved back-to-back (B2B) hardware test setup that replicates the full power map of a traction inverter under realistic drive cycle conditions. A passive-damped LCL filter is introduced between inverter phases to enhance power control and maintain a high power factor over a wide frequency range, particularly in the motor's field-weakening region. A two-stage optimization framework is developed to determine the filter parameters, ensuring minimal inductor values while achieving constant power transfer. Furthermore, the feasibility of active damping using capacitor voltage and current sensing is investigated to reduce external power supply losses in the passive damping resistances. The proposed configuration enhances testbed accuracy and efficiency, facilitating safer tests and more effective high-power inverter validation.

Interoperability in HVDC systems could be supported with open upper-level control and protection (C&P) software, while hardware-near C&P functions stay black-boxed and proprietary. Methodologies like model-based systems engineering and graph theory can assist in defining the boundary between open and closed software. Most likely, partially open C&P software in HVDC is not hindered by legislation, but has to be addressed in contractual agreements. Also, a new responsibility matrix for testing is proposed.

This paper presents a practical condition monitoring method for detecting bond wire degradation in TO247 packaged SiC MOSFET devices using ON-state resistance (R_dsON) compensated for junction temperature variations. While R_dsON is a promising health indicator, its strong dependence on junction temperature (T_j) limits its direct applicability in realworld systems. To overcome this, a novel approach is proposed that uses the temperature measured at the drain leg (T_Midleg) as a proxy for T_j, enabling temperature-compensated R_dsON measurements during power cycling tests (PCT). The method is experimentally validated on two SCT30N120 SiC MOSFET devices under active power cycling test conditions. The results demonstrate a clear correlation between the increase in R_dsON measured at the defined T_MidLeg and bond wire degradation, with similar trends observed when R_dsON is evaluated at the minimum junction temperature (T_j,min) estimated using the TSEP method. Failure analysis confirms bond wire cracking without significant solder layer delamination, demonstrating the effectiveness of the proposed method for bond wire-related failure detection.

This study analyzes the sequential failure and remaining useful life (RUL) of a multi-chip power module (MCPM) using finite element (FE) simulation, an empirical lifetime model, and recursive deconvolution. The FE model captures electro-thermal interactions, while the empirical model estimates failure probabilities from power cycling test data. The deconvolution method refines the probability density function of the first failure, providing deeper insights into degradation trends. Results show that the first die in an MCPM can fail significantly earlier than the last, with temperature imbalances contributing to this variation. Despite early failures, the system can continue operating with minor thermal impacts. These findings highlight the need for adaptive failure management and improved thermal design to enhance reliability and system life time.

This paper presents a condition monitoring approach for SiC MOSFET devices by compensating the ON-state resistance (R_dson ) to effectively detect package-related failures. While R_dsON is a promising health indicator, its strong dependence on junction temperature (T_j) and threshold voltage (V_th ) can obscure degradation signals. This study proposes compensation techniques to mitigate the influence of T_j and V_th  drift, enabling reliable monitoring. The methodology is validated using a custom-designed power cycling test bench, in compliance with AQG-324, to stress SiC MOSFETs under controlled thermal conditions. Two R_dson drift compensation methods are compared to analyze the evolution of compensated R_dSON: a moving polynomial fit (Method 1) and a derivative-based technique with post-filtering (Method 2). Results show that both methods can differentiate between linear (die-level degradation) and non-linear (package-related failure) regions of R_dsON  drift. However, Method 1 provides more stable estimates with lower noise, especially for smaller window sizes. The findings support the use of compensated R_dSON as a practical and robust condition monitoring parameter for SiC MOSFET reliability assessment.

Interconnecting power converters (IPCs) are the main elements enabling the interconnection of multiple high-voltage alternating current (HVac) and high-voltage direct current (HVdc) subgrids. To ensure stable operation of the resulting hybrid ac/dc systems, grid-following (GFL) and grid-forming (GFM) controls need to be carefully assigned to individual IPC terminals when using common IPC controls. In contrast, dual-port GFM control imposes a stable voltage on the ac and dc terminals and can be deployed on all IPCs regardless of the network configuration. In this work, we use hybrid ac/dc admittance models, eigenvalue sensitivities, and case studies to analyze and quantify the underlying properties of ac-GFM control, ac-GFL, and dual-port GFM control. Compared to common ac-GFM and ac-GFL controls, dual-port GFM control: 1) renders IPCs dissipative over a much wider range of frequencies and operating points; 2) significantly reduces the sensitivity of IPC small-signal dynamics to operating point changes; and 3) exhibits an improved dynamic response to severe contingencies. Finally, the results are illustrated and validated in an experimental scaled-down point-to-point HVdc system.

Grid-forming converters can emulate the behavior of a synchronous generator through frequency droop control. The stability of grid-forming modular multilevel converters can be studied via the impedance-based stability criterion. This paper presents an ac-side impedance model of a grid-forming modular multilevel converter which includes a complete grid-forming control structure. The impact of different control schemes and parameters on the closed-loop output impedance of the converter is thoroughly analyzed and the learnings have been used in mitigating undesired control interactions with the grid. The results are verified through simulations in time- and frequency-domains along with experiments on a down-scaled laboratory prototype.