Electrostatically operated micro- and nanoelectromechanical (MEM/NEM) relays have been proposed as digital switches to replace transistors due to their sharp turn-on/off transient, zero leakage current between drain and source in the OFF-state, and capability to operate at far higher temperatures and radiation levels than CMOS. However, the different components associated with energy consumption in MEM/NEM relays, including the dynamic energy associated with charging the gate capacitance and static energy lost through substrate leakage, have not been investigated to date. Here, we present a detailed analysis of the energy consumption of NEM/MEM relays starting from first principles and compare against measurements carried out on silicon MEM relay prototypes. The dynamic energy consumed by a transistor in a binary switching transfer is accurately captured by 0.5CV2. This expression, which has also been used for relays, is only valid under the approximation of an unvarying capacitance C. However, the gate capacitance of an MEM/NEM relay varies as a function of gate voltage, as it is determined by the airgap between the gate electrode and the moving beam. We show how including this effect adds an extra term to the dynamic energy consumption expression. Furthermore, we investigate different current leakage mechanisms and devise a new method to estimate the substrate leakage current based on using the switching hysteresis of relays. The models, analyses, and measurement methodologies presented here constitute a set of essential techniques for accurate estimation of the energy consumption of MEM/NEM relays in ultralow power circuit applications.

Nanoelectromechanical (NEM) switches have the advantages of zero leakage current, abrupt switching characteristics, and harsh environmental capabilities. This makes them a promising component for digital computing circuits when high energy efficiency under extreme environmental conditions is important. However, to make NEM-based logic circuits commercially viable, NEM switches must be manufacturable in existing semiconductor foundry platforms to guarantee reliable switch fabrication and very large-scale integration densities, which remains a big challenge. Here, we demonstrate the use of a commercial silicon-on-insulator (SOI) foundry platform (iSiPP50G by IMEC, Belgium) to implement monolithically integrated silicon (Si) NEM switches. Using this SOI foundry platform featuring sub-200 nm lithography technology, we implemented two different types of NEM switches: (1) a volatile 3-terminal (3-T) NEM switch with a low actuation voltage of 5.6 V and (2) a bi-stable 7-terminal (7-T) NEM switch, featuring either volatile or non-volatile switching behavior, depending on the switch contact design. The experimental results presented here show how an established CMOS-compatible SOI foundry process can be utilized to realize highly integrated Si NEM switches, removing a significant barrier towards scalable manufacturing of high performance and high-density NEM-based programmable logic circuits and non-volatile memories.

Nanoelectromechanical relays are inherently radiation hard and can operate at high temperatures. Thus, they have potential to serve as the building blocks in non-volatile memory that can be used in harsh environments with zero standby power. However, a reprogrammable memory cell built entirely from relays that can be operated with a digital protocol has not yet been demonstrated. Here, we demonstrate a fully mechanical digital non-volatile memory cell built from in-plane silicon nanoelectromechanical relays; a 7-terminal bistable relay utilizes surface adhesion forces to store binary data without consuming any energy, while 3-terminal relays are used for read and write access without the need for CMOS. We have optimized the designs to prevent collapse to the substrate under actuation and recorded voltages of 13, 13.2 and 27V for programming, read and reprogramming operations. This non-volatile memory cell can potentially be used to build embedded memories for edge applications that have stringent temperature, radiation and energy constraints.

Silicon photonics is an excellent platform for integrated cavity optomechanics due to silicon's high light confinement and favorable mechanical properties. However, optomechanical devices require a vacuum environment to inhibit damping due to air.We present an integrated platform for cavity optomechanics using thermo-compression bonding of silicon caps to provide on-chip vacuum sealing. We demonstrate optomechanical coupling in a vacuum-sealed ring resonator implemented on the platform, either by modulation of the laser power or by using an electrostatic phase shifter in the ring.By enabling optomechanics on a standard platform, we aim to make the technology available to a wider user base.

We present 4-terminal (4-T) silicon (Si) nanoelectronmechanical (NEM) relays fabricated on silicon-oninsulator (SOI) wafers. We demonstrate true 4-T switching behavior with isolated control and signal paths. A pull-in voltage as low as 11.6 V is achieved with the miniaturized design. 4-T NEM relays are a very promising candidate for building ultra-low-power logic circuits since they enable novel circuit architectures to realize logic functions with far fewer devices than CMOS implementations, while also allowing the dynamic power consumption to be reduced by body-biasing.

We present 4-terminal (4-T) silicon (Si) nanoelectron-mechanical (NEM) relays fabricated on silicon-on-insulator (SOI) wafers. We demonstrate true 4-T switching behavior with isolated control and signal paths. A pull-in voltage (Vpi ) as low as 11.6 V is achieved with the miniaturized design. 4-T NEM relays are a very promising candidate for building ultra-low-power logic circuits, since they enable novel circuit architectures to realize logic functions with far fewer devices than CMOS implementations, while also allowing the dynamic power consumption to be reduced by body-biasing.

NEM relay-based circuits can operate in harsh environmental conditions, high temperatures and high levels of radiation, without consuming energy in standby mode. These attributes make NEM relay technology very attractive for edge computing applications in industrial and manufacturing sectors. Here we describe a complete hardware platform for designing and fabricating densely integrated NEM relay circuits, and discuss the design of several prototypes we are developing to showcase this technology.

Integrated nanoelectromechanical (NEM) relays can be used instead of transistors to implement ultra-low power logic circuits, due to their abrupt turn-off characteristics and zero off-state leakage. Further, realizing circuits with 4-terminal (4-T) NEM relays enables significant reduction in circuit device count compared to conventional transistor circuits. For practical 4-T NEM circuits, however, the relays need to be miniaturized and integrated with high-density back-end-of-line (BEOL) interconnects, which is challenging and has not been realized to date. Here, we present electrostatically actuated silicon 4-T NEM relays that are integrated with multi-layer BEOL metal interconnects, implemented using a commercial silicon-on-insulator (SOI) foundry process. We demonstrate 4-T switching and the use of body-biasing to reduce pull-in voltage of a relay with a 300 nm airgap, from 15.8 V to 7.8 V, consistent with predictions of the finite-element model. Our 4-T NEM relay technology enables new possibilities for realizing NEM-based circuits for applications demanding harsh environment computation and zero standby power, in industries such as automotive, Internet-of-Things, and aerospace.

Silicon photonics has emerged as a mature technology that is expected to play a key role in critical emerging applications, including very high data rate optical communications, distance sensing for autonomous vehicles, photonic-accelerated computing, and quantum information processing. The success of silicon photonics has been enabled by the unique combination of performance, high yield, and high-volume capacity that can only be achieved by standardizing manufacturing technology. Today, standardized silicon photonics technology platforms implemented by foundries provide access to optimized library components, including low-loss optical routing, fast modulation, continuous tuning, high-speed germanium photodiodes, and high-efficiency optical and electrical interfaces. However, silicon's relatively weak electro-optic effects result in modulators with a significant footprint and thermo-optic tuning devices that require high power consumption, which are substantial impediments for very large-scale integration in silicon photonics. Microelectromechanical systems (MEMS) technology can enhance silicon photonics with building blocks that are compact, low-loss, broadband, fast and require very low power consumption. Here, we introduce a silicon photonic MEMS platform consisting of high-performance nano-opto-electromechanical devices fully integrated alongside standard silicon photonics foundry components, with wafer-level sealing for long-term reliability, flip-chip bonding to redistribution interposers, and fibre-array attachment for high port count optical and electrical interfacing. Our experimental demonstration of fundamental silicon photonic MEMS circuit elements, including power couplers, phase shifters and wavelength-division multiplexing devices using standardized technology lifts previous impediments to enable scaling to very large photonic integrated circuits for applications in telecommunications, neuromorphic computing, sensing, programmable photonics, and quantum computing.

The demand for efficient actuators in photonics has peaked with increasing popularity for large-scale general-purpose programmable photonics circuits. We present our work to enhance an established silicon photonics platform with low-power micro-electromechanical (MEMS) and liquid crystal (LC) actuators to enable large-scale programmable photonic integrated circuits (PICs).