Micro- and nanoscale patterning of conformal thin-film coatings on the exterior surfaces of complex three-dimensional (3D) structures is essential for emerging applications such as soft robotics, photonics, and functional 3D-printed MEMS devices. However, existing methods struggle to deliver high-resolution patterning on complex 3D structures and often suffer from poor thickness control, and inadequate surface conformity of the thin-film coatings. Here we present a robust approach for patterning of conformal thin-film coatings on complex 3D structures, including on sloped surfaces with angles up to 90°, with multiscale dimensions from 100 μm to 100 nm, and even down to the sub-30 nm scale when mask shrinkage techniques are used. This patterning approach utilizes a lithographically defined 3D Scaffold-Architected Lift-Off (SALO) mask in the lift-off process. It is agnostic to the used thin-film deposition process and enables even lift-off patterning of atomic layer deposited (ALD) conformal coatings, a task infeasible for conventional shadowing-based lift-off processes. Our approach opens opportunities for manufacturing complex 3D structures at the micro- and nanoscale by enabling lithographic patterning on the exterior surfaces of arbitrary 3D structures.

Single-molecule trapping and analysis are critical in understanding biomolecular processes at an unprecedented resolution. Traditional nanopore systems often face limitations in scalability and integration with electronic components, which complicates their use in compact, high-density applications. Addressing these challenges, we introduce a novel on-chip nanopore array system integrated with a silver (Ag) electrode and self-aligned femtolitersized cavities, representing an innovative approach for electronic single-molecule trapping. Our design utilizes a wafer-scale fabrication process with a buried electrode architecture, enabling the scalable production of high-density nanopore arrays without the need for through-wafer etching. Successful DNA translocation measurements demonstrate the system's potential as a versatile platform for single-molecule trapping and reaction studies.

ABSTRACT A device (1) and a method for fabricating such a device is described. The device (1) comprises a device layer (4), a substrate (2) defining a substrate plane (3). A device layer plane (5) is defined on the side of the device layer (4) facing the substrate (2). The device also comprises a waveguide (7) for guiding an electromagnetic wave. The waveguide (7) is supported on the substrate (2) via a support structure (6) extending from the substrate (2) to the device layer (4). The ratio of the largest distance (D1), perpendicular to the substrate plane (3), between a free surface of the waveguide (7) facing the substrate and any solid material to the height (h) of the waveguide (7) is more than 6, i.e. D1/h \textgreater 6. The ratio of the distance (D2), perpendicular to the substrate plane (3), between the device layer plane (5) and the substrate plane (3) to the height (h) of the waveguide (7) is more than 6, i.e. D2/h \textgreater 6.

Tunneling junctions are pairs of electrodes separated by gaps of a few nanometers that allow electrons to tunnel across the gap. Tunneling junctions are of great importance for applications such as label-free biomolecule sensing and single molecule electronics, but their fabrication remains difficult and laborious. In this paper, we present a simple 2-stage process for the fabrication of tunneling junctions consisting of electrode pairs made of gold (Au). This is achieved by combining a novel methodology for fabricating crack-defined Au nanowires at wafer-scale with a constant voltage, feedback-free electromigration procedure to form tunneling nanogaps free of debris.

Single nanowires have a broad range of applications in chemical and bio-sensing, photonics, and material science, but realizing individual nanowire devices in a scalable manner remains extremely challenging. This work presents a scalable and flexible method to realize single gold nanowire devices. We use conventional optical stepper lithography to generate notched beam structures, and crack lithography to obtain sub-20-nm-wide nanogaps at the notches, thereby obtaining a suitable shadow mask to define a single nanowire device. Then a gold evaporation step through the shadow mask forms the individual gold nanowires with positional and dimensional accuracy and with electrical contacts to probing pads.

Single nanowires (NWs) have a broad range of applications in nanoelectronics, nanomechanics, and nano photonics, but, to date, no technique can produce single sub 20 nm wide NWs with electrical connections in a scalable fashion. In this work, we combine conventional optical and crack lithographies to generate single NW devices with controllable and predictable dimensions and placement and with individual electrical contacts to the NWs. We demonstrate NWs made of gold, platinum, palladium, tungsten, tin, and metal oxides. We have used conventional i-line stepper lithography with a nominal resolution of 365 nm to define crack lithography structures in a shadow mask for large-scale manufacturing of sub-20 nm wide NWs, which is a 20-fold improvement over the resolution that is possible with the utilized stepper lithography. Overall, the proposed method represents an effective approach to generate single NW devices with useful applications in electrochemistry, photonics, and gas- and biosensing.

Break junctions provide tip-shaped contact electrodes that are fundamental components of nano and molecular electronics. However, the fabrication of break junctions remains notoriously time-consuming and difficult to parallelize. Here we demonstrate true parallel fabrication of gold break junctions featuring sub-3 nm gaps on the wafer-scale, by relying on a novel self-breaking mechanism based on controlled crack formation in notched bridge structures. We achieve fabrication densities as high as 7 million junctions per cm(2), with fabrication yields of around 7% for obtaining crack-defined break junctions with sub-3 nm gaps of fixed gap width that exhibit electron tunneling. We also form molecular junctions using dithiol-terminated oligo(phenylene ethynylene) (OPE3) to demonstrate the feasibility of our approach for electrical probing of molecules down to liquid helium temperatures. Our technology opens a whole new range of experimental opportunities for nano and molecular electronics applications, by enabling very large-scale fabrication of solid-state break junctions.

The ability to manufacture a nanogap in between two electrodes has proven a powerful catalyst for scientific discoveries in nanoscience and molecular electronics. A wide range of bottom-up and top-down methodologies are now available to fabricate nanogaps that are less than 10 nm wide. However, most available techniques involve time-consuming serial processes that are not compatible with large-scale manufacturing of nanogap devices. The scalable manufacturing of sub-10 nm gaps remains a great technological challenge that currently hinders both experimental nanoscience and the prospects for commercial exploitation of nanogap devices. Here, available nanogap fabrication methodologies are reviewed and a detailed comparison of their merits is provided, with special focus on large-scale and reproducible manufacturing of nanogaps. The most promising approaches that could achieve a breakthrough in research and commercial applications are identified. Emerging scalable nanogap manufacturing methodologies will ultimately enable applications with high scientific and societal impact, including high-speed whole genome sequencing, electromechanical computing, and molecular electronics using nanogap electrodes.