The temperature evolution during a short-circuit (SC) fault in the dies of three different silicon carbide (SiC) 1200-V power devices is presented in this article. Transient electrothermal simulations are performed based on the reconstructed structure of commercially available devices. The simulations reveal the location of the hottest point in each device. The nonisothermal electrical analysis supports the necessity to turn-off SC events rapidly to protect the immunity of the device after a fault. The analysis also reveal differences in delay required to turn-off devices depending on their type. A thorough analysis of the temperature rise in the die of the SiC metal-oxide semiconductor field-effect transistors (MOSFET) device is also presented, where the maximum temperature with regards to different fault cases and circuit characteristics is presented. The impact of the gate resistance, circuit inductance, detection time, drain-source voltage, and gate-source voltage are considered.

Power semiconductors, or transistors, constitute the core part of adjustable speed drives, which are commonly used in motor drive applications. Overheat of the semiconductors can compromise their behavior and, eventually, shorten the lifespan of the whole system. Therefore, the thermal management of transistors is crucial both at the design stage and during operation. Commonly performed thermal simulations normally rely on transistor thermal resistance. However, this approach does not account for the thermal behavior in transient regime. Furthermore, it is inappropriate for intermittent applications, such as for drilling machines, where the motor is on and off in repetitive working cycles, and the transistors never reach the equilibrium temperature. The transient thermal behavior is described by the concept of transfer thermal impedance. The transfer junction-to-case thermal impedance is given in the datasheet and assumes a constant ambient temperature; an assumption that is, however, not true in real applications. In this paper, we overcome this main limitation by using a resistive sensor. We consider MOSFETs in a 3-phase inverter, and model their thermal behavior with a well-known algorithm that uses the junction to-case and junction-to-ambient thermal impedances, along with application dependent parameters. The actual rise of ambient temperature of the circuit board is included in the algorithm by virtue of the resistive sensor. The method has been validated with lab measurements, for two different MOSFETs. The proposed method can be used both at the design stage and during operation of the motor drive. Future works will include refinements of the power loss formulas, of the junction-to-ambient impedance modeling, as well as aging effects of the transistors.

Wide Bandgap power semiconductors such as SiC MOSFETs, have enabled compact and highly efficient power converters operated at higher frequencies. In converters using SiC MOSFETs and capacitive snubbers, the blanking times may have a significant impact on switching losses. The power losses induced by unnecessary long blanking times have been quantified experimentally. It was found that, at 100 kHz, an adaptive blanking time can reduce the losses by more than 20 %. As those losses are directly proportional to the switching frequency, an adaptive blanking time is essential when designing for high operation frequencies. Doing so, higher operation frequencies are possible while maintaining a high efficiency.

Wide Bandgap power semiconductors such as SiC MOSFETs, have enabled compact and highly efficient power converters operated at higher frequencies. However, parasitic inductance of the package may significantly increase power losses and limit the operation. This paper aims to quantify experimentally these losses in a soft-switching converter. A "removable" stray inductance is implemented in a setup consisting of discrete SiC MOSFET units. Thus, the power loss of the transistors with and without stray inductance can be compared. Similarly slower switching speeds are also implemented to fully emulate a 62-mm module. The power loss induced by the package can thus be evaluated.

Wide Bandgap power semiconductors such as SiC MOSFETs, have enabled compact and highly efficient power converters operated at higher frequencies. However, parasitic inductance of the package may significantly increase power losses and limit the operation. This paper aims to quantify experimentally these losses in a soft-switching converter. A 'removable' stray inductance is implemented in a setup consisting of discrete SiC MOSFET units. Thus, the power loss of the transistors with and without stray inductance can be compared. Similarly slower switching speeds are also implemented to fully emulate a 62-mm module. The power loss induced by the package can thus be evaluated.

The effect of humidity on SiC Power MOSFET modules is investigated in a real application. Four modules are operated outdoor and four modules are operated indoor in identical setups, while their breakdown voltages are monitored regularly. The evolution of the leakage current, indicating humidity-induced degradation is observed.

Silicon Carbide (SiC) Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) have the potential to increase the power density in power electronics converters compared to the currently used silicon (Si). Their benefits are higher efficiency, higher switching speeds, and higher operating temperatures. Moreover, SiC MOSFETs, which are normally-off, offer the possibility to directly replace Si Isolated-Gate-BipolarTransistors (IGBTs) in already existing converter designs with minimal circuit changes. Nevertheless, as an emerging technology, the reliability performance remains to be investigated. A reliability analysis has been performed based on a full-bridge resonant converter rated at 60 kW for modern Electrostatic Precipitator (ESP) power supplies. This analysis shows that introducing SiC devices will increase the lifetime of the converter while reducing the losses. The investment costs of replacing the Si IGBTs with SiC MOSFETs can thus be covered with the reduction of the losses over the economical operational lifetime. Furthermore, a theoretical analysis on how introducing SiC MOSFETs could increase the power density of the converter while maintaining the efficiency and the reliability. Finally, an analysis on introducing redundancy as a way to improve the reliability of the system has been performed.

Commercially available Silicon Carbide (SiC) MOSFET power modules often have a design based on existing packages previously used for silicon insulated-gate bipolar transistors. However, these packages are not optimized to take advantage of the SiC benefits, such as, high switching speeds and high-temperature operation. The package of a half-bridge SiC MOSFET module has been modeled and the parasitic elements have been extracted. The model is validated through experiments. An analysis of the impact of these parasitic elements on the gate-source voltage on the chip has been performed for both low switching speeds and high switching speeds. These results reveal potential reliability issues for the gate-oxide if higher switching speeds are targeted.

Commercially available silicon carbide (SiC) MOSFET power modules often have a design based on existing packages previously used for silicon insulated-gate bipolar transistors. However, these packages are not optimized to take advantage of the SiC benefits, such as high switching speeds and high-temperature operation. The package of a half-bridge SiC MOSFET module has been modeled and the parasitic elements have been extracted. The model is validated through experiments. An analysis of the impact of these parasitic elements on the gate-source voltage on the chip has been performed for both low switching speeds and high switching speeds. These results reveal potential reliability issues for the gate oxide if higher switching speeds are targeted.

The Silicon Carbide (SiC) MOSFET is considered to be the leading candidate for future 1.7 kV and 3.3 kV switches in 2-level voltage source converters (VSC) up to 2 MW. For those converters, short circuit (SC) in the dc-link loop can occur due to a number of reasons, e.g. faulty semiconductor modules, faulty gate drivers (GDs), or electro-magnetic interference (EMI). Termination of such SCs is important in order to protect components and reduce the damage in the converter box. This paper presents a new short circuit protection scheme based on a universal current-source GD principle without dedicated hardware components. The performance of the design is evaluated for SC in the dc-link loop under load conditions, called type II and type III. Moreover, measurement results are presented using the proposed GD connected to a 1700 V 300 A SiC MOSFET tested during SC type II and III at two different dc-link stray inductances, 30 nH and 100 nH, and at two different temperatures, 25 °C and 125 °C. The conclusions are that the proposed scheme is able to terminate both SC type II and III with fast reaction time, with low energy dissipation, with a margin of about 15 times below the destructive level for dc-link voltages and load currents up to 1050 V and 300 A respectively.