A method for transferring an atomically thin layer comprising providing a target substrate and a donor substrate on which a first atomically thin layer has been formed. The method further comprises disposing an adhesion layer at the donor substrate or at the target substrate. The method further comprises bringing the target substrate and the donor substrate together. Further, the method comprises bonding together the donor substrate, the adhesion layer and the target substrate and removing the donor substrate.

The field of silicon (Si) photonic micro-electromechanical system (MEMS) for photonic integrated circuits (PICs) has evolved rapidly. Thanks to the ultra-low power consumption of Si photonic MEMS, it enables a wide range of high-performance photonic devices such as integrated optical MEMS phase shifters, tunable couplers and switches. However, photonic MEMS have suspended and movable parts which need to be protected from environmental influences, such as exposure to dust and humidity. Therefore, a packaging solution is needed for reliable operation over long periods. Here, we demonstrate wafer-level vacuum sealing of Si photonic MEMS inside cavities with ultra-thin Si caps.

The emerging fields of silicon (Si) photonic micro–electromechanical systems (MEMS) and optomechanics enable a wide range of novel high-performance photonic devices with ultra-low power consumption, such as integrated optical MEMS phase shifters, tunable couplers, switches, and optomechanical resonators. In contrast to conventional SiO2-clad Si photonics, photonic MEMS and optomechanics have suspended and movable parts that need to be protected from environmental influence and contamination during operation. Wafer-level hermetic sealing can be a cost-efficient solution, but Si photonic MEMS that are hermetically sealed inside cavities with optical and electrical feedthroughs have not been demonstrated to date, to our knowledge. Here, we demonstrate wafer-level vacuum sealing of Si photonic MEMS inside cavities with ultra-thin caps featuring optical and electrical feedthroughs that connect the photonic MEMS on the inside to optical grating couplers and electrical bond pads on the outside. We used Si photonic MEMS devices built on foundry wafers from the iSiPP50G Si photonics platform of IMEC, Belgium. Vacuum confinement inside the sealed cavities was confirmed by an observed increase of the cutoff frequency of the electro-mechanical response of the encapsulated photonic MEMS phase shifters, due to reduction of air damping. The sealing caps are extremely thin, have a small footprint, and are compatible with subsequent flip-chip bonding onto interposers or printed circuit boards. Thus, our approach for sealing of integrated Si photonic MEMS clears a significant hurdle for their application in high-performance Si photonic circuits.

Integrating two-dimensional (2D) materials into semiconductor manufacturing lines is essential to exploit their material properties in a wide range of application areas. However, current approaches are not compatible with high-volume manufacturing on wafer level. Here, we report a generic methodology for large-area integration of 2D materials by adhesive wafer bonding. Our approach avoids manual handling and uses equipment, processes, and materials that are readily available in large-scale semiconductor manufacturing lines. We demonstrate the transfer of CVD graphene from copper foils (100-mm diameter) and molybdenum disulfide (MoS2) from SiO2/Si chips (centimeter-sized) to silicon wafers (100-mm diameter). Furthermore, we stack graphene with CVD hexagonal boron nitride and MoS2 layers to heterostructures, and fabricate encapsulated field-effect graphene devices, with high carrier mobilities of up to 4520 cm2V-1s-1. Thus, our approach is suited for backend of the line integration of 2D materials on top of integrated circuits, with potential to accelerate progress in electronics, photonics, and sensing. The existing integration approaches for 2D materials often degrade material properties and are not compatible with industrial processing. Here, the authors devise an adhesive wafer bonding strategy to transfer and stack monolayers, suitable for back end of the line integration of 2D materials.

Integrating two-dimensional (2D) materials into semiconductor manufacturing lines is essential to exploit their material properties in a wide range of application areas. However, current approaches are not compatible with high-volume manufacturing on wafer level. Here, we report a generic methodology for large-area integration of 2D materials by adhesive wafer bonding. Our approach avoids manual handling and uses equipment, processes, and materials that are readily available in large-scale semiconductor manufacturing lines. We demonstrate the transfer of CVD graphene from copper foils (100-mm diameter) and molybdenum disulfide (MoS2) from SiO2/Si chips (centimeter-sized) to silicon wafers (100-mm diameter). Furthermore, we stack graphene with CVD hexagonal boron nitride and MoS2 layers to heterostructures, and fabricate encapsulated field-effect graphene devices, with high carrier mobilities of up to 4520cm2V−1s−14520cm2V−1s−1. Thus, our approach is suited for backend of the line integration of 2D materials on top of integrated circuits, with potential to accelerate progress in electronics, photonics, and sensing.

Polymer bonding employs an intermediate polymer layer as the bonding material to join the surfaces of two substrates. Polymer bonding is also extensively used for thin wafer handling, by temporarily bonding the thin wafers to handle wafers, thereby assisting grinding and etching processes and manufacturing of through-substrate vias. The bonding of wafers with an intermediate polymer layer can be performed using standard commercial wafer bonding equipment or hot presses. In localized or selective polymer wafer bonding, only predefined parts of the wafer surfaces are bonded instead of bonding the wafers with a continuous polymer layer. Wafer-to-wafer alignment requirements can range from sub-micrometer accuracy to a few tens of micrometers. The self-alignment effect of such interlocking structures can help achieve sub-µm wafer-to-wafer alignment accuracy. The chapter presents examples of suitable wafer bonding processes with two different types of polymers, which are commonly used for wafer bonding.

Silicon (Si) photonic micro-electro-mechanical systems (MEMS), with its low-power phase shifters and tunable couplers, is emerging as a promising technology for large-scale reconfigurable photonics with potential applications for example in photonic accelerators for artificial intelligence (AI) workloads. For silicon photonic MEMS devices, hermetic/vacuum packaging is crucial to the performance and longevity, and to protect the photonic devices from contamination. Here, we demonstrate a wafer-level vacuum packaging approach to hermetically seal Si photonic MEMS wafers produced in the iSiPP50G Si photonics foundry platform of IMEC. The packaging approach consists of transfer bonding and sealing the silicon photonic MEMS devices with 30 µm-thick Si caps, which were prefabricated on a 100 mm-diameter silicon-on-insulator (SOI) wafer. The packaging process achieved successful wafer-scale vacuum sealing of various photonic devices. The functionality of photonic MEMS after the hermetic/vacuum packaging was confirmed. Thus, the demonstrated thin Si cap packaging shows the possibility of a novel vacuum sealing method for MEMS integrated in standard Si photonics platforms.

We report the integration of graphene/hexagonal boron nitride (hBN) heterostructure devices on large-areas by adhesive wafer bonding, a method suitable for industrial mass-production. In this new approach, we stack graphene and hBN by two consecutive bond transfers whereby the graphene and its interface to hBN is not in contact with potentially contaminating polymers or adhesives at any time. To show the feasibility of our approach for back end of the line (BEOL) integration of two-dimensional (2D) material heterostructures on standard silicon substrates, we fabricated graphene/hBN devices with electrical bottom contacts using only established semiconductor manufacturing tools, processes and materials.

In the European project MORPHIC we develop a platform for programmable silicon photonic circuits enabled by waveguide-integrated micro-electro-mechanical systems (MEMS). MEMS can add compact, and low-power phase shifters and couplers to an established silicon photonics platform with high-speed modulators and detectors. This MEMS technology is used for a new class of programmable photonic circuits, that can be reconfigured using electronics and software, consisting of large interconnected meshes of phase shifters and couplers. MORPHIC is also developing the packaging and driver electronics interfacing schemes for such large circuits, creating a supply chain for rapid prototyping new photonic chip concepts. These will be demonstrated in different applications, such as switching, beamforming and microwave photonics.

The out-of-plane integration of microfabricated planar microchips into functional three-dimensional (3D) devices is a challenge in various emerging MEMS applications such as advanced biosensors and flow sensors. However, no conventional approach currently provides a versatile solution to vertically assemble sensitive or fragile microchips into a separate receiving substrate and to create electrical connections. In this study, we present a method to realize vertical magnetic-field-assisted assembly of discrete silicon microchips into a target receiving substrate and subsequent electrical contacting of the microchips by edge wire bonding, to create interconnections between the receiving substrate and the vertically oriented microchips. Vertical assembly is achieved by combining carefully designed microchip geometries for shape matching and striped patterns of the ferromagnetic material (nickel) on the backside of the microchips, enabling controlled vertical lifting directionality independently of the microchip's aspect ratio. To form electrical connections between the receiving substrate and a vertically assembled microchip, featuring standard metallic contact electrodes only on its frontside, an edge wire bonding process was developed to realize ball bonds on the top sidewall of the vertically placed microchip. The top sidewall features silicon trenches in correspondence to the frontside electrodes, which induce deformation of the free air balls and result in both mechanical ball bond fixation and around-the-edge metallic connections. The edge wire bonds are realized at room temperature and show minimal contact resistance (<0.2 Omega) and excellent mechanical robustness (>168mN in pull tests). In our approach, the microchips and the receiving substrate are independently manufactured using standard silicon micromachining processes and materials, with a subsequent heterogeneous integration of the components. Thus, this integration technology potentially enables emerging MEMS applications that require 3D out-of-plane assembly of microchips.