An experimental analysis of the behavior under short-circuit conditions of three different siliconcarbide (SiC) 1200-V power devices is presented. It is found that all devices take up a substantial voltage, which is favorable for detection of short circuits. A transient thermal device simulation was performed to determine the temperature stress on the die during a short-circuit event, for the SiC MOSFET. It was found that, for reliability reasons, the short-circuit time should be limited to values well below Si IGBT tolerances. Guidelines toward a rugged design for short-circuit protection (SCP) are presented with an emphasis on improving the reliability and availability of the overall system. A SiC device driver with an integrated SCP is presented for each device-type, respectively, where a shortcircuit detection is added to a conventional driver design in a simple way. The SCP driver was experimentally evaluated with a detection time of 180 ns. For all devices, short-circuit times well below 1 µs were achieved.

Silicon carbide (SiC) bipolar junction transistors (BJTs) require a continuous base current in the on-state. This base current is usually made constant and is corresponding to the maximum collector current and maximum junction temperature that is foreseen in a certain application. In this paper, a discretized proportional base driver is proposed which will reduce, for the right application, the steady-state power consumption of the base driver. The operation of the proposed base driver has been verified experimentally, driving a 1200-V/40-A SiC BJT in a dc-dc boost converter. In order to determine the potential reduction of the power consumption of the base driver, a case with a dc-dc converter in an ideal electric vehicle driving the new European drive cycle has been investigated. It is found that the steady-state power consumption of the base driver can be reduced by approximately 60%. The total reduction of the driver consumption is 3459 J during the drive cycle, which is slightly more than the total on-state losses for the SiC BJTs used in the converter.

Soft-switching converters equipped with insulated gate bipolar transistors (IGBTs) in silicon (Si) have to be dimensioned with respect to additional losses due to the dynamic conduction losses originating from the conductivity modulation lag. Replacing the IGBTs with emerging silicon carbide (SiC) transistors could reduce not only the dynamic conduction losses but also other loss components of the IGBTs. In the present paper, therefore, several types of SiC transistors are compared to a state-of-the-art 1200-V Si IGBT. First, the conduction losses with sinusoidal current at a fixed amplitude (150 A) are investigated at different frequencies up to 200 kHz. It was found that the SiC transistors showed no signs of dynamic conduction losses in the studied frequency range. Second, the SiC transistors were compared to the Si IGBT in a realistic soft-switching converter test system. Using a calorimetric approach, it was found that all SiC transistors showed loss reductions of more than 50%. In some cases loss reductions of 65% were achieved even if the chip area of the SiC transistor was only 11% of that of the Si IGBT. It was concluded that by increasing the chip area to a third of the Si IGBT, the SiC vertical trench junction field-effect transistor could yield a loss reduction of approximately 90%. The reverse conduction capability of the channel of unipolar devices is also identified to be an important property for loss reductions. A majority of the new SiC devices are challenging from a gate/base driver point-of-view. This aspect must also be taken into consideration when making new designs of soft-switching converters using new SiC transistors.

Operation of parallel-connected 4H-SiC vertical junction field effect transistors (VJFETs) from SemiSouth is modeled using numerical simulations and experimentally verified. The unbalanced current waveforms of parallel-connected VJFETs are investigated with respect to the spread in the critical parameters of the device structure and to the influence of the parasitic inductances in the measurement circuit. The device structures are reconstructed based on scanning electron microscopy (SEM) analysis, electrical characterization, and device simulations. The doping concentration and profile depth of a p-grid formed by angular implantation are studied as main contributors that influence the variation of the on-state characteristics, and the threshold voltage of the experimental devices. It has been shown elsewhere that similar differences in p-grid also lead to differences in gate-source breakdown voltage. The switching performance of the parallel-connected JFETs is measured using single and double gate drivers in a double-pulse test and compared with simulations. The switched current and voltage waveforms from measurements are reproduced in simulation by introducing the parasitics. From the analysis, it is found that reasonable differences in doping levels and profiles of the p-grid give rise to significant differences in device parameters. However, even with these parameter differences and circuit asymmetries, it is possible to successfully operate parallel-connected VJFETs of this type.

An experimental analysis of the behavior under short-circuit conditions of three different Silicon Carbide (SiC) 1200 V power devices is presented. It is found that all devices take up a substantial voltage, which is favorable for detection of short-circuits. A suitable method for short-circuit detection without any comparator is demonstrated. A SiC JFET driver with an integrated short-circuit protection (SCP) is presented where a short-circuit detection is added to a conventional driver design in a simple way. Experimental tests of the SCP driver operating under short-circuit condition and under normal operation are performed successfully.

Silicon Carbide high-power modules populated with several parallel-connected junction field-effect transistors must be driven properly. Parasitic elements could act as drawbacks in order to achieve fast and oscillation-free switching performance, which are the main goals. These two requirements are related closely to the design of the gate-drive unit, and they must be kept under certain limits when high efficiencies are targeted. This paper deeply investigates several versions of gate-drive units and proposes a dual-function gate-drive unit which is able to switch the module with an acceptable speed without letting the current suffer from significant oscillations. It is experimentally shown that turn-on and turn-off switching times of approximately 130 and 185 ns respectively can be reached, while the magnitude of the current oscillations is kept at an adequate level. Moreover, using the proposed gate driver an efficiency of approximately 99.7% is expected for a three-phase converter rated at 125 kVA and having a switching frequency of 2 kHz.

The 4H-SiC Schottky barrier diodes for high temperature operation over 200 °C have been developed using buried grids formed by implantation. Compared to a conventional JBS-type SBD with surface grid (SG), JBS-type SBD with buried grid (BG) has significantly reduced leakage current at reverse bias due to a better field shielding of the Schottky contact. By introducing the BG technology, the 1.7 kV diodes with an anode area 0.0024 cm2 (1 A) and 0.024 cm2 (10 A) were successfully fabricated, encapsulated in TO220 packages, and electrically evaluated. Two types of buried grid arrangement with different grid spacing dimensions were investigated. The measured IV characteristics were compared with simulation. The best fit was obtained with an active area of approximately 60% and 70% of the anode area in large and small devices, respectively. The measured values of the device capacitances were 1000 pF in large devices and 100 pF in small devices at zero bias. The capacitance values are proportional to the device area. The recovery behavior of big devices was measured in a double pulse tester and simulated. The recovery charge, Qc, was 18 nC and 24 nC in simulation and measurement, respectively. The fabricated BG JBS-type SBDs have a smaller maximum reverse recovery current compared to the commercial devices. No influence of the different grid spacing on the recovery charge was observed.

This paper presents the design process of a 312 kVA three-phase silicon carbide inverter using ten parallel-connected metal-oxide-semiconductor field-effect-transistor power modules in each phase-leg. The design processes of the gate-drive circuits with short-circuit protection and the power circuit layout are also presented. Electrical measurements in order to evaluate the performance of the gate-drive circuits have been performed using a double-pulse setup. Experimental results showing the electrical performance during steady-state operation of the power converter are also shown. Taking into account measured data, an efficiency of approximately 99.3% at the rated power has been estimated for the inverter.

As the chip sizes of commercially available silicon carbide power transistors will remain smaller than for silicon counterpartsin the next five to ten years, multi-chip circuit designs will be necessary in order to reach power levels exceeding10 kW. In the present paper, therefore, experiences from parallel connected discrete devices, multi-chip modules,and parallel-connected multi-chip modules are presented. It is concluded that new multi-chip circuit designs are necessaryif the high switching speeds of silicon carbide power transistors should be exploited. In the opinion of the authors,each chip must be contacted by means of individual current paths, and internal bus bars conducting the whole current ofthe module must be avoided.

This paper describes issues related to parallel connection of SiC bipolar junction transistors (BJTs) in discrete packages. The devices are applied in a high-frequency dc/dc boost converter where the switching losses significantly exceed the conduction losses. The design and construction of the converter is discussed-with special emphasis on successful parallel-operation of the discrete BJTs. All considerations are experimentally illustrated by a 6-kW, 250-kHz boost converter (300 V/600 V). A special solution for the base-drive unit, based on the dual-source driver concept, is also shown in this paper. The performance of this driver and the current sharing of the BJTs are both presented. The power losses and thermal performance of the parallel-connected transistors have been determined experimentally for different powers and switching frequencies. An efficiency of 98.23% (+/- 0.02%) was measured using a calorimetric setup, while the maximum temperature difference among the four devices is 12 degrees C.