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Publications (7 of 7) Show all publications
Aknesil, C., Dubrova, E., Lindskog, N., Sternby, J. & Englund, H. (2025). Hybrid Fingerprinting for Effective Detection of Cloned Neural Networks. In: Proceedings - 2025 IEEE 55th International Symposium on Multiple-Valued Logic, ISMVL 2025: . Paper presented at 55th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2025, Montreal, Canada, Jun 5 2025 - Jun 6 2025 (pp. 129-134). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Hybrid Fingerprinting for Effective Detection of Cloned Neural Networks
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2025 (English)In: Proceedings - 2025 IEEE 55th International Symposium on Multiple-Valued Logic, ISMVL 2025, Institute of Electrical and Electronics Engineers (IEEE) , 2025, p. 129-134Conference paper, Published paper (Refereed)
Abstract [en]

As artificial intelligence plays an increasingly important role in decision-making within critical infrastructure, ensuring the authenticity and integrity of neural networks is crucial. This paper addresses the problem of detecting cloned neural networks. We present a method for identifying clones that employs a combination of metrics from both the information and physical domains: output predictions, probability score vectors, and power traces measured from the device running the neural network during inference. We compare the effectiveness of each metric individually, as well as in combination. Our results show that the effectiveness of both the information and the physical domain metrics is excellent for a clone that is a near replica of the target neural network. Furthermore, both the physical domain metric individually and the hybrid approach outperform the information domain metrics at detecting clones whose weights were extracted with low accuracy. The presented method offers a practical solution for verifying neural network authenticity and integrity. It is particularly useful in scenarios where neural networks are at risk of model extraction attacks, such as in cloud-based machine learning services.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2025
Keywords
fingerprinting, intellectual property, model extraction, neural networks, power side channels
National Category
Communication Systems Computer Sciences
Identifiers
urn:nbn:se:kth:diva-368825 (URN)10.1109/ISMVL64713.2025.00033 (DOI)001540510800025 ()2-s2.0-105009321533 (Scopus ID)
Conference
55th IEEE International Symposium on Multiple-Valued Logic, ISMVL 2025, Montreal, Canada, Jun 5 2025 - Jun 6 2025
Note

Part of ISBN 9798331507442

QC 20250902

Available from: 2025-09-02 Created: 2025-09-02 Last updated: 2025-12-08Bibliographically approved
Aknesil, C. & Dubrova, E. (2024). Circuit Disguise: Detecting Malicious Circuits in Cloud FPGAs without IP Disclosure. In: Proceedings - 2024 27th Euromicro Conference on Digital System Design, DSD 2024: . Paper presented at 27th Euromicro Conference on Digital System Design, DSD 2024, Paris, France, Aug 28 2024 - Aug 30 2024 (pp. 361-368). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Circuit Disguise: Detecting Malicious Circuits in Cloud FPGAs without IP Disclosure
2024 (English)In: Proceedings - 2024 27th Euromicro Conference on Digital System Design, DSD 2024, Institute of Electrical and Electronics Engineers (IEEE) , 2024, p. 361-368Conference paper, Published paper (Refereed)
Abstract [en]

At present, the state-of-the-art cloud FPGA deployment process does not allow the cloud provider to perform design checks for malicious circuits unless the clients' designs are available in an unprotected form. In this paper, we introduce the circuit disguise method that allows the design checks to be performed without disclosing the clients' Intellectual Property (IP). The method is based on a lossy circuit transformation that generates a compressed version of the netlist specifying the client's design. While the design checks can still be performed on the compressed version of the netlist, reversing the transformation to recover the original design is not possible. The circuit disguise method can be used in combination with bitstream encryption. This enables the clients to protect not only the designs but also the bitstreams. Furthermore, with circuit disguise, new design checks can be performed on designs that are already compiled into a protected bitstream. We present an implementation of the circuit disguise method and demonstrate its effectiveness with various benign and malicious benchmark designs. The implementation is publicly available.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2024
Keywords
cloud security, DoS attack, FPGA, side-channel attacks, Trojans, trusted computing
National Category
Computer Sciences
Identifiers
urn:nbn:se:kth:diva-358135 (URN)10.1109/DSD64264.2024.00055 (DOI)001414927800046 ()2-s2.0-85211894946 (Scopus ID)
Conference
27th Euromicro Conference on Digital System Design, DSD 2024, Paris, France, Aug 28 2024 - Aug 30 2024
Note

Part of ISBN 979-8-3503-8038-5

QC 20250107

Available from: 2025-01-07 Created: 2025-01-07 Last updated: 2025-05-14Bibliographically approved
Aknesil, C., Dubrova, E., Lindskog, N. & Englund, H. (2023). A Near-Field EM Sensor Implemented in FPGA Configurable Fabric. In: Proceedings - 2023 IEEE 22nd International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom/BigDataSE/CSE/EUC/iSCI 2023: . Paper presented at 22nd IEEE International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom 2023, November 1-3, 2023, Exeter, United Kingdom of Great Britain and Northern Ireland (pp. 1908-1913). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>A Near-Field EM Sensor Implemented in FPGA Configurable Fabric
2023 (English)In: Proceedings - 2023 IEEE 22nd International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom/BigDataSE/CSE/EUC/iSCI 2023, Institute of Electrical and Electronics Engineers (IEEE) , 2023, p. 1908-1913Conference paper, Published paper (Refereed)
Abstract [en]

In this paper, we present the first near-field electro-magnetic (EM) sensor that is entirely implemented in the FPGA configurable fabric, without the use of any peripherals such as analog-to-digital converters, external antennas, or resistor-capacitor circuits. The sensor detects changes in path delays caused by external EM radiation using an antenna (composed of the interconnect) and a time-to-digital converter. A cloud-based FPGA remotely configured with such a sensor may act as a receiving end of a wireless covert channel, e.g., to another FPGA in the neighborhood that does not share any common resources with the receiving FPGA. Thus, our results show the plausibility of an exploitable attack vector for cloud-based FPGA that is not limited to the multi-tenancy scenario.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2023
Keywords
cloud security, covert channel, EM sensor, FPGA, time-to-digital converter
National Category
Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-348282 (URN)10.1109/TrustCom60117.2023.00259 (DOI)001239879400235 ()2-s2.0-85195460693 (Scopus ID)
Conference
22nd IEEE International Conference on Trust, Security and Privacy in Computing and Communications, TrustCom 2023, November 1-3, 2023, Exeter, United Kingdom of Great Britain and Northern Ireland
Note

Part of ISBN 979-8-3503-8200-6

QC 20241023

Available from: 2024-06-20 Created: 2024-06-20 Last updated: 2025-05-14Bibliographically approved
Aknesil, C., Dubrova, E., Lindskog, N. & Englund, H. (2023). Is your FPGA transmitting secrets: covert antennas from interconnect. In: 2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023: . Paper presented at 2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023, May 15 2023 - May 19, 2023, St. Petersburg, United States of America (pp. 79-84). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Is your FPGA transmitting secrets: covert antennas from interconnect
2023 (English)In: 2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023, Institute of Electrical and Electronics Engineers (IEEE) , 2023, p. 79-84Conference paper, Published paper (Refereed)
Abstract [en]

A hidden transmitter embedded into a chip to extract secret information is a well-known type of hardware Trojan. Various ways of implementing covert channels have been proposed in the past. The focus of this paper is covert antennas created from the FPGA interconnect. We present several on-chip antenna implementations that leverage the routing resources of FPGAs. The proposed antennas can transmit data processed by the FPGA with bit-level precision. A near-field probe is used to capture the radiated signal and the transmitted data is restored with 100% accuracy. Our results suggest that introducing a routine screening process for covert antennas in FPGA designs, similar to the one performed for ring oscillators, would be of benefit for FPGA security.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2023
Keywords
cloud security, covert antenna, FPGA, hardware Trojan, radio access networks., side-channel attacks
National Category
Telecommunications
Identifiers
urn:nbn:se:kth:diva-336743 (URN)10.1109/IPDPSW59300.2023.00025 (DOI)001055030700010 ()2-s2.0-85169292470 (Scopus ID)
Conference
2023 IEEE International Parallel and Distributed Processing Symposium Workshops, IPDPSW 2023, May 15 2023 - May 19, 2023, St. Petersburg, United States of America
Note

Part of ISBN 9798350311990

QC 20230919

Available from: 2023-09-19 Created: 2023-09-19 Last updated: 2025-05-14Bibliographically approved
Aknesil, C. & Dubrova, E. (2022). Towards Generic Power/EM Side-Channel Attacks: Memory Leakage on General-Purpose Computers. In: Proceedings of the 2022 IFIP/IEEE 30th international conference on very large scale integration (VLSI-SOC): . Paper presented at 30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), OCT 03-05, 2022, Univ Patras, Patras, GREECE. Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>Towards Generic Power/EM Side-Channel Attacks: Memory Leakage on General-Purpose Computers
2022 (English)In: Proceedings of the 2022 IFIP/IEEE 30th international conference on very large scale integration (VLSI-SOC), Institute of Electrical and Electronics Engineers (IEEE) , 2022Conference paper, Published paper (Refereed)
Abstract [en]

Today's power/EM side-channel analysis is limited by the complexity of the target hardware. We investigate the feasibility of power/EM side-channel analysis of general-purpose computers. This paper makes a step towards this goal by analyzing memory operations of Raspberry Pi 3 Model B, a widely used general-purpose IoT device that is capable of running an operating system, and shows that it is possible to extract information about the data field of memory operations from near-field EM measurements.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2022
Keywords
Side-channel attack, electromagnetic trace, memory leakage, deep learning, Raspberry Pi
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-322786 (URN)10.1109/VLSI-SoC54400.2022.9939649 (DOI)000889978800080 ()2-s2.0-85142441523 (Scopus ID)
Conference
30th IFIP/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), OCT 03-05, 2022, Univ Patras, Patras, GREECE
Note

Part of proceedings ISBN 978-1-6654-9005-4

QC 20230207

Available from: 2023-02-07 Created: 2023-02-07 Last updated: 2025-05-14Bibliographically approved
Aknesil, C. & Dubrova, E. (2021). An FPGA Implementation of 4x4 Arbiter PUF. In: 2021 IEEE 51st international symposium on multiple-valued logic (ISMVL 2021): . Paper presented at 51st IEEE International Symposium on Multiple-Valued Logic (ISMVL), MAY 25-27, 2021, ELECTR NETWORK (pp. 160-165). Institute of Electrical and Electronics Engineers (IEEE)
Open this publication in new window or tab >>An FPGA Implementation of 4x4 Arbiter PUF
2021 (English)In: 2021 IEEE 51st international symposium on multiple-valued logic (ISMVL 2021), Institute of Electrical and Electronics Engineers (IEEE) , 2021, p. 160-165Conference paper, Published paper (Refereed)
Abstract [en]

The need of protecting data and bitstreams increases in computation environments such as FPGA as a Service (FaaS). Physically Unclonable Functions (PUFs) have been proposed as a solution to this problem. In this paper, we present an implementation of Arbiter PUF with 4 x 4 switch blocks in Xilinx Series 7 FPGA, perform its statistical analysis, and compare it to other Arbiter PUF variants. We show that the presented implementation utilizes five times less area than 2 x 2 Arbiter PUF-based implementations. It is suitable for many real-world applications, including identification, authentication, key provisioning, and random number generation.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE), 2021
Series
International Symposium on Multiple-Valued Logic, ISSN 0195-623X
National Category
Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-302615 (URN)10.1109/ISMVL51352.2021.00035 (DOI)000693398200026 ()2-s2.0-85113221218 (Scopus ID)
Conference
51st IEEE International Symposium on Multiple-Valued Logic (ISMVL), MAY 25-27, 2021, ELECTR NETWORK
Note

Part of proceedings: ISBN 978-1-7281-9224-6, QC 20230117

Available from: 2021-10-05 Created: 2021-10-05 Last updated: 2025-05-14Bibliographically approved
Aknesil, C., Dubrova, E., Lindskog, N., Sternby, J. & Englund, H.Hybrid Fingerprinting for Effective Detection of Cloned Neural Networks.
Open this publication in new window or tab >>Hybrid Fingerprinting for Effective Detection of Cloned Neural Networks
Show others...
(English)Manuscript (preprint) (Other academic)
Abstract [en]

As artificial intelligence plays an increasingly important role in decision-making within critical infrastructure, ensuring the authenticity and integrity of neural networks is crucial. This paper addresses the problem of detecting cloned neural networks. We present a method for identifying clones that employs a combination of metrics from both the information and physical domains: output predictions, probability score vectors, and power traces measured from the device running the neural network during inference. We compare the effectiveness of each metric individually, as well as in combination. Our results show that the effectiveness of both the information and the physical domain metrics is excellent for a clone that is a near replica of the target neural network. Furthermore, both the physical domain metric individually and the hybrid approach outperformed the information domain metrics at detecting clones whose weights were extracted with low accuracy. The presented method offers a practical solution for verifying neural network authenticity and integrity. It is particularly useful in scenarios where neural networks are at risk of model extraction attacks, such as in cloud-based machine learning services.

Keywords
fingerprinting, neural networks, intellectual property, model extraction, power side channels
National Category
Communication Systems Other Electrical Engineering, Electronic Engineering, Information Engineering
Identifiers
urn:nbn:se:kth:diva-363339 (URN)
Funder
Vinnova, 2023-00221Swedish Civil Contingencies Agency, 2020-11632
Note

QC 20250513

Available from: 2025-05-13 Created: 2025-05-13 Last updated: 2025-05-14Bibliographically approved
Organisations
Identifiers
ORCID iD: ORCID iD iconorcid.org/0000-0002-1707-5178

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