Interoperability in HVDC systems could be supported with open upper-level control and protection (C&P) software, while hardware-near C&P functions stay black-boxed and proprietary. Methodologies like model-based systems engineering and graph theory can assist in defining the boundary between open and closed software. Most likely, partially open C&P software in HVDC is not hindered by legislation, but has to be addressed in contractual agreements. Also, a new responsibility matrix for testing is proposed.

This study analyzes the sequential failure and remaining useful life (RUL) of a multi-chip power module (MCPM) using finite element (FE) simulation, an empirical lifetime model, and recursive deconvolution. The FE model captures electro-thermal interactions, while the empirical model estimates failure probabilities from power cycling test data. The deconvolution method refines the probability density function of the first failure, providing deeper insights into degradation trends. Results show that the first die in an MCPM can fail significantly earlier than the last, with temperature imbalances contributing to this variation. Despite early failures, the system can continue operating with minor thermal impacts. These findings highlight the need for adaptive failure management and improved thermal design to enhance reliability and system life time.

This paper presents a condition monitoring approach for SiC MOSFET devices by compensating the ON-state resistance (R_dson ) to effectively detect package-related failures. While R_dsON is a promising health indicator, its strong dependence on junction temperature (T_j) and threshold voltage (V_th ) can obscure degradation signals. This study proposes compensation techniques to mitigate the influence of T_j and V_th  drift, enabling reliable monitoring. The methodology is validated using a custom-designed power cycling test bench, in compliance with AQG-324, to stress SiC MOSFETs under controlled thermal conditions. Two R_dson drift compensation methods are compared to analyze the evolution of compensated R_dSON: a moving polynomial fit (Method 1) and a derivative-based technique with post-filtering (Method 2). Results show that both methods can differentiate between linear (die-level degradation) and non-linear (package-related failure) regions of R_dsON  drift. However, Method 1 provides more stable estimates with lower noise, especially for smaller window sizes. The findings support the use of compensated R_dSON as a practical and robust condition monitoring parameter for SiC MOSFET reliability assessment.

Interconnecting power converters (IPCs) are the main elements enabling the interconnection of multiple high-voltage alternating current (HVac) and high-voltage direct current (HVdc) subgrids. To ensure stable operation of the resulting hybrid ac/dc systems, grid-following (GFL) and grid-forming (GFM) controls need to be carefully assigned to individual IPC terminals when using common IPC controls. In contrast, dual-port GFM control imposes a stable voltage on the ac and dc terminals and can be deployed on all IPCs regardless of the network configuration. In this work, we use hybrid ac/dc admittance models, eigenvalue sensitivities, and case studies to analyze and quantify the underlying properties of ac-GFM control, ac-GFL, and dual-port GFM control. Compared to common ac-GFM and ac-GFL controls, dual-port GFM control: 1) renders IPCs dissipative over a much wider range of frequencies and operating points; 2) significantly reduces the sensitivity of IPC small-signal dynamics to operating point changes; and 3) exhibits an improved dynamic response to severe contingencies. Finally, the results are illustrated and validated in an experimental scaled-down point-to-point HVdc system.

Grid-forming converters can emulate the behavior of a synchronous generator through frequency droop control. The stability of grid-forming modular multilevel converters can be studied via the impedance-based stability criterion. This paper presents an ac-side impedance model of a grid-forming modular multilevel converter which includes a complete grid-forming control structure. The impact of different control schemes and parameters on the closed-loop output impedance of the converter is thoroughly analyzed and the learnings have been used in mitigating undesired control interactions with the grid. The results are verified through simulations in time- and frequency-domains along with experiments on a down-scaled laboratory prototype.

Double-sided cooled (DSC) power semiconductor modules have garnered increased interest over the past decade due to their ability to offer an additional path for heat removal, facilitating higher power density operation while reducing junction temperatures and thermal stresses. Nevertheless, when operating at similar junction temperatures, DSC modules might exhibit elevated thermo-mechanical stress compared to single-sided cooled (SSC) modules. This increase can be attributed to restricted vertical movement within the DSC modules. Furthermore, the integration of various spacers within the DSC modules, which enable bond wire connections to gate terminals, can significantly influence both the thermal performance and induced thermo-mechanical stresses. Depending on the materials used in the spacer, the thermal performance and thermo-mechanical stresses inside the module can vary. In this study, we have first analysed the thermal performance of the DSC power modules employing different spacers. Following that, we have also performed thermo-mechanical analysis in different solder layers. Finally, fatigue analysis is done to demonstrate the weakest solder layer inside the package.

Accurate estimation of losses in high-power traction converters is essential for an effective design. Precise estimation of switching and conduction losses is crucial for this purpose. In this paper, the widely recognized Double Pulse Test (DPT) is employed to determine these losses. However, time-shift errors and misalignments in measurements can lead to significant deviations in loss estimation of the actual setup. This paper introduces a postprocessing method aimed at mitigating time-shift and misalignment issues in voltage and current waveforms. The proposed method is validated through simulation, demonstrating its effectiveness in improving the accuracy of loss estimation for high-power traction converters.

This paper evaluates traction inverters for heavy-duty electric vehicles, focusing on key criteria such as raised power ratings with improved efficiency and power densities. Boosted voltage and current levels are required to achieve higher power levels and provide megawatt charging system solutions, which results in the need to utilize new semiconductors and topologies. In this study, 3-Level neutral point clamped (3L- NPC) and 2-Level 6-phase (2L-6Ph) voltage source inverters (VSIs) are evaluated and compared to conventional 2-Level 3-phase (2L-3Ph). The comparison uses figure-of-merit parameters and a virtual prototyping method based on several performance indices, such as efficiency, power density, output harmonic quality, and reliability. Then, efficiency maps are acquired to find out the sweet operating points, minimizing losses. Results show that the 3L-NPC VSI system provides a higher switching frequency, which also shrinks the size of the passive elements and cooling system. Although the 3L-NPC inverter requires additional power switches and isolated gate drivers, its estimated performance outweighs such reliability and cost-dependent issues. Therefore, this study concludes that multi-level inverter topologies hold promise for high-voltage, high-power traction drives.

The semiconductor industry plays a critical role in numerous sectors, yet faces vulnerability in its supply chains. The recent global semiconductor shortage highlighted the risks of relying on a single supplier. To mitigate this, companies adopt dualsourcing strategies, but power devices like silicon carbide (SiC) metal-oxide semiconductor field-effect transistors (MOSFETs) pose challenges due to manufacturing nuances. Configurable gate-drive units (GDUs) offer flexibility but often require external input for device recognition. This paper introduces a method to achieve a self-configurable gate-drive unit based on measuring the gate step-response for power device identification. The proposed method enhances safety, ensures seamless integration, and offers adaptability in full-bridge or multi-phase systems. Experimental results demonstrate component uniformity, emphasize the importance of interval selection, and showcase the impact of external gate resistors on rise and fall times. Estimations of input capacitance using different methods highlight their effectiveness in distinguishing among devices. The practical implementation of the proposed method contributes to the efficiency, reliability, and cost-effectiveness of self-configurable GDUs.

Silicon carbide (SiC)-based metal-oxide-semiconductor field-effect transistors (MOSFETs) hold promising application prospects in future high-capacity high-power converters due to their excellent electrothermal characteristics. However, as nascent power electronic devices, their long-term operational reliability lacks sufficient field data. The power cycling test is an important experimental method to assess packaging-related reliability. In order to obtain data closest to actual working conditions, forward power cycling is utilized to carry out SiC MOSFET degradation experiments. Due to the wide bandgap characteristics of SiC MOSFETs, the short-term drift of the threshold voltage is much more serious than that of silicon (Si)-based devices. Therefore, an offline threshold voltage measurement circuit is implemented during power cycling tests to minimize errors arising from this short-term drift. Different characterizations are performed based on power cycling tests, focused on measuring the on-state resistance, thermal impedance, and threshold voltage of the devices. The findings reveal that the primary failure mode under forward power cycling tests, with a maximum junction temperature of 130 degrees C, is bond-wire degradation. Conversely, the solder layer and gate oxide exhibit minimal degradation tendencies under these conditions.