Silicon carbide (SiC)-based metal-oxide-semiconductor field-effect transistors (MOSFETs) hold promising application prospects in future high-capacity high-power converters due to their excellent electrothermal characteristics. However, as nascent power electronic devices, their long-term operational reliability lacks sufficient field data. The power cycling test is an important experimental method to assess packaging-related reliability. In order to obtain data closest to actual working conditions, forward power cycling is utilized to carry out SiC MOSFET degradation experiments. Due to the wide bandgap characteristics of SiC MOSFETs, the short-term drift of the threshold voltage is much more serious than that of silicon (Si)-based devices. Therefore, an offline threshold voltage measurement circuit is implemented during power cycling tests to minimize errors arising from this short-term drift. Different characterizations are performed based on power cycling tests, focused on measuring the on-state resistance, thermal impedance, and threshold voltage of the devices. The findings reveal that the primary failure mode under forward power cycling tests, with a maximum junction temperature of 130 degrees C, is bond-wire degradation. Conversely, the solder layer and gate oxide exhibit minimal degradation tendencies under these conditions.

This paper investigates the use of ON-state resistance (R_dsON) as a health monitoring indicator for diagnosing package-related degradation in silicon carbide (SiC) MOSFET devices. While R_dsON is a widely recognized aging precursor, its application in SiC MOSFETs is challenging due to its strong dependence on junction temperature (T_j) and threshold voltage (V_th) drift during power cycling. To address these challenges, this work introduces compensation techniques that eliminate the influence of T_j variations and Vth drift in R_dsON. The proposed methods are validated through active power cycling tests on TO-247-3 packaged SiC MOSFETs, with experimental results showing that the compensated R_dsON provides a stable and reliable health indicator. In addition, slope-based Vth drift compensation methods, including moving average filtering and recursive least squares (RLS) estimation, are evaluated for detecting package-related degradation. Failure analysis using scanning acoustic microscopy (SAM) and scanning electron microscopy (SEM) confirms the correlation between compensated R_dsON signatures and bondwire/solder degradation. The proposed method therefore enables reliable health monitoring of SiC MOSFET devices using R_dsON.

This paper presents an early-stage bond wire failure detection method for SiC MOSFET devices subjected to active power cycling. Bond-wire degradation, including lift-off and heel cracking, is among the most critical and prevalent package-level failure mechanisms in SiC devices. However, the initial stages of such degradation typically cause only small increases in ON-state resistance (R_dsON), making early detection challenging. The proposed method first compensates for the temperature-dependent variations in R_dsON by using a second-order polynomial fit function derived from junction temperature (T_j) measurements obtained via a temperature-sensitive electrical parameter. The temperature-compensated R_dsON is then analyzed using a Recursive Least Squares (RLS) estimator that tracks changes in its slope. Sudden slope spikes are shown to correlate strongly with individual bond wire failure events. Experimental results from power cycling three TO-247-3 packaged SiC MOSFET devices show that the proposed method is capable of detecting bond wire failures at an earlier stage and with improved distinction compared to conventional R_dsON-based monitoring methods.

Body-diode voltage drop has been identified as a reliable parameter for both as a temperature-sensitive electrical parameter (TSEP) to estimate the SiC MOSFET junction temperature and as a failure precursor to identify any package related degradation. However, in the inverse-mode power-cycling test (PCT), it is found that the body-diode voltage drop changes at a fixed temperature. It is known from the previous research that the increase in a body-diode voltage drop at heating current acts as a failure precursor, indicating package related degradation. However, the change in the voltage drop at a low measurement current, due to degradation, is not well investigated. This study aims to analyse how the body-diode voltage drop at low current changes in TO-247 packaged SiC MOSFETs during inverse and forward-mode PCT. 

Solder layers, used as bonding material inside the power module to attach the semiconductor die on Direct Bond Copper (DBC) substrate and DBC substrate on baseplate, are one of the regions most prone to failure. The failure usually occurs in the form of solder cracks and depends on various operating conditions, such as-maximum temperature, temperature swing, and heating time. The cracks generated inside the solder layers can eventually result in its delamination. Power modules are usually power cycled to estimate the failure sites and mechanisms. However, the failure mechanisms can vary depending on the frequency, amplitude, and range of the temperature in the Power Cycling Tests (PCT). In this study, we have used the Finite Element Method (FEM) in COMSOL Multiphysics to analyse the impact of the PCT on both die attach, and baseplate attach solder layers. Additionally, the effect of the degree of asymmetry in the die position on the reliability of both the solder layers are analysed. The FEA (Finite Element Analysis) results are analysed to have a better understanding about the aspects impacting the lifetime of the power module.

Commercialization of SiC MOSFETs and electrification of the automotive sector has resulted in the accelerated development of power semiconductor devices. To take the most advantage of the SiC properties and make the power semiconductor modules automotive graded, the power module packaging technologies are developing at a rapid pace. New materials are being introduced and more innovative ways are being investigated to operate the SiC die at high temperatures while maintaining high reliability. Silver (Ag) sinter, due to its superior properties, has been introduced as a state-of-the-art die-attaching technology, while different ways are being investigated to either eliminate the aluminium (Al) bondwires or replace them with copper (Cu) counterparts. In this study, we will use the Finite Element (FE) method to investigate the impact of different packaging aspects like using copper foil and Ag sinter on thermal and mechanical performance of the power module. We will also investigate the effect of different packaging on power module reliability.

Double-sided cooled (DSC) power semiconductor modules have garnered increased interest over the past decade due to their ability to offer an additional path for heat removal, facilitating higher power density operation while reducing junction temperatures and thermal stresses. Nevertheless, when operating at similar junction temperatures, DSC modules might exhibit elevated thermo-mechanical stress compared to single-sided cooled (SSC) modules. This increase can be attributed to restricted vertical movement within the DSC modules. Furthermore, the integration of various spacers within the DSC modules, which enable bond wire connections to gate terminals, can significantly influence both the thermal performance and induced thermo-mechanical stresses. Depending on the materials used in the spacer, the thermal performance and thermo-mechanical stresses inside the module can vary. In this study, we have first analysed the thermal performance of the DSC power modules employing different spacers. Following that, we have also performed thermo-mechanical analysis in different solder layers. Finally, fatigue analysis is done to demonstrate the weakest solder layer inside the package.

This paper presents a condition monitoring approach for SiC MOSFET devices by compensating the ON-state resistance (R_dson ) to effectively detect package-related failures. While R_dsON is a promising health indicator, its strong dependence on junction temperature (T_j) and threshold voltage (V_th ) can obscure degradation signals. This study proposes compensation techniques to mitigate the influence of T_j and V_th  drift, enabling reliable monitoring. The methodology is validated using a custom-designed power cycling test bench, in compliance with AQG-324, to stress SiC MOSFETs under controlled thermal conditions. Two R_dson drift compensation methods are compared to analyze the evolution of compensated R_dSON: a moving polynomial fit (Method 1) and a derivative-based technique with post-filtering (Method 2). Results show that both methods can differentiate between linear (die-level degradation) and non-linear (package-related failure) regions of R_dsON  drift. However, Method 1 provides more stable estimates with lower noise, especially for smaller window sizes. The findings support the use of compensated R_dSON as a practical and robust condition monitoring parameter for SiC MOSFET reliability assessment.