With the increase in penetration of power electronic converters in the power systems, a demand for overcurrent/ overloading capability has risen for the fault clearance duration. This article gives an overview of the limiting factors and the recent technologies for the overcurrent performance of SiC power modules in power electronics converters. It presents the limitations produced at the power module level by packaging materials, which include semiconductor chips, substrates, metallization, bonding techniques, die attach, and encapsulation materials. Specifically, technologies for overcurrent related temperatures in excess of 200 degrees C are discussed. This article also discusses potential technologies, which have been proven or may be potential candidates for improving the safe operating area. The discussed technologies are use of phase-change materials below the semiconductor chip, Peltier elements, new layouts of the power modules, control and modulation techniques for converters. Special attention has been given to an overview of various potential phase-change materials, which can be considered for high-temperature operations.

Unsymmetrical faults in the power system typically last for approximately 200 ms until the circuit breakers clear the faults. Hence, it is important to ensure that power semiconductors in converters do not fail due to the associated increased current. This is possible if the heat generated in the SiC device due to over-currents (OCs) is removed as soon as possible. Various materials such as metals (copper, aluminum, nickel, silver and gold), diamond, graphite and phase change materials for removing the heat just below/above the semiconductor have been considered in this paper. The calculations and COMSOL simulations have been performed assuming a heat pulse on one side of the material and adiabatic conditions on the other side. This assumption is valid for short pulses as the components further away would take more time to absorb heat. It has been concluded that the higher thermal conductivity, the faster is the removal of the heat from the semiconductor. Because of this, metals, diamond and graphite have been proven to be more effective in heat removal and keeping the temperature below 250°C during OCs for the heat pulse of 400 W/cm2 for 200 ms. The concept of sensible height and limitations of the use of the materials is also discussed. There is a limit to the reduction of junction temperature by adding and increasing the amount of material above the chip. After this limit, the further reduction of junction temperature is not possible, even by increasing the amount of material. This limit reached is different for different materials.

The fault clearance time in the power system can vary from a few milliseconds to a few hundred milliseconds. Power electronics converters should be able to provide the increased current during faults without failing due to thermal limits. Hence, the heat generated in the semiconductor chip due to the over-current (OC) should be removed as soon as it is generated. In this paper, cooling by heat-absorbing material has been investigated on the top, bottom, and top + bottom of the SiC MOSFET chip using COMSOL simulations for OCs. The heat-absorbing materials considered in the paper are copper, graphite, and aluminum. The maximum allowed chip temperature is assumed to be 250 ˆC since SiC devices do not fail in this range of temperature. It is concluded that the cooling on the top of the chip has the best performance among the three arrangements discussed in the paper in terms of OC duration and steady-state temperature. Another conclusion is that copper has the best performance due to higher thermal capacity for the same volume of the heat-absorbing material.

An increasing share of fluctuating and intermittent renewable energy sources can cause over-currents (OCs) in the power system. The heat generated during OCs increases the junction temperature of semiconductor devices and could even lead to thermal runaway if thermal limits are reached. In order to keep the junction temperature within the thermal limit of the semiconductor, the power module structure with heat-absorbing material below the chip is investigated through COMSOL Multiphysics simulations. The upper limits of the junction temperature for Silicon (Si) and Silicon Carbide (SiC) are assumed to be 175 and 250 ∘∘C, respectively. The heat-absorbing materials considered for analysis are a copper block and a copper block with phase change materials (PCMs). Two times, three times, and four times of OCs would be discussed for durations of a few hundred milliseconds and seconds. This article also discusses the thermal performance of a copper block and a copper block with PCMs. PCMs used for Si and SiC are LM108 and Lithium, respectively. It is concluded that the copper block just below the semiconductor chip would enable OC capability in Si and SiC devices and would be more convenient to manufacture as compared to the copper block with PCM.

An increasing share of fluctuating and intermittent renewable energy sources can cause over-currents (OCs) in the power system. The heat generated during OCs increases the junction temperature of semiconductor devices and could even lead to thermal runaway if thermal limits are reached. In order to keep the junction temperature within the thermal limit of the semiconductor, the power module structure with heat-absorbing material below the chip is investigated through COMSOL Multiphysics simulations. The upper limits of the junction temperature for Silicon (Si) and Silicon Carbide (SiC) are assumed to be 175 and 250 ∘∘C, respectively. The heat-absorbing materials considered for analysis are a copper block and a copper block with phase change materials (PCMs). Two times, three times, and four times of OCs would be discussed for durations of a few hundred milliseconds and seconds. This article also discusses the thermal performance of a copper block and a copper block with PCMs. PCMs used for Si and SiC are LM108 and Lithium, respectively. It is concluded that the copper block just below the semiconductor chip would enable OC capability in Si and SiC devices and would be more convenient to manufacture as compared to the copper block with PCM.

Fault clearance time in the power system with renewables generally varies from 0.5-10 cycles (10-667 ms for 50 Hz). Power electronic converters should be able to provide an increased current without exceeding the thermal limits during faults. Accordingly, the heat generated in the semiconductor chip during over-current (OCs) should be removed from the chip as soon as it is generated. In this paper, microchannel (MC) cooling has been investigated through COMSOL simulations for OCs with SiC MOSFETs. The upper limit of the chip temperature has been assumed to be 250 °C as SiC devices do not fail in this temperature range. The duration of OCs is from a few tens of milliseconds to a few seconds. It is concluded that MC cooling has the potential to increase the duration of OC without reaching the assumed upper limit of the temperature.

The typical fault clearance time in an AC grid is approximately 200 ms. Grid-connected power converters should be able to deliver increased currents during this time. This paper investigates the over-current (OC) capability using microchannel (MC) cooling below the chip using COMSOL simulations with SiC MOSFETs. The paper also compares thermal performance of MCs above and below the chip. The maximum allowable chip temperature is assumed to be 250 °C since SiC devices do not fail up to this temperature if the package is adapted for such operation. OC durations is from a few milliseconds to a few seconds. It is concluded that MC cooling below the chip can potentially increase the OC capability. However, the OC capability is significantly superior when MC cooling is applied on top of chip.

Over-currents (OCs) in the power system could be caused by fluctuations in the load, bus voltage, etc. In this article, TO-247 MOSFETs have been stressed for over-currents with a pulse duration of approximately 1 ms for two times OCs (2 OCs) to five times OCs (5 OCs). The junction temperature has been estimated and the failure modes are discussed. It has been observed that the devices do not show degraded behavior (change in on-state resistance and threshold voltage) for 100 cycles until 4.5 OCs. The devices failed anywhere between the first cycle to seven cycles for 4.8 OC and the devices always failed in the first cycle for 5 OCs. This observation gives an estimation of the limit of stressing the devices for short pulses of a few milliseconds.

With the increase in high-voltage direct current (HVDC) systems, the need for power flow controllers (PFCs) has been identified recently to avoid overloads in the cables. An interline PFC has gained attention because of no need for an external power source. The paper presents an analysis to decide the best location in terms of the maximum current variation. A particular case study of a 3-terminal HVDC system has been presented with PFCs at different nodes. The analysis uses a PFC which has been tested experimentally in previous work. Simulations are performed using the PLECS software to extend the studies further for wider applications and make a well-informed choice about the location of PFCs. It is concluded that the maximum current variation is possible when the PFC is applied at the slack node (the node with fixed voltage)