kth.sePublications KTH
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
IncineRate: Multi-Modal FPGA Accelerator Architecture for SCNNs
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0009-0007-3374-4355
KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Software and Computer systems, SCS.ORCID iD: 0000-0001-5452-6794
2025 (English)In: Proceedings - 2025 IEEE 18th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2025, Institute of Electrical and Electronics Engineers (IEEE) , 2025, p. 165-172Conference paper, Published paper (Refereed)
Abstract [en]

Spiking Neural Networks (SNNs) are a promising alternative to conventional Artificial Neural Networks (ANNs) due to their biological interpretability and capability to exploit sparse computation. Specialized hardware for SNNs has potential advantages over general-purpose devices in terms of power and performance. However, the computational requirements of modern Spiking Convolutional Neural Networks (SCNNs) renders most SNN hardware inefficient for SCNN acceleration. As a step towards efficient SCNN acceleration, we present IncineRate, a flexible FPGA-based SCNN accelerator architecture. IncineRate has built-in support for many SCNNs, such as AlexNet, VGG16, and ResNets, and can be extended to support other network models. The number of simulation time steps, the network architecture, and other settings are specified at run time, so an already deployed device can execute multiple networks without reconfiguration. Our results show that IncineRate achieves state-of-the-art classification accuracy among FPGA-based SCNNs on CIFAR10 and CIFAR100.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2025. p. 165-172
Keywords [en]
computer vision, fpga, neuromorphic architecture, reconfigurable hardware, scnn
National Category
Computer Engineering
Identifiers
URN: urn:nbn:se:kth:diva-378751DOI: 10.1109/MCSoC67473.2025.00035Scopus ID: 2-s2.0-105032437580OAI: oai:DiVA.org:kth-378751DiVA, id: diva2:2049951
Conference
18th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, MCSoC 2025, Singapore, Singapore, December 15-18, 2025
Note

Part of ISBN 9798331565718

QC 20260331

Available from: 2026-03-31 Created: 2026-03-31 Last updated: 2026-03-31Bibliographically approved

Open Access in DiVA

No full text in DiVA

Other links

Publisher's full textScopus

Authority records

Lindqvist, Björn A.Podobas, Artur

Search in DiVA

By author/editor
Lindqvist, Björn A.Podobas, Artur
By organisation
Electronics and Embedded systemsSoftware and Computer systems, SCS
Computer Engineering

Search outside of DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 13 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf