Soft-switching converters equipped with insulated gate bipolar transistors (IGBTs) in silicon (Si) have to be dimensioned with respect to additional losses due to the dynamic conduction losses originating from the conductivity modulation lag. Replacing the IGBTs with emerging silicon carbide (SiC) transistors could reduce not only the dynamic conduction losses but also other loss components of the IGBTs. In the present paper, therefore, several types of SiC transistors are compared to a state-of-the-art 1200-V Si IGBT. First, the conduction losses with sinusoidal current at a fixed amplitude (150 A) are investigated at different frequencies up to 200 kHz. It was found that the SiC transistors showed no signs of dynamic conduction losses in the studied frequency range. Second, the SiC transistors were compared to the Si IGBT in a realistic soft-switching converter test system. Using a calorimetric approach, it was found that all SiC transistors showed loss reductions of more than 50%. In some cases loss reductions of 65% were achieved even if the chip area of the SiC transistor was only 11% of that of the Si IGBT. It was concluded that by increasing the chip area to a third of the Si IGBT, the SiC vertical trench junction field-effect transistor could yield a loss reduction of approximately 90%. The reverse conduction capability of the channel of unipolar devices is also identified to be an important property for loss reductions. A majority of the new SiC devices are challenging from a gate/base driver point-of-view. This aspect must also be taken into consideration when making new designs of soft-switching converters using new SiC transistors.

This paper studies the possibility of building a modular multilevel converter (M2C) using silicon carbide (SiC) switches. The main focus is on a theoretical investigation of the conduction losses of such a converter and a comparison to a corresponding converter with silicon-insulated gate bipolar transistors. Both SiC BJTs and JFETs are considered and compared in order to choose the most suitable technology. One of the submodules of a down-scaled 3 kVA prototype M2C is replaced with a submodule with SiC JFETs without antiparallel diodes. It is shown that the diode-less operation is possible with the JFETs conducting in the negative direction, leaving the possibility to use the body diode during the switching transients. Experimental waveforms for the SiC submodule verify the feasibility during normal steady-state operation. The loss estimation shows that a 300 MW M2C for high-voltage direct current transmission would potentially have an efficiency of approximately 99.8% if equipped with future 3.3 kV 1.2 kA SiC JFETs.

An experimental performance comparison between SiC JFET and SiC BJT switches which are used as the main switch for a 2 kW dc/dc converter is presented. In order to perform a fair comparison and due to the different chip areas of these two SiC devices, they both operate under the same on-state losses. Moreover, the switching speeds of the gate and base drivers are approximately equal. It is experimentally shown that the SiC BJT is switching slightly faster than the SiC JFET under the same circuit conditions, while the driver loss for the SiC BJT is higher than for the JFET, especially at relatively low switching frequencies. Various experimental results dealing with the switching performance of the SiC devices and the power losses at different switching frequencies are presented. It is found that the BJT converter has a higher efficiency (99.0% measured at 50 kHz) that the JFET converter.

State-of-the-art silicon carbide switches have current ratings that are not sufficiently high to be used in high-power converters. It is, therefore, necessary to connect several switches in parallel in order to reach sufficient current capabilities. An investigation of parallel-connected normally ON silicon carbide JFETs is presented in this paper. The device parameters that play the most important role for the parallel connection are the pinch-off voltage, the gate-source reverse breakdown voltage, the spread in the on-state resistances, and the variations in static transfer characteristics of the devices. Moreover, it is experimentally shown that a fifth factor affecting the parallel connection of the devices is the parasitic inductances of the circuit layout. The temperature dependence of the gate-source reverse breakdown voltages is analyzed for two different designs of silicon carbide JFETs. If the spread in the pinch-off and gate-source reverse breakdown voltages is sufficiently large, there might be no possibility for a stable off-state operation of a pair of transistors without forcing one of the gate voltages to exceed the breakdown voltage. A solution to this problem using individual gate circuits for the JFETs is given. The switching performance of two pairs of parallel-connected devices with different combinations of parameters is compared employing two different gate-driver configurations. Three different circuit layouts are considered and the effect of the parasitic inductances is experimentally investigated. It is found that using a single gate circuit for the two mismatched JFETs may improve the switching performance and therefore the distribution of the switching losses significantly. Based on the measured switching losses, it is also clear that regardless of the design of the gate drivers, the lowest total switching losses for the devices are obtained when they are symmetrically placed.

Considering the present development of the available Silicon Carbide switches, their current ratings are so low that they cannot be used for high-power converters. It is therefore necessary to connect several switches in parallel in order to obtain sufficient current ratings. An investigation of parallel-connected normally-on Silicon Carbide Junction Field Effect Transistors is presented in this paper. The parameters that play the most important role for the parallel connection are the pinch-off and the gate-source breakdown voltages. The temperature dependency of those two voltages is analyzed based on the pnp structure of the device. If the spread in these parameters is sufficiently large there might be no possibility for a stable off-state operation of a pair of transistors without forcing one of the gate voltages to exceed the breakdown voltage, especially at high temperatures. A solution to this problem is given. The switching performance of two pairs of parallel-connected devices is compared with respect to their pinch-off voltages, and it is found that differences of approximately 25% in switching losses could result from a difference in the pinch-off voltage of 0.5 V.

Due to the low current ratings of the currently available silicon carbide (SiC) switches they cannot be employed in high-power converters. Thus, it is necessary to parallel-connect several switches in order to reach higher current ratings. This paper presents an investigation of parallel-connected normally-on SiC junction field effect transistors. There are four crucial parameters affecting the effectiveness of the parallel-connected switches. However, the pinch-off voltage and the reverse breakdown voltage of the gates seem to be the most important parameters which affect the switching performance of the devices. In particular, the spread in these two parameters might affect the stable off-state operation of the switches. The switching performance and the switching losses of a pair of parallel-connected devices having different reverse breakdown voltages of the gates is investigated by employing three different gate-driver configurations. It is experimentally shown that using a single gate-driver circuit the switching performance of the parallel-connected devices is almost identical, while the total switching losses are lower compared to the other two configurations.

The very low on-state resistance, the voltage-controlled gate, and the relative simplicity of fabrication of the normally ON silicon carbide junction field-effect transistor (JFET) make this device the most important player among all state-of-the-art silicon carbide transistors. However, the normally ON nature counts as the main factor which keeps this device far from being considered as an alternative to the silicon insulated-gate bipolar transistor. A self-powered gate driver without external power supply for normally ON silicon carbide JFETs is presented in this paper. The proposed circuit is able to handle the short-circuit currents when the devices are subjected to the dc-link voltage by utilizing the energy associated with this current. On the other hand, it supplies the necessary negative gate-source voltage during the steady-state operation. A detailed description of the operating states in conjunction with a theoretical analysis of the proposed self-powered gate driver is presented. The first part of the experimental investigation has been performed when the proposed circuit is connected to a device which is directly subjected to the dc-link voltage. The second set of measurements were recorded when the self-powered gate-driver was employed as the driver of normally ON components in a half-bridge converter. From the experimental results, it is shown that the short-circuit current is cleared within approximately 20μs after the dc-link voltage is applied, while the power consumption when all devices are kept in the OFF state equals 0.37W. Moreover, it is experimentally shown that the proposed gate driver can properly switch when it is employed in a half-bridge converter. Finally, limitations regarding the range of the applications where the self-powered gate drive can efficiently operate are also discussed.

This paper describes the concept, design, construction, and experimental investigation of a 40-kVA inverter with silicon carbide junction field-effect transistors (JFETs). The inverter was designed to reach an efficiency exceeding 99.5%. The size of the heat sink is significantly reduced in comparison to silicon insulated-gate bipolar transistor designs, and the high efficiency makes it possible to use free-convection cooling. This could potentially increase reliability compared with solutions with fans. A very low conduction loss has been achieved by parallel connecting ten 85-m Omega normally-ON JFETs in each switch position. A special gate-drive solution was applied, forcing the transistors to switch very fast (approximately 10 kV/mu s), resulting in very low switching losses. As output power is almost equal to input power, special effort was done to precisely determine the amount of semiconductor power losses via comparative thermal measurements. A detailed analysis of the measurements shows that the efficiency of the inverter is close to 99.7% at 40 kVA.