The self-aligned silicide (salicide) process, where a metallic silicide is formed without lithographic definition to both source/drain-regions and the gate, is important for devices thanks to its ability to minimize parasitic resistances in scaled silicon CMOS technology. The challenge to transfer the process to SiC technology is two-fold: a single silicide has to give low resistance contacts to both ion implanted p-type and n-type simultaneously, and the typical temperatures required to form contacts to SiC is high enough that silicide agglomerates on polysilicon. In this work, we investigated if there exists a process window for salicide process for the purpose of developing a salicide process for SiC CMOS. Transfer length method structures were fabricated by ion implantation of phosphorus and aluminum to investigate simultaneous contacts to SiC. Bridge resistor structures (2μm width) were fabricated both with and without silicide-block to determine the silicide stability on highly in-situ doped polysilicon. The approach is design of experiment with multiple factors, including silicide composition, annealing temperature, deposited metal thickness and annealing time. The formation of self-aligned low resistive contacts to both n-type and p-type SiC was successful. The mutual process window for the co-existence of stable silicide on polysilicon and low resistive contacts to SiC, which is required for true salicide process, could not be found.