kth.sePublications KTH
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Activation in Network for NoC-Based Deep Neural Network Accelerator
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0002-4911-0257
KTH Royal Institute of Technology, Department of Electrical Engineering, Stockholm, Sweden.ORCID iD: 0000-0001-8488-3506
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0003-0061-3475
2024 (English)In: 2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024 - Proceedings, Institute of Electrical and Electronics Engineers (IEEE) , 2024Conference paper, Published paper (Refereed)
Abstract [en]

Network-on-Chip (NoC) based Deep Neural Net-work (DNN) accelerators are widely adopted, but their performance is still not satisfactory as the network congestion may enlarge the inference latency. In this work, we leverage the idea of in-network processing and propose a computation-while-blocking method to conduct activation in network that improves inference latency for NoC-based DNN accelerators. Our approach offloads the non-linear activation from processing elements (PEs) to network routers. Based on a cycle-accurate NoC-DNN simulator, we experiment on a popular neural network model LeNet. The proposed approach can achieve up to 12% speedup in the first layer, and an overall around 6% decrease in total cycles compared to the baseline.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2024.
Keywords [en]
Deep neural networks, DNN accelerator, In-network processing, Network-on-Chip
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:kth:diva-349914DOI: 10.1109/VLSITSA60681.2024.10546384ISI: 001253001400044Scopus ID: 2-s2.0-85196721436OAI: oai:DiVA.org:kth-349914DiVA, id: diva2:1881692
Conference
2024 International VLSI Symposium on Technology, Systems and Applications, VLSI TSA 2024, Hsinchu, Taiwan, Apr 22 2024 - Apr 25 2024
Note

QC 20240704

Part of ISBN 979-8-3503-6034-9

Available from: 2024-07-03 Created: 2024-07-03 Last updated: 2024-09-03Bibliographically approved

Open Access in DiVA

No full text in DiVA

Other links

Publisher's full textScopus

Authority records

Zhu, WenyaoChen, YizhiLu, Zhonghai

Search in DiVA

By author/editor
Zhu, WenyaoChen, YizhiLu, Zhonghai
By organisation
Electronics and Embedded systems
Computer Systems

Search outside of DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 877 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf