kth.sePublications KTH
Change search
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf
Multi-level Memory-Centric Profiling on ARM Processors with ARM SPE
KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Computational Science and Technology (CST).
KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Computational Science and Technology (CST).
Lawrence Livermore National Laboratory, Livermore, USA.
KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science, Computational Science and Technology (CST).ORCID iD: 0000-0003-1669-7714
Show others and affiliations
2024 (English)In: Proceedings of SC 2024-W: Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis, Institute of Electrical and Electronics Engineers (IEEE) , 2024, p. 996-1005Conference paper, Published paper (Refereed)
Abstract [en]

High-end ARM processors are emerging in data centers and HPC systems, posing as a strong contender to x86 machines. Memory-centric profiling is an important approach for dissecting an application's bottlenecks on memory access and guiding optimizations. Many existing memory profiling tools leverage hardware performance counters and precise event sampling, such as Intel PEBS and AMD IBS, to achieve high accuracy and low overhead. In this work, we present a multi-level memory profiling tool for ARM processors, leveraging Statistical Profiling Extension (SPE). We evaluate the tool using both HPC and Cloud workloads on the ARM Ampere processor. Our results provide the first quantitative assessment of time overhead and sampling accuracy of ARM SPE for memory-centric profiling at different sampling periods and aux buffer sizes.

Place, publisher, year, edition, pages
Institute of Electrical and Electronics Engineers (IEEE) , 2024. p. 996-1005
Keywords [en]
ARM SPE, memory profiling, precise event sampling
National Category
Computer Systems Computer Sciences
Identifiers
URN: urn:nbn:se:kth:diva-360172DOI: 10.1109/SCW63240.2024.00139ISI: 001451792300112Scopus ID: 2-s2.0-85217180414OAI: oai:DiVA.org:kth-360172DiVA, id: diva2:1938789
Conference
2024 Workshops of the International Conference for High Performance Computing, Networking, Storage and Analysis, SC Workshops 2024, Atlanta, United States of America, Nov 17 2024 - Nov 22 2024
Note

Part of ISBN 979-835035554-3

QC 20250224

Available from: 2025-02-19 Created: 2025-02-19 Last updated: 2025-09-24Bibliographically approved

Open Access in DiVA

No full text in DiVA

Other links

Publisher's full textScopus

Authority records

Miksits, SamuelShi, RuiminWahlgren, JacobSchieffer, GabinPeng, Ivy Bo

Search in DiVA

By author/editor
Miksits, SamuelShi, RuiminWahlgren, JacobSchieffer, GabinPeng, Ivy Bo
By organisation
Computational Science and Technology (CST)
Computer SystemsComputer Sciences

Search outside of DiVA

GoogleGoogle Scholar

doi
urn-nbn

Altmetric score

doi
urn-nbn
Total: 90 hits
CiteExportLink to record
Permanent link

Direct link
Cite
Citation style
  • apa
  • ieee
  • modern-language-association-8th-edition
  • vancouver
  • Other style
More styles
Language
  • de-DE
  • en-GB
  • en-US
  • fi-FI
  • nn-NO
  • nn-NB
  • sv-SE
  • Other locale
More languages
Output format
  • html
  • text
  • asciidoc
  • rtf