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Bounding Local Memory Usage of Preemptive 3-Phase Tasks under Partitioned Fixed-Priority Scheduling
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0001-9363-3525
KTH, School of Electrical Engineering and Computer Science (EECS), Electrical Engineering, Electronics and Embedded systems.ORCID iD: 0000-0002-1276-3609
2024 (English)In: 2024 32nd international conference on real-time networks and systems, RTNS 2024, Association for Computing Machinery (ACM) , 2024, p. 153-164Conference paper, Published paper (Refereed)
Abstract [en]

Phased execution models tame the increased complexity and unpredictability of commercial off-the-shelf (COTS) multi-core platforms by separating execution from access to shared resources, e.g., Acquisition-Execution-Restitution (AER) model, PRedictable Execution Model (PREM). Memory phases are used to preload all instructions and data into the local memory so that task computations can be performed only using the local memory without shared memory access. While preemption can improve the schedulability ratio, managing the local memory during preemption becomes nontrivial due to its limited size. In this work, we focus on the 3-phase model under partitioned fixed-priority scheduling. Existing works that allow preemption in this model make the conservative assumption that local memory is sufficiently large to hold the memory partitions for all tasks simultaneously. In contrast, we propose a novel preemption chain analysis that takes the characteristics of the phased execution model into account to compute tight bounds on the memory requirements of a task set under preemption. In addition, we propose a memory-aware mapping (MAM) algorithm that utilizes the preemption chain analysis to assign tasks to cores such that the resulting system meets both timing and memory constraints. Evaluations show that the preemption-chain analysis reduces the memory requirements by up to 50% compared to the state-of-the-art. We further show that the MAM algorithm provides 20% more task sets that satisfy both timing and memory constraints than mapping heuristics that don't take memory into account.

Place, publisher, year, edition, pages
Association for Computing Machinery (ACM) , 2024. p. 153-164
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:kth:diva-363834DOI: 10.1145/3696355.3699703ISI: 001446181700013Scopus ID: 2-s2.0-85217623182OAI: oai:DiVA.org:kth-363834DiVA, id: diva2:1962099
Conference
32nd International Conference on Real-Time Networks and Systems, NOV 06-08, 2024, Porto, PORTUGAL
Note

Part of ISBN 9798400717246

QC 20260610

Available from: 2025-05-28 Created: 2025-05-28 Last updated: 2026-06-10Bibliographically approved

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Thilakasiri, ThilankaBecker, Matthias

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