Not AND (NAND) flash memory has been widely used in consumer electronics in recent years. Due to various interferences faced by NAND flash memory, data reliability has severely declined. Low-density parity-check (LDPC) codes are leveraged for popular triple-level cell (TLC) NAND flash due to their strong error correction capability. LDPC decoding is an iterative procedure of log-likelihood ratio (LLR). The absorbing sets cause inaccurate LLRs to continuously propagate, making decoding difficult to converge, and severely affecting decoding performance. To improve decoding performance after LLR quantization, we propose an absorbing set characteristic aware LDPC algorithm, called AsLDPC, which modifies the LLR of some nodes in the absorbing sets through two Steps. For Step One, we select variable nodes that fall into absorbing sets based on sign characteristics of LLR at the late iteration and modify the initial prior message. For Step Two, we adjust the LLR of check nodes that satisfy the variable nodes and utilize the revised LLR to continue iteration. AsLDPC abstracts the process of finding the node locations in absorbing sets into formulas, finds the erroneous nodes through calculation, and then modifies their LLR messages. Simulation results demonstrate that AsLDPC significantly reduces the frame error rate (FER) by 58% and 48.1% for two LDPC codes, respectively, when compared to the quasi-uniform quantization scheme, while also reducing decoding latency. Additionally, AsLDPC outperforms the uniform algorithm in terms of storage space efficiency and maintains accurate decoding capabilities for raw bit error rate (RBER) below 1.2e - 2.