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Memory allocation in a hierarchical memory system
Ericsson.ORCID iD: 0000-0003-4088-7884
KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science.ORCID iD: 0000-0001-5083-4052
KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science.ORCID iD: 0000-0002-1256-1070
KTH, School of Electrical Engineering and Computer Science (EECS), Computer Science.ORCID iD: 0000-0002-6066-746X
2019 (English)Patent (Other (popular science, discussion, etc.))
Abstract [en]

A memory allocator in a computer system comprising a plurality of CPU cores (5101-5104) and a first (530) and a second (5120) memory unit having different data access times and wherein each one of the first and the second memory units is divided into memory portions wherein each memory portion (SLICE 0-3) in the second memory unit is associated with at least one memory portion (A-G) in the first memory unit, and wherein each memory portion in the second memory unit is associated with a CPU core. If at least a predetermined number of memory portions in the first memory unit being part of the available requested memory is associated with the memory portion in the second memory unit that is associated with the CPU core on which the requesting application is running, the requested available memory is allocated to the requesting application.

Place, publisher, year, edition, pages
2019.
Keywords [en]
memory allocator, CPU cores, memory unit
National Category
Computer Systems
Identifiers
URN: urn:nbn:se:kth:diva-379086OAI: oai:DiVA.org:kth-379086DiVA, id: diva2:2051599
Patent
US US 12293227 B2 (2025-05-06)
Funder
Wallenberg AI, Autonomous Systems and Software Program (WASP)
Note

QC 20260422

Available from: 2026-04-08 Created: 2026-04-08 Last updated: 2026-04-22Bibliographically approved

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Roozbeh, AmirFarshin, Alireza

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