Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with carrier mobility enhancement. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.

This article presents a low-cost, flexible, chipless Radio Frequency Identification (RFID) tag for humidity monitoring applications. The tag exhibits moisture sensing feature within a compact geometrical dimension of 20mm x 17.6mm. The design is loaded with 12 resonators, where each resonator represents 1 bit in the frequency domain. For the designed 12-bit tag, 11 inverted C-shaped resonators are dedicated for encoding 11-bit information in their spectral signature. An integrated meandered-shaped resonator, covered with moisture sensitive Kapton (R) HN film, functions as a 1-bit moisture sensor. It is deployed for monitoring relative humidity (RH) levels, simultaneously. The passive RFID tag is realized on Taconic TLX-0 and has an operational bandwidth of 2.62 GHz. Furthermore, the design is modeled and analyzed for multiple substrates. The performance of the sensor tag for various humidity levels indicates that it is a potential solution for inexpensive sensing applications.

Implantable tag antennas are an integral component of contemporary pervasive patient monitoring setups envisioned to reduce the medical errors and improve the quality of health care facilities. These tags, embedded into the human body, transmit critical patient information to the external equipment via a wireless communication link. This research article presents an implantable compact folded dipole antenna of size 10 mm 3 15 mm 3 2 mm, designed to operate in the industrial-scientificmedical band (2.4-2.48GHz). A three-layered phantom representing the human arm is used to evaluate the subcutaneous antenna performance. The tag antenna embedded in the middle of the fat layer offers a maximum gain of 216.3 dBi. The tag antenna performance as a function of implant position and phantom dimensions is analyzed. Link budget calculations show that with the achieved antenna gain the link power exceeds the required power by 38.37 dBm, and hence wireless communication is viable.

The current work is devoted to studying the evolution of deep level defects in the lower half of the 4H-SiC bandgap after high temperature processing and ion implantation. Two as-grown and pre-oxidized 4H-SiC sets of samples have been thermally treated at temperatures up to 1950 °C for 10 min duration using RF inductive heating. Another set of as grown samples was implanted by 4.2 MeV Si ions at room temperature (RT) with different doses (1- 4×108 cm-2). The so-called “D-center” at EV+0.6 eV dominates and forms after the elevated heat treatments, while it shows no change after the ion implantations (EV denotes the valence band edge). In contrast, the concentration of the so-called HK4 level at EV+1.44 eV increases with the implantation dose, whereas it anneals out after heat treatment at ≥ 1700 °C.

The carbon vacancy (V-C) is a prominent defect in as-grown 4H-SiC epitaxial layers for high power bipolar devices. V-C is electrically active with several deep levels in the bandgap, and it is an efficient "killer" of the minority carrier lifetime in n-type layers, limiting device performance. In this study, we provide new insight into the equilibration kinetics of the thermodynamic processes governing the V-C concentration and how these processes can be tailored. A slow cooling rate after heat treatment at similar to 2000 degrees C, typically employed to activate dopants in 4H-SiC, is shown to yield a strong reduction of the V-C concentration relative to that for a fast rate. Further, post-growth heat treatment of epitaxial layers has been conducted over a wide temperature range (800-1600 degrees C) under C-rich surface conditions. It is found that the thermodynamic equilibration of V-C at 1500 degrees C requires a duration less than 1 h resulting in a V-C concentration of only similar to 10(11) cm(-3), which is, indeed, beneficial for high voltage devices. In order to elucidate the physical processes controlling the equilibration of V-C, a defect kinetics model is put forward. The model assumes Frenkel pair generation, injection of carbon interstitials (C-i's) from the C-rich surface (followed by recombination with V-C's), and diffusion of V-C's towards the surface as the major processes during the equilibration, and it exhibits good quantitative agreement with experiment.

Dopant-defect reactions dominate the defect formation in mono-crystalline ZnO samples implanted with Ag and B ions. This is in contrast to most other ion species studied and results in an enhanced concentration of extended defects, such as stacking faults and defect clusters. Using a combination of B and Ag implants and diffusion of residual Li atoms as a tracer, we demonstrate that extended defects in ZnO act as efficient traps for highly mobile Zn interstitials. The results imply that dynamic annealing involving interaction of point defects with extended ones can play a key role in the disorder saturation observed for ZnO and other radiation-hard semiconductors implanted with high doses.

Spin torque nano-oscillators (STNO) represent a unique class of nano-scale microwave signal generators and offer a combination of intriguing properties, such as nano sized footprint, ultrafast modulation rates, and highly tunable microwave frequencies from 100 MHz to close to 100 GHz. However, their low output power and relatively high threshold current still limit their applicability and must be improved. In this study, we investigate the influence of the bottom Cu electrode thickness (t(Cu)) in nano-contact STNOs based on Co/Cu/NiFe GMR stacks and with nano-contact diameters ranging from 60 to 500 nm. Increasing t(Cu) from 10 to 70 nm results in a 40% reduction of the threshold current, an order of magnitude higher microwave output power, and close to two orders of magnitude better power conversion efficiency. Numerical simulations of the current distribution suggest that these dramatic improvements originate from a strongly reduced lateral current spread in the magneto-dynamically active region.

Spin torque nano-oscillators [1,2] (STNO) represent a unique class of nano-scale microwave signal generators where spin transfer torque [3-5] (STT) from a direct spin-polarized current drives and controls the auto-oscillation of the local free layer magnetization, which through its oscillating magnetoresistance transforms the direct current into a tunable microwave voltage.

Cipher-based message authentication code, CMAC, is a NIST approved standard for checking message integrity and authentication. This work presents a low-latency AES architecture for CMAC. The architecture uses intensive parallel processing per round and takes advantage of the BRAM present in modern FPGA. Experimental results show that for typical IoT application, the proposed architecture has a latency of 10 clock cycles, consumes 1355 slices, 2 BRAMs and achieves a throughput of 3.8Gbps.

Monolithic 3D (M3D) integration is considered as a key enabling technology for thecontinuation of Moore’s Law. To facilitate the study of M3D circuits, a design flow isclearly needed. In this work we discuss the potentials and challenges of thistechnology and present a design flow for M3D circuits which includes a M3D ProcessDesign Kit (PDK) with parametric extraction capabilities.

The Monolithic 3D (M3D) integration technology has emerged as a promising alternative to dimensional scaling thanks to the unprecedented integration density capabilities and the low interconnect parasitics that it offers. In order to support technological investigations and enable future M3D circuits, M3D design methodologies, flows and tools are essential. Prospective M3D digital applications have attracted a lot of scientific interest. This paper identifies the potential of M3D RF/analog circuits and presents the first attempt to demonstrate such circuits. Towards this, a M3D custom design platform, which is fully compatible with commercial design tools, is proposed and validated. The design platform includes process characteristics, device models, LVS and DRC rules and a parasitic extraction flow. The envisioned M3D structure is built on a commercial CMOS process that serves as the bottom tier, whereas a SOI process is used as top tier. To validate the proposed design flow and to investigate the potential of M3D RF/analog circuits, a RF front-end design for Zig-Bee WPAN applications is used as case-study. The M3D RF front-end circuit achieves 35.5 % area reduction, while showing similar performance with the original 2D circuit.

This paper demonstrates a fully integrated low phase noise PLL at 40GHz, implemented in a 0.25-μm SiGe:C BiCMOS technology. An in-band phase noise improvement of 1.4dB to 3.2dB is measured across the locking range using the proposed double-gain PFD. The PLL achieves an in-band phase noise <-92.5dBc/Hz and an integrated RMS jitter of 104fs, a 25% improvement over conventional PFD. The reference spurs are <-73dBc across the whole locking range.

Silicon nanoparticles (SiNPs) are formed by implanting 70 keV Si+ into a SiO2-film and subsequent thermal annealing. SiNP samples are further annealed in forming gas. Another group of samples containing SiNP is implanted by 7.5 keV H+ and subsequently annealed in N2-atmosphere at 450 °C to reduce implantation damage. Nuclear reaction analysis (NRA) is employed to establish depth profiles of the H-concentration. Enhanced hydrogen concentrations are found close to the SiO2surface, with particularly high concentrations for the as-implanted SiO2. However, no detectable uptake of hydrogen is observed by NRA for samples treated by forming gas annealing (FGA). H-concentrations detected after H-implantation follow calculated implantation profiles. Photoluminescence (PL) spectroscopy is performed at room temperature to observe the SiNP PL. Whereas FGA is found to increase PL under certain conditions, i.e., annealing at high temperatures, increasing implantation fluence of H reduces the SiNP PL. Hydrogen implantation also introduces additional defect PL. After low-temperature annealing, the SiNP PL is found to improve, but the process is not found equivalently efficient as conventional FGA.

The effects of MeV heavy ion irradiation at varying fluence and flux on excess Si, introduced in SiO2 by keV ion implantation, are investigated by photoluminescence (PL). From the PL peak wavelength (λ) and decay lifetime (τ), two PL sources are distinguished: i) quasi-direct recombination of excitons of Si-nanoparticles (SiNPs), appearing after thermal annealing (λ &gt; 720 nm, τ ∼ μs), and ii) fast-decay PL, possibly due to oxide-related defects (λ ∼ 575-690 nm, τ ∼ ns). The fast-decay PL (ii) observed before and after ion irradiation is induced by ion implantation. It is found that this fast-decay luminescence decreases for higher irradiation fluence of MeV heavy ions. After thermal annealing (forming SiNPs), the SiNP PL is reduced for samples irradiated by MeV heavy ions but found to stabilize at higher level for higher irradiation flux; the (ii) band vanishes as a result of annealing. The results are discussed in terms of the influence of electronic and nuclear stopping powers.

Silicon carbide is an excellent candidate when high temperature power electronics applications are considered. Integrated circuits as well as several power devices have been tested at high temperature. However, little attention has been paid to high temperature passive components that could enable the full SiC potential. In this work, the high-temperature performances of different passive components have been studied. Integrated capacitors in bipolar SiC technology have been tested up to 300 degrees C and, three different designs of inductors have been tested up to 700 degrees C.

Modern energy storage devices for portable and wearable technologies must fulfill a number of requirements, such as small size, flexibility, thinness, reliability, transparency, manufacturing simplicity and performance, in order to be competitive in an ever expanding market. To this end, a comprehensive inkjet printing process is developed for the scalable and low-cost fabrication of transparent and flexible micro-supercapacitors. These solid-state devices, with printed thin films of graphene flakes as interdigitated electrodes, exhibit excellent performance versus transparency (ranging from a single-electrode areal capacitance of 16 mu F cm(-2) at transmittance of 90% to a capacitance of 99 mu F cm(-2) at transmittance of 71%). Also, transparent and flexible devices are fabricated, showing negligible capacitance degradation during bending. The ease of manufacturing coupled with their great capacitive properties opens up new potential applications for energy storage devices ranging from portable solar cells to wearable sensors.

In the internet of things age, future communication technologies should provide the necessary bandwidth and latency for the connection of billion devices and the development of ubiquitous applications to improve the quality of life. The design of the prospected mobile communication system needs wide skills in wireless communication, analog circuit design, embedded system, microwave technology, and so forth. System level analyses, design space exploration, performance tradeoffs are some key steps that enable the design of low-cost, energy efficient, ubiquitous and flexible transceiver. This chapter provides comprehensive design techniques for 5G mobile communication in the dark silicon era and using More than Moore technology (MtM). 

To achieve p-n junctions for n-type solar cells, we have studied BBr3 diffusion in an open tube furnace, varying parameters of the BBr3 diffusion process such as temperature, gas flows, and duration of individual process steps, i.e., predeposition and drive-in. Then, output parameters such as carrier lifetime, sheet resistance, and diffusion profile were measured and statistically analyzed to optimize the emitter characteristics. Statistical analysis (factorial design) was finally employed to systematically explore the effects of the set of input variables on the outputs. The effect of the interactions between inputs was also evaluated for each output, quantified using a two-level factorial method. Temperature and BBr3 flow were found to have the most significant effect on different outputs such as carrier lifetime, junction depth, sheet resistance, and final surface concentration.

A self-aligned Nickel (Ni) silicide process (Salicide) for n-type ohmic contacts on 4H-SiC is demonstrated and electrically verified in a wafer-scale device process. The key point is to anneal the contacts in two steps. The process is successfully employed on wafer-level and a contact resistivity below 5 × 10−6 Ω · cm2 is achieved. The influence of the proposed process on the oxide quality is investigated and no significant effect is observed. The proposed self-aligned technology eliminates the undesirable effects of the lift-off process. Moreover, it is simple, fast, and manufacturable at wafer-scale which saves time and cost.

High-current 4H-SiC lateral BJTs for hightemperature monolithic integrated circuits are fabricated. The BJTs have three different sizes and the designs are optimized in terms of emitter finger width and length and the device layout to have higher current density (J(C)), lower on-resistance (R-ON), and more uniform current distribution. A maximum current gain (beta) of >53 at significantly high current density was achieved for different sizes of SiC BJTs. The BJTs aremeasured fromroom temperature to 500 degrees C. An open-base breakdown voltage (V-CEO) of > 50 V is measured for the devices.

1.2 kV SiC buried grid junction barrier Schottky (BG-JBS) diodes are demonstrated. The design considerations for high temperature applications are investigated. The design is optimized in terms of doping concentration and thickness of the epilayers, as well as grid size and spacing dimensions, in order to obtain low on-resistance and reasonable leakage current even at high temperatures. The device behavior at temperatures ranging from 25 to 250ºC is analyzed and measured on wafer level. The forward voltage drop of 1.1 V at 100 A/cm2 and 3.8 V at 1000 A/cm2 is measured, respectively. At reverse voltage of 1 kV, a leakage current density below 0.1 μA/cm2 and below 0.1 mA/cm2 is measured at 25 and 250ºC, respectively. This proves the effective shielding effect of the BG-JBS design and provides benefits in high voltage applications, particularly for high temperature operation.

We present dispersion-corrected density functional calculations of water and carbon dioxide molecules adsorption on graphene residing on silica and sapphire substrates. The equilibrium positions and bonding distances for the molecules are determined. Water is found to prefer the hollow site in the center of the graphene hexagon, whereas carbon dioxide prefers sites bridging carbon-carbon bonds as well as sites directly on top of carbon atoms. The energy differences between different sites are however minute - typically just a few tenths of a millielectronvolt. Overall, the molecule-graphene bonding distances are found to be in the range 3.1-3.3 (A) over circle. The carbon dioxide binding energy to graphene is found to be almost twice that of the water binding energy (around 0.17 eV compared to around 0.09 eV). The present results compare well with previous calculations, where available. Using charge density differences, we also qualitatively illustrate the effect of the different substrates and molecules on the electronic structure of the graphene sheet.

Graphene has interesting gas sensing properties with strong responses of the graphene resistance when exposed to gases. However, the resistance response of double-layer graphene when exposed to humidity and gasses has not yet been characterized and understood. In this paper we study the resistance response of double-layer graphene when exposed to humidity and CO₂, respectively. The measured response and recovery times of the graphene resistance to humidity are on the order of several hundred milliseconds. For relative humidity levels of less than ~ 3% RH, the resistance of double-layer graphene is not significantly influenced by the humidity variation. We use such a low humidity atmosphere to investigate the resistance response of double-layer graphene that is exposed to pure CO₂ gas, showing a consistent response and recovery behaviour. The resistance of the double-layer graphene decreases linearly with increase of the concentration of pure CO₂ gas. Density functional theory simulations indicate that double-layer graphene has a weaker gas response compared to single-layer graphene, which is in agreement with our experimental data. Our investigations contribute to improved understanding of the humidity and CO₂ gas sensing properties of double-layer graphene which is important for realizing viable graphene-based gas sensors in the future.

In this paper chipless RFID tag, capable of carrying 9-bit data is presented. The tag is optimized for several flexible substrates. With growing information and communication technology, sensor integration with data transmission has gained significant attention. Therefore, the tag with the same dimension is then optimized using paper substrate. For different values of permittivity, the relative humidity is observed. Hence, besides carrying information bits, the tag is capable of monitoring and sensing the humidity. The overall dimension of the tag comprising of 9 ring slot resonators is 7 mm. Due to its optimization on the paper substrate, the tag can be an ideal choice for deploying in various low-cost sensing applications.

In this letter, 8-bit paper based printable chipless tag is presented. The tag not only justifies the green electronic concept but also it is examined for sensing functionality. The compact tag structure comprises of seven L-shaped and one I-shaped dipole structure. These conducting tracks/dipole structures are of silver nano-particle based ink having a conductivity of 1.1 × 107 S/m. Each conducting track yields one bit corresponding to one peak. The tag design is optimized and analyzed for three different flexible substrates i.e. paper, Kapton® HN, and PET. The tag has ability to identify 28 = 256 objects, by using different binary combinations. The variation in length of particular conducting strip results in a shift of peak for that specific conducting track. This shift corresponds to logic state-1. The response of the tag for paper, Kapton® HN, and PET substrates is observed in the frequency band of 2.2-6.1 GHz, 2.4-6.3 GHz, and 2.5-6.5 GHz, respectively. The tag has an attractive nature because of its easy printability and usage of low-cost, flexible substrates. The tag can be deployed in various low-cost sensing applications.

A chipless RFID tag with unique ASK encoding technique is presented in this paper. The coding efficiency is enhanced regarding tag capacity. The amplitude variations of the backscattered RFID signal is used for encoding data instead of OOK Strips of different widths are used to have amplitude variations. The ASK technique is applied using three different substrates of Kapton (R) HN, PET, and paper. To incorporate ASK technique, dual polarized rhombic shaped resonators are designed. These tags operate in the frequency range of 3.1-10.6 GHz with size of 70 x 42 mm(2). The presented tags are flexible and offer easy printability. The paper-based decomposable organic tag appears as an ultra low-cost solution for wide scale tracking. This feature enables them to secure a prominent position in the emerging fields of IoT and green electronics.

Aggressive technology scaling and intensive computations have caused acceleration in the aging and wear-out process of digital systems, hence leading to an increased occurrence of premature permanent faults. Online testing techniques are becoming a necessity in current and near future digital systems. However, state-of-the-art techniques are not aware of the other digital systems’ power/performance requirements that exist in modern multi-/many-core systems. This chapter presents an approach for power-aware non-intrusive online testing in many-core systems. The approach aims at scheduling at runtime Software-Based Self-Test (SBST) routines on the various cores to exploit their idle periods in order to benefit the potentially available power budget and minimize the performance degradation. Furthermore, a criticality metric is used to identify and rank cores that need testing at a time and power and reliability issues related to the testing at different voltage and frequency levels are taken into account. Experimental results show that the proposed approach can (1) efficiently perform cores’ testing, within less than 1?% penalty on system throughput and by dedicating only 2?% of the actual consumed power, (2) adapt to the current stress level of the cores by using the utilization metric, and (3) cover all the voltage and frequency levels during the various tests.

This paper demonstrates a fully integrated master-slave emitter-coupled logic (ECL)comparator and a frequency divider implemented in 4H-SiC bipolar technology. The comparator consists of two latch stages, two level shifters and an output buffer stage. The circuits have been tested up to 500 °C. The single ended output swing of the comparator is -7.73 V at 25 °C and-7.63 V at 500 °C with a -15 V supply voltage. The comparator consumes 585 mW at 25 °C. The frequency divider consisting of two latches shows a relatively constant output voltage swing over the wide temperature range. The output voltage swing is 7.62 V at 25 °C and 7.32 V at 500 °C.

An in-house fabricated 4H-SiC PIN diode that has both optical sensing and temperature sensing functions from room temperature (RT) to 550 ºC is presented. The two sensing functions can be simply converted from one to the other by switching the bias voltage on the diode. The optical responsivity of the diode at 365 nm is 31.8 mA/W at 550 ºC. The temperature sensitivity of the diode is 2.7 mV/ºC at the forward current of 1 μA.

The p-i-n ultraviolet (UV) photodiodes based on 4H-SiC have been fabricated and characterized from room temperature (RT) to 550 degrees C. Due to bandgap narrowing at higher temperatures, the photocurrent of the photodiode increases by 9 times at 365 nm and reduces by 2.6 times at 275 nm from RT to 550 degrees C. Moreover, a 4H-SiC p-i-n photodiode array has been fabricated. Each column and row of the array is separately connected by two-layer metallization.

Ultraviolet (UV) detection is important in astronomy, combustion detections and medical analysis. Solid-state UV detectors based on wide band gap semiconductors, such as 4H-SiC, are widely studied because of their excellent electrical properties [1]. 4H-SiC based UV detectors are solar blind and can be applied in extremely high temperature environments [2]. However, the state-of-art 4H-SiC photodetectors still have large sizes (&gt;10000 μm2), which are not suitable to be integrated into high resolution UV photography sensors. To build a full-frame UV imaging sensor containing megapixels, photodiodes smaller than 20 μm by side are necessary. Here, we report the fabrication and characterization of 4H-SiC p-i-n photodiodes with mesa areas scaled from 40000 μm2 to 400 μm2. The relationships between the parameters and the areas of the photodiodes are discussed. The photodiodes are fully functional from room temperature (RT) to 500 °C.

This paper presents a multiplication reduction technique through near-zero approximation, enabling embedded learning in resource-constrained IoT devices. The intrinsic resilience of neural network and the sparsity of data are identified and utilized. Based on the analysis of leading zero counting and adjustable threshold, intentional approximation is applied to reduce near-zero multiplications. By setting the threshold of the multiplication result to 2-5 and employing ReLU as the neuron activation function, the sparsity of the CNN model can reach 75% with negligible loss in accuracy when recognizing the MNIST data set. Corresponding hardware implementation has been designed and simulated in UMC 65nm process. It can achieve more than 70% improvement of energy efficiency with only 0.37% area overhead of a 256 Multiply-Accumulator array.

A polarization insensitive, compact, fully-passive bit encoding structure exhibiting 1 : 1 resonator-to-bit correspondence is presented. Inspired by frequency selective surface (FSS) based microwave absorbers, the structure readily operates as a chipless radio frequency identification (RFID) tag. The unit cell is composed of several concentric hexagonal loops. Finite repetitions of the unit cell constitute the proposed RFID tag in its entirety. The required bit sequence is encoded in the frequency domain by addition or omission of corresponding nested resonant elements. A functional prototype is fabricated on a commercial-grade grounded FR4 substrate, occupying a physical footprint of 23 × 10mm2 while offering a capacity of 14 bits. The proposed tag boasts a minuscule profile, and demonstrates polarization insensitivity as well as stable oblique angular performance.

This paper presents a switched-capacitor high-pass delta-sigma modulator that can directly convert a chopper modulated signal to the digital domain. Low power consumption is achieved by employing inverter-based amplifiers and dynamic biasing in the first amplifier with relaxed slew-rate requirements as a result of the multi-bit quantization. The mismatch errors in the switched-capacitor DAC are first-order noise shaped by a tree-structured dynamic element matching encoder. Schematic level simulations show that the high-pass modulator achieves a peak SNDR of 96.4 dB and a SFDR of 101 dBc over a bandwidth of 300 Hz. The total estimated power consumption of the modulator is 19.56 mu W leading to a figure-of-merit of 0.6 pJ/conv.

The authors have studied the reaction between a Ge (100) substrate and thin layers of Ni ranging from 2 to 10 nm in thickness. The formation of metal-rich Ni5Ge3 was found to precede that of the monogermanide NiGe by means of real-time in situ x-ray diffraction during ramp-annealing and ex situ x-ray pole figure analyses for phase identification. The observed sequential growth of Ni5Ge3 and NiGe with such thin Ni layers is different from the previously reported simultaneous growth with thicker Ni layers. The phase transformation from Ni5Ge3 to NiGe was found to be nucleationcontrolled for Ni thicknesses < 5 nm, which is well supported by thermodynamic considerations. Specifically, the temperature for the NiGe formation increased with decreasing Ni (rather Ni5Ge3) thickness below 5 nm. In combination with sheet resistance measurement and microscopic surface inspection of samples annealed with a standard rapid thermal processing, the temperature range for achieving morphologically stable NiGe layers was identified for this standard annealing process. As expected, it was found to be strongly dependent on the initial Ni thickness.

This work proposes a new power management scheme for wirelessly-powered UHF RFID tags with flexible inkjet-printed Electrochromic (EC) display for human-to-device interaction. EC display on polyimide substrate is integrated at tag side to provide an ambient and direct human-to-device display interface. An aggressive duty-cycling power management scheme with dual supplies is designed to drive the EC display under the tag power budget in microwatt level through RF energy harvesting. In this scheme, energy for display refreshing is accumulated over multiple power management cycles. A single-pixel addressing scheme with minimal pixel size is proposed to further reduce display power and improve tag sensitivity by exploiting EC display bi-stability. The experimental results show that the EC display can be refreshed with the tag sensitivity of -10.5 dBm at 11.7 sec/cm2 update rate.

An efficient run-time application mapping approach can considerably enhance resource utilization and mitigate the dark silicon phenomenon. In this chapter, we present a dark silicon aware run-time application mapping approach that patterns active cores alongside the inactive cores in order to evenly distribute power density across the chip. This approach leverages dark silicon to balance the temperature of active cores to provide higher power budget and better resource utilization, within a safe peak operating temperature. In contrast to exhaustive search based mapping techniques, the proposed agile heuristic approach has a negligible run-time overhead. This patterning strategy yields a surplus power budget of up to 17?% along with an improved throughput of up to 21?% in comparison with other state-of-the-art run-time mapping strategies, while the surplus budget is as high as 40?% compared to worst case scenarios.

The possibilities to increase single-core performance have ended due to limited instruction-level parallelism and a high penalty when increasing frequency. This prompted designers to move toward multi-core paradigms [1], largely supported by transistor scaling [2]. Scaling down transistor gate length makes it possible to switch them faster at a lower power, as they have a low capacitance. In this context, an important consideration is power density-the power dissipated per unit area. Dennard’s scaling establishes that reducing physical parameters of transistors allows operating them at lower voltage and thus at lower power, because power consumption is proportional to the square of the applied voltage, keeping power density constant [3]. Dennard’s estimation of scaling effects and constant power density is shown in Table 1.1. Theoretically, scaling down further should result in more computational capacity per unit area. However, scaling is reaching its physical limits to an extent that voltage cannot be scaled down as much as transistor gate length leading to failure of Dennardian trend. This along with a rise in leakage current results in increased power density, rather than a constant power density. Higher power density implies more heat generated in a unit area and hence higher chip temperatures which have to be dissipated through cooling solutions, as increase in temperature beyond a certain level results in unreliable functionality, faster aging, and even permanent failure of the chip. To ensure a safe operation, it is essential for the chip to perform within a fixed power budget [4]. In order to avoid too high power dissipation, a certain part of the chip needs to remain inactive; the inactive part is termed dark silicon [5]. Hence, we have to operate working cores in a multi-core system at less than their full capacity, limiting the performance, resource utilization, and efficiency of the system.

Power capping techniques based on dynamic voltage and frequency scaling (DVFS) and power gating (PG) are oriented toward power actuation, compromising on performance and energy. Inherent error resilience of emerging application domains, such as Internet-of-Things (IoT) and machine learning, provides opportunities for energy and performance gains. Leveraging accuracy-performance tradeoffs in such applications, we propose approximation (APPX) as another knob for close-looped power management, to complement power knobs with performance and energy gains. We design a power management framework, APPEND+, that can switch between accurate and approximate modes of execution subject to system throughput requirements. APPEND+ considers the sensitivity of the application to error to make disciplined alteration between levels of APPX such that performance is maximized while error is minimized. We implement a power management scheme that uses APPX, DVFS, and PG knobs hierarchically. We evaluated our proposed approach over machine learning and signal processing applications along with two case studies on IoT-early warning score system and fall detection. APPEND+ yields 1.9x higher throughput, improved latency up to five times, better performance per energy, and dark silicon mitigation compared with the state-of-the-art power management techniques over a set of applications ranging from high to no error resilience.

In the recent decade, integrated electronics in wide bandgap semiconductor technologies such as Gallium Nitride (GaN) and Silicon Carbide (SiC) have been shown to be viable candidates in extreme environments (e.g high-temperature and high radiation). Such electronics have applications in down-hole drilling, automobile-, air- and space- industries. In this thesis, integrated circuits (ICs) in bipolar 4H-SiC for high-temperature power applications are explored. In particular, device modelling, circuit design, layout design, and measurements are discussed for a range of circuits including operational amplifiers, linear voltage regulators, drivers for power switches, and power converters with integrated control. The circuits were demonstrated and tested from 25 °C up to 500 °C. Circuit design in bipolar SiC technology involves challenges such as the fabrication process’ uncertainties and incomplete models of the devices. Furthermore, high temperature modelling of the integrated devices is needed for circuit design and simulation. From the circuit design viewpoint, techniques such as negative-feedback, temperature-insensitive biasing, buffering and Darlington stages, and amplifiers with fewer gain stages, were shown to be useful for high-temperature IC design in bipolar SiC. It is shown that the linear voltage regulator can be improved by using a tailored high-current lateral Darlington power device in the same fabrication process. This results in a high temperature high current power supply solution. Moreover, the drivers can be improved by design in order to provide higher voltage levels and peak currents for the power devices (bipolar and MOSFET based). In addition, a DC-DC converter with fully integrated hysteretic control is designed taking advantage of several sub-circuits such as operational amplifier, Schmitt trigger and driver for the power switch. This study is followed by preliminary experimental results for the converter and controller IC.

A dual-source energy harvesting interface that combines energy from implanted glucose biofuel cell and thermoelectric generator is presented. A single-inductor dual-input dual-output boost converter topology is employed to efficiently transfer the extracted power to the output. A dual-input feature enables the simultaneous maximum power extraction from two harvesters, while a dual-output allows a control circuit to perform complex digital functions at nW power levels. The control circuit reconfigures the converter to improve the efficiency and achieve zero-current and zero-voltage switching. The measurement results of the proposed boost converter, implemented in a 0.18 μm CMOS process, show a peak efficiency of 89.5% when both sources provide a combined input power of 66 μW. In the single-source mode, the converter achieves a peak efficiency of 85.2% at 23 μW for the thermoelectric source and 90.4% at 29 μW for the glucose biofuel cell. The converter can operate from minimum input voltages of 10 mV for the thermoelectric source and 30 mV for the glucose biofuel cell. 

A theoretical analysis of losses in low power thermoelectric harvester interfaces is used to find expressions for properly sizing the power transistors according to the input voltage level. These expressions are used to propose an adaptive FET sizing technique that tracks the input voltage level and automatically reconfigures the converter in order to improve its conversion efficiency. The performance of a low-power thermoelectric energy harvesting interface with and without the proposed technique is evaluated by circuit simulations under different input voltage/power conditions. The simulation results show that the proposed technique improves the conversion efficiency of the energy harvesting interface up to 12% at the lowest input voltage/power levels.

Fossil fuel storage is running low and scientists around the globe are involved in a big search for an optimized substitute. Photovoltaic is one of the most likely alternatives to solve this issue and replace the fossil fuels. Among all types of cells, silicon solar cells are the most economical ones to produce affordable energy. In this paper, a systematic study was done on the diffusion of phosphorous in multi-crystalline silicon during solar cell emitter formation. All parameters involved in the conversion of a multi-crystalline p-type silicon to a p-n junction were analyzed quantitatively. This systematic approach predicts the effect of inputs on the outputs which decreases the number of the trail runs. The analysis result indicate, that raising the diffusion temperature from 830 to 880 A degrees C decreases the sheet resistance by -100 Omega/sq, and increasing POCl3 flow from 300 to 500 SCCM has an effect of -21 Omega/sq.

This article presents a low-cost, compact antenna with coplanar waveguide (CPW) feed line for multiband wireless applications. The presented multiband radiator is envisioned for integration into microwave circuits and portable RF devices. The prototype is realized on 1.6 mm thick readily available FR4 substrate with a compact geometrical size of 24x32 mm(2). The acquired quad-bands are centered at: 2.45, 3.5, 5.2 and 5.8 GHz justifying the appropriateness of the proposed radiator for the WLAN and WiMAX applications, as well as Bluetooth and ISM wireless standards. From the aspect of integration into transportable handheld devices and system designing, the presented compact antenna illustrates more expandability and flexibility. The radiation characteristics measured in the E and H-planes for desired operating frequencies are monopole-like and omni-directional, respectively. A sufficient gain is also achieved. Simulated as well as experimental results exhibit agreeable behavior.

For logic gate with higher voltage swing, 4H-SiC pseudo-CMOS logic inverter with four nMOS was suggested and demonstrated, and a high voltage swing of 4.4 V was achieved at VDD=5 V. Simple nMOS inverters were also investigated. Both of pseudo-CMOS and nMOS inverters were operated at a high temperature of 200ºC. For future SiC large integrated circuits, junction leakage current between n+ regions were also investigated with the comb-shaped test elements.

The formation of interfacial oxides during heat treatment of dielectric films on 4H-SiC has been studied. The 4H-SiC surface has been carefully prepared to create a clean and abrupt interface to Al2O3. An amorphous, 3 nm thick, Al2O3 film has been prepared on 4H-SiC by atomic layer deposition and rapid thermal annealing was then performed in N2O ambient at 700 degrees C and 1100 degrees C during 1 min. The samples were studied by time-of-flight medium energy ion scattering (ToF-MEIS), with sub-nanometer depth resolution and it is seen that, at both annealing temperatures, a thin SiOx (1 <= x <= 2) is formed at the interface. Our results further indicate that carbon remains in the silicon oxide in samples annealed at 700 degrees C. Additional electrical capacitance voltage measurements indicate that a large concentration of interface traps is formed at this temperature. After 1100 degrees C annealing, both MEIS and XRD measurements show that these features disappear, in accordance with electrical data.

We report here heterogeneous photonic crystal (PC) bandedge surface emitting membrane lasers on bulk silicon (Si) substrates. Optically pumped lasers were demonstrated experimentally with single mode operation and side-mode suppression ratio (SMSR) greater than 13.5 dB. Thermal resistance was investigated to evaluate the heat dissipation and lasing characteristics afforded by this integration and potential for high efficiency application.