This work proposes a compact, penta-band, slotted antenna with Defected Ground Structure (DGS). The proposed multiband resonator is intended for integration into microwave circuits and portable RF portable devices. The prototype with spurlines and DGS is designed on thin Rogers RT Duroid 5880 substrate having thickness 0.508 mm. The presented radiator is capable to cover the frequency bands 2.46-2.59 GHz, 2.99-3.78 GHz, 5.17-5.89 GHz, 6.86-7.36 GHz, 9.38-11 GHz. The impedance bandwidths of 5.24%, 23.68%, 12.8%, 7.24% and 16.08% is obtained for the covered frequency bands respectively. The antenna proposed in this work thus supports WLAN, WiMAX, ISM, LTE, Bluetooth, C-band and X-band applications. The radiator attains 4.2 dB peak gain. It is apparent from the radiation performance of the prototype, that it is an effective candidate for current and forthcoming multiband wireless applications.

Combinatorial optimization problems are known for being particularly hard to solve on traditional von Neumann architectures. This has led to the development of Ising Machines (IMs) based on quantum annealers and optical and electronic oscillators, demonstrating speed-ups compared to central processing unit (CPU) and graphics processing unit (GPU) algorithms. Spin torque nano-oscillators (STNOs) have shown GHz operating frequency, nanoscale size, and nanosecond turn-on time, which would allow their use in ultrafast oscillator-based IMs. Here, we show using numerical simulations based on STNO auto-oscillator theory that STNOs exhibit fundamental characteristics needed to realize IMs, including in-phase/out-of-phase synchronization and second harmonic injection locking phase binarization. Furthermore, we demonstrate numerically that large STNO network IMs can solve Max-Cut problems on nanosecond timescales.

Emerging spin-torque nano oscillators (STNOs) and spin-Hall nano oscillators (SHNOs) are potential candidates for microwave applications. Recent advances in three-terminal magnetic tunnel junction (MTJ)-based SHNOs opened the possibility to develop more reliable and well-controlled oscillators, thanks to individual spin Hall-driven precession excitation and read-out paths. To develop hybrid systems by integrating three-terminal SHNOs and CMOS circuits, an electrical model able to capture the analog characteristics of three-terminal SHNOs is needed. This model needs to be compatible with current electric design automation (EDA) tools. This work presents a comprehensive macrospin-based model of three-terminal SHNOs able to describe the dc operating point, frequency modulation, phase noise, and output power. Moreover, the effect of voltage-controlled magnetic anisotropy (VCMA) is included. The model shows good agreement with experimental measurements and could be used in developing hybrid three-terminal SHNO/CMOS systems.

In this work, a novel magnetic field-to-digital converter based on emerging spin-torque nano-oscillators (STNOs) is proposed. The architecture is inspired by voltage controlled oscillator (VCO)-based analog-to-digital converters (ADCs) which have shown inherent first-order noise shaping of both quantization- and phase-noise without the need for feedback. In the proposed architecture, the STNO acts both as a magnetic field sensor and VCO. The architecture's performance is evaluated in terms of signal-to-noise and distortion ratio (SNDR) utilizing Verilog-AMS modeling, where a macrospin model fitted to experimental data is employed for accurate description of the STNO operation. The presented simulation results demonstrate the potential of the STNO-based magnetic field-to-digital converter architecture.

Early warning score (EWS) is an approach to detect the deterioration of a patient. It is based on a fact that there are several changes in the physiological parameters prior a clinical deterioration of a patient. Currently, EWS procedure is mostly used for in-hospital clinical cases and is performed in a manual paper-based fashion. In this paper, we propose an automated EWS health monitoring system to intelligently monitor vital signs and prevent health deterioration for in-home patients using Internet-of-Things (IoT) technologies. IoT enables our solution to provide a real-Time 24/7 service for health professionals to remotely monitor inhome patients via Internet and receive notifications in case of emergency. We also demonstrate a proof-of-concept EWS system where continuous reading, transferring, recording, and processing of vital signs have been implemented. 

This paper presents a novel electronically polarization reconfigurable 2 port multi input multi output (MIMO) for millimeter wave (MMW) fifth-generation (5G) wireless communications. The design consists of slotted circular patch. A semicircle and open-ended T-shaped arcs are inserted in circular patch to achieve the circular polarization. Furthermore in order to enhance the gain 2 element array is designed. Two pin-diodes are inserted in antenna array for polarization diversity. The design is extended to two ports MIMO. Port isolation is enhanced between the ports using defected ground structure (DGS). The vertical and horizontal slots are inserted in the ground to enhance the port isolation. The presented design covers dual frequency band that 24.0-25.3 and 27.3-28.7 GHz band. The 27.3-28.7 GHz band is considered for investigation of all parameters. The simulated peak gain is 9.99 dBi. The axial ratio (AR) below-3dB is achieved for whole operating band of proposed design. The MIMO performance parameters like transmission coefficient, Envelop correlation coefficient (ECC), and diversity gain (DG) are also investigated.

An electronically beam-steerable antenna (BSA) is envisioned. The presented BSA is a possible solution to overthrow the limitations inherent to phased antenna arrays. The design consists of a gap coupling inset feed rectangular patch (driven element) and 3 x 1 passive parasitic patches deployed on both sides of the driven patch. Prototype having 20 x 20 mm dimensions is printed on Rogers(R) RT/duroid(R)5870. Four switches are used to load the reactive impedance on parasitic patches, which in turn, change the phases of surface current on parasitic elements and the driven element. Based on the different ON and OFF configuration of switches in parasitic array elements, the main beam is steered along with different directions. The simulated results show that the design can operate between 26.8 and 30.3 GHz a wide impedance bandwidth |S-11|< -10 dB (12.5%) with a peak gain of 8.9 dBi and wide 3-dB scanning angle that is, -37 degrees to 156 degrees in the azimuth plane. The exhibited performance of BSA with favourable characteristics, such as wideband, adequate gain, wide-angle beam switching, and low profile renders the BSA a good candidate for 5G millimetre wave handheld devices. Moreover, to corroborate the performance, the design is fabricated, and experimental measurements were performed. Congruence is observed between the experimentally measured and computationally simulated results. The simulated results of spherical coverage analysis of BSA with the integration of smartphone form factor are also presented.

The conventional 2D geometrical scaling of transistors is now facing many challenges in order to continue the performance enhancement while decreasing power consumption. The decrease in the device power consumption is related to the scaling of the power supply voltage (V_dd) and interconnects wiring length. In addition, monolithic three dimensional (M3D) integration in the form of vertically stacked devices, is a possible solution to increase the device density and reduce interconnect wiring length. Integrating strained germanium on insulator (sGeOI) pMOSFETs monolithically with strained silicon/silicon-germanium on insulator (sSOI/sSiGeOI) nMOSFETs can increase the device performance and packing density. Low temperature processing (<550 ºC) is essential as interconnects and strained layers limit the thermal budget in M3D. This thesis presents an experimental investigation of the low temperature (<450 ºC) fabrication of group IV semiconductor-on-insulator substrates with the focus on sGeOI and sSiGeOI fabrication processes compatible with M3D.

  To this aim, direct bonding was used to transfer the relaxed and strained semiconductor layers. The void formation dependencies of the oxide thickness, the surface treatment of the oxide and the post annealing time were fully examined. Low temperature SiGe epitaxy was investigated with the emphasis on the fabrication of Si_0.5Ge_0.5 strain-relaxed buffers (SRBs), etch-stop layer, and the device layer in the SiGeOI and GeOI process schemes. Ge epitaxial growth on Si as thick SRBs and thin device layers was investigated. Thick (500 nm-3 µm) and thin (<30 nm) relaxed GeOI substrates were fabricated. The latter was fabricated by continuous epitaxial growth of a 3-µm Ge (SRB)/Si_0.5Ge_0.5 (etch stop)/Ge (device layer) stack on Si. The fabricated long channel Ge pFETs from these GeOI substrates exhibit well-behaved IV characteristics with an effective mobility of 160 cm²/Vs.

  The planarization of SiO₂ and SiGe SRBs for the fabrication of the strained GeOI and SiGeOI were accomplished by chemical mechanical polishing (CMP). Low temperature processes (<450 ºC) were developed for compressively strained GeOI layers (ɛ ~ -1.75 %, < 20 nm), which are used for high mobility and low power devices. For the first time, tensile strained Si_0.5Ge_0.5 (ɛ ~ 2.5 %, < 20 nm) films were successfully fabricated and transferred onto patterned substrates for 3D integration.

This article presents a 12-bit frequency coded chipless RFID system in the frequency range of 3 to 6 GHz. The system consists of a fully printable chipless tag and a pair of high-gain reader antennas. The tag also incorporates its own antennas to improve the read range. Information is encoded into frequency spectrum using a multi-resonant circuit. The circuit consists of multiple microstrip U and L-shaped open stub resonators patterned in a unique configuration. The proposed configuration aids in capturing more data in a reduced space as well as tunable frequency operation. Tag and reader antennas utilize techniques such as stepped impedance feeding line, defective partial ground plane, and stair-step patch structure to achieve wide-band impedance bandwidth in miniature size. The results of the wireless measurements in the non-anechoic environment show that the proposed system has a reading range of more than 20 cm. The presented system possesses great potential for low-cost short-range inventory tracking.

A novel low-profile metal mountable UHF RFID tag antenna is presented. The tag antenna design consists of two resonating patches with different resonant frequencies fed through a joint inductive loop. This design topology offers benefits such as bandwidth enhancement in the single band and the possibility of attaining a tunable dualband coverage in the UHF RFID band. The proposed antenna structure doesn't require any electrical connection (shorting pins/shorting plates/via holes) and therefore facilitates fabrication through a conventional RFID inlay manufacturing process. Fabrication and testing of a prototype of the proposed antenna design are carried out. The prototype antenna achieves free space and an on-metal reading range of better than 8 m and 11 m respectively in the US RFID band of 902-928 MHz.

The carbon vacancy (Vc) is perhaps the most prominent point defect in silicon carbide (SiC) and it is an efficient charge carrier lifetime killer in high-purity epitaxial layers of 4H-SÌC. The Vc concentration needs to be controlled and minimized for optimum materials and device performance, and an approach based on post-growth thermal processing under C-rich ambient conditions is presented. It utilizes thermodynamic equilibration and after heat treatment at 1500 °C for 1 h, the Vc concentration is shown to be reduced by a factor-25 relative to that in as-grown state-of-the-art epi-layers. Concurrently, a considerable enhancement of the carrier lifetime occurs throughout the whole of >40 urn thick epi-layers. 

The carbon vacancy (VC) is a minority carrier lifetime controlling defect in 4H-SiC and it is formed during high temperature treatment. In this study, we have performed heat treatment on two sets of n-type 4H-SiC epitaxial samples. The first set was isothermally treated at 1850 °C to follow the evolution of VC as a function of time. The VC concentration is not affected by changing the duration. Samples of the other set were treated at 1950 °C for 10 min, but with different cooling rates and a reduction of the VC concentration was indeed demonstrated by lowering the cooling rate. The VC concentration in the slow-cooled sample is about 2 times less than in the fast-cooled one, reflecting a competition between equilibrium conditions and the cooling rate.

The carbon vacancy (VC) is a major limiting-defect of minority carrier lifetime in n-type 4H-SiC epitaxial layers and it is readily formed during high temperature processing. In this study, a kinetics model is put forward to address the thermodynamic equilibration of VC, elucidating the possible atomistic mechanisms that control the VC equilibration under C-rich conditions. Frenkel pair generation, injection of carbon interstitials (Ci’s) from the C-rich surface, followed by recombination with VC’s, and diffusion of VC’s towards the surface appear to be the major mechanisms involved. The modelling results show a close agreement with experimental deep-level transient spectroscopy (DLTS) depth profiles of VC after annealing at different temperatures.

It is known that the behavior of residual Li in ion implanted ZnO depends on the preferential localization of the implants, in particular, forming characteristic Li depleted or Li pile-up regions for Zn or O sublattice occupation of the implants due to the corresponding excess generation of Zn and O interstitials in accordance with the so-called "+1 model." However, the present study reveals that conditions for the radiation damage annealing introduce additional complexity into the interpretation of the Li redistribution trends. Specifically, four implants residing predominantly in the Zn-sublattice, but exhibiting different lattice recovery routes, were considered. Analyzing Li redistribution trends in these samples, it is clearly shown that Li behavior depends on the defect annealing kinetics which is a strong function of the implanted fluence and ion species. Thus, Li depleted and Li pile-up regions (or even combinations of the two) were observed and correlated with the defect evolution in the samples. It is discussed how the observed Li redistribution trends can be used for better understanding a thermal evolution of point defects in ZnO and, in particular, energetics and migration properties of Zn interstitials.

Sequential 3D (S3D) integration has been identified as a potential candidate for area efficient ICs. It entails the sequential processing of tiers of devices, one on top the other. The sequential nature of this processing allows the inter-tier vias to be processed like any other inter-metal vias, resulting in an unprecedented increase in the density of vertical interconnects. A lot of scientific attention has been directed towards the processing aspects of this 3-D integration approach, and in particular producing high-performance top-tier transistors without damaging the bottom tier devices and interconnects.As far as the applications of S3D integration are concerned, a lot of focus has been placed on digital circuits. However, the advent of Internet-of-Things applications has motivated the investigation of other circuits as well.

As a first step, two S3D design platforms for custom ICs have been developed, one to facilitate the development of the in-house S3D process and the other to enable the exploration of S3D applications. Both contain device models and physical verification scripts. A novel parasitic extraction flow for S3D ICs has been also developed for the study of tier-to-tier parasitic coupling.

The potential of S3D RF/AMS circuits has been explored and identified using these design platforms. A frequency-based partition scheme has been proposed, with high frequency blocks placed in the top-tier and low-frequency ones in the bottom. As a proof of concept, a receiver front-end for the ZigBee standard has been designed and a 35% area reduction with no performance trade-offs has been demonstrated.

To highlight the prospects of S3D RF/AMS circuits, a study of S3D inductors has been carried out. Planar coils have been identified as the most optimal configuration for S3D inductors and ways to improve their quality factors have been explored. Furthermore, a set of guidelines has been proposed to allow the placement of bottom tier blocks under top-tier inductors towards very compact S3D integration. These guidelines take into consideration the operating frequencies and type of components placed in the bottom tier.

Lastly, the prospects of S3D heterogeneous integration for circuit design have been analyzed with the focus lying on a Ge-over-Si approach. Based on the results of this analysis, track-and-hold circuits and digital cells have been identified as potential circuits that could benefit the most from a Ge-over-Si S3D integration scheme, thanks to the low on-resistance of Ge transistors in the triode region. To improve the performance of top-tier Ge transistors, a processing flow that enables the control of their back-gates has been also proposed, which allows controlling the threshold voltage of top-tier transistors a truntime.

The placement of bottom tier blocks under top-tierinductors could significantly improve the area-efficiency of M3DRF/AMS circuits, paving the way for new applications of thisintegration technology. This work investigates the potential ofplacing digital blocks in the bottom tier, underneath top tierinductors. A design-technology co-optimization flow is appliedand a number of design guidelines are suggested. These guidelinesensure high electromagnetic isolation between the two tiers, withminimum penalties on the loading of bottom tier wires, as wellas on the inductor’s performance.

The influence on magnetic droplet nucleation boundaries by canted magnetic elds are investigated and reported. The nucleation boundary condition, I_n = αAH + BH + C, is determined at different canted angles (0°< θ_H<20°) using magnetoresistance (MR) and microwave measurements in nanocontact spintorque oscillators (NC-STOs). As θ_H increased, the nucleation boundary shifts gradually towards higher I_n and H. The coefficient B of the nucleation boundary equation also nearly doubled as θ_H increases. On theother hand, the coefficient αA remained constant for all values of θ_H. These observations can be explained by considering the drift instability of magnetic droplets and the different tilt behaviour of the Co fixed layer induced by different θH.

Significant research interest is being devoted to exploiting the properties of graphene but the difficult integration on various substrates limits its use. In this regard, we developed a transfer technique that allows the direct deposition of inkjet printed graphene devices on arbitrary substrates, even 3D objects and living plants. With this technique, we fabricated micro-supercapacitors, which exhibited good adhesion on almost all substrates and no performance degradation induced by the process. Specifically, the microsupercapacitor on an orchid leaf showed an areal capacitance as high as 441 mu F cm(-2) and a volumetric capacitance of 1.16 F cm(-3). This technique can boost the use of graphene in key technological applications, such as self powered epidermal electronics and environmental monitoring systems.

The smart grid is a new paradigm that aims to modernize the legacy power grid. It is based on the integration of ICT technologies, embedded system, sensors, renewable energy and advanced algorithms for management and optimization. The smart grid is a system of systems in which communication technology plays a vital role. Safe operations of the smart grid need a careful design of the communication protocols, cryptographic schemes, and computing technology. In this article, the authors describe current communication technologies, recently proposed algorithms, protocols, and architectures for securing smart grid communication network. They analyzed in a unifying approach the three principles pillars of smart-gird: Sensors, communication technologies, and security. Finally, the authors elaborate open issues in the smart-grid communication network.

This paper proposes hardware architecture for a fuel estimation algorithm suitable for SoC FPGA. The architecture utilizes 32-point single precision floating point representation. A resource constraint scheduling algorithm is elaborated to synthesize an area efficient architecture. The floating point arithmetic is implemented using commercial IP. Synthesis results for the Virtex-6 FPGA family reveal that the proposed architecture consumes 1655 slices, has a latency of 71 ns and consumes 0.15 µJ. Additionally, the present work describes a software implementation of the fuel estimation algorithm using Zynq-7000 SoC.

This work presents an algorithm to select a low-cost modulus for the implementation of Blum Blum Shub pseudorandom number generator in an FPGA device. Additionally, it elaborates a low-latency architecture for the BBS algorithm suitable for the security service of the IEEE 1609.2 standard. The architecture uses diminished-1 arithmetic and is log2($N$) faster than previously reported implementation using Montgomery multiplier. The architecture is able to implement 224-bit and 256-bit BBS sequences. Synthesis results show that the latencies for the 224-bit and 256-bit BBS are, respectively, 1.12μs and 1.28μs.

This article presents a word serial retimed architecture for the SHA-256/224 algorithm. The architecture is compliant with the dedicated-short range communication for safety message authentications. We elaborate three-operand adder architectures suitable for field programmable gate array implementation. Several transformation techniques at the data-flow-graph level have been used to derive the architecture. Synthesis results show that the architecture has high throughput/ slice value compared with state-of-the-art SHA-256 implementations. The article also promulgates a comparison between high-level synthesis and RTL design.

The iGrid project deals with the design and implementation of a solar-powered smart microgrid to supply electric power to small rural communities. In this paper, we discuss the roadmap of the iGrid project, which forms by merging the roadmaps of KIC (knowledge and Innovation Community) and CDE (Challenge-Driven Education). We introduce and explain a five-gear chain as Challenge, Education, Research, Innovation, and Deployment, called CERID, to reach the main goals of this project. We investigate the full chain in the iGrid project, which is established between KTH Royal Institute of Technology (Sweden) and University of Dar es Salam (Tanzania). We introduce the key stakeholders and explain how CERID goals can be accomplished in higher educations and through scientific research. Challenges are discussed, some innovative ideas are introduced and deployment solutions are recommended.

Control of defects at or near the MOS interface is paramount for device performance optimization. The SiC MOS system is known to exhibit two types of MOS defects,defects at the SiO₂/SiC interface and defects inside of the gate oxide that can trap channel charge carriers. Differentiating these two types can be challenging. In this work, we use several electrical measurement techniques to extract and separate these two types of defects. The charge pumping method and the ultrafast pulsed I-V method are given focus, as they are independent methods for extracting the defects inside the gate oxide. Defects are extracted from low voltage n-channel MOSFETs with differently processed gate oxides: steam-treatment, dry oxidation and nitridation. Ultrafast pulsed I-V and charge pumping gives comparable results. The presented analysis of the electrical characterization methods is of use for SiC MOSFET process development.

Graphene is an atomically thin material that features unique electrical and mechanical properties, which makes it an extremely promising material for future nanoelectromechanical systems (NEMS). Recently, basic NEMS accelerometer functionality has been demonstrated by utilizing piezoresistive graphene ribbons with suspended silicon proof masses. However, the proposed graphene ribbons have limitations regarding mechanical robustness, manufacturing yield, and the maximum measurement current that can be applied across the ribbons. Here, we report on suspended graphene membranes that are fully clamped at their circumference and have attached silicon proof masses. We demonstrate their utility as piezoresistive NEMS accelerometers, and they are found to be more robust, have longer life span and higher manufacturing yield, can withstand higher measurement currents, and are able to suspend larger silicon proof masses, as compared to the previous graphene ribbon devices. These findings are an important step toward bringing ultraminiaturized piezoresistive graphene NEMS closer toward deployment in emerging applications such as in wearable electronics, biomedical implants, and internet of things (IoT) devices.

Nanoelectromechanical system (NEMS) sensors and actuators could be of use in the development of next-generation mobile, wearable and implantable devices. However, these NEMS devices require transducers that are ultra-small, sensitive and can be fabricated at low cost. Here, we show that suspended double-layer graphene ribbons with attached silicon proof masses can be used as combined spring–mass and piezoresistive transducers. The transducers, which are created using processes that are compatible with large-scale semiconductor manufacturing technologies, can yield NEMS accelerometers that occupy at least two orders of magnitude smaller die area than conventional state-of-the-art silicon accelerometers. With our devices, we also extract the Young’s modulus values of double-layer graphene and show that the graphene ribbons have significant built-in stresses.

Graphene's unparalleled strength, chemical stability, ultimate surface-to-volume ratio and excellent electronic properties make it an ideal candidate as a material for membranes in micro- and nanoelectromechanical systems (MEMS and NEMS). However, the integration of graphene into MEMS or NEMS devices and suspended structures such as proof masses on graphene membranes raises several technological challenges, including collapse and rupture of the graphene. We have developed a robust route for realizing membranes made of double-layer CVD graphene and suspending large silicon proof masses on membranes with high yields. We have demonstrated the manufacture of square graphene membranes with side lengths from 7 mu m to 110 mu m, and suspended proof masses consisting of solid silicon cubes that are from 5 mu mx5 mu mx16.4 mu m to 100 mu mx100 mu mx16.4 mu m in size. Our approach is compatible with wafer-scale MEMS and semiconductor manufacturing technologies, and the manufacturing yields of the graphene membranes with suspended proof masses were >90%, with >70% of the graphene membranes having >90% graphene area without visible defects. The measured resonance frequencies of the realized structures ranged from tens to hundreds of kHz, with quality factors ranging from 63 to 148. The graphene membranes with suspended proof masses were extremely robust, and were able to withstand indentation forces from an atomic force microscope (AFM) tip of up to 7000nN. The proposed approach for the reliable and large-scale manufacture of graphene membranes with suspended proof masses will enable the development and study of innovative NEMS devices with new functionalities and improved performances.

Kernel correlation filters (KCF) demonstrate significant potential in visual object tracking by employing robust descriptors. Proper selection of color and texture features can provide robustness against appearance variations. However, the use of multiple descriptors would lead to a considerable feature dimension. In this paper, we propose a novel low-rank descriptor, that provides better precision and success rate in comparison to state-of-the-art trackers. We accomplished this by concatenating the magnitude component of the Overlapped Multi-oriented Tri-scale Local Binary Pattern (OMTLBP), Robustness-Driven Hybrid Descriptor (RDHD), Histogram of Oriented Gradients (HoG), and Color Naming (CN) features. We reduced the rank of our proposed multi-channel feature to diminish the computational complexity. We formulated the Support Vector Machine (SVM) model by utilizing the circulant matrix of our proposed feature vector in the kernel correlation filter. The use of discrete Fourier transform in the iterative learning of SVM reduced the computational complexity of our proposed visual tracking algorithm. Extensive experimental results on Visual Tracker Benchmark dataset show better accuracy in comparison to other state-of-the-art trackers.

This paper ideates a novel texture descriptor that retains its classification accuracy under varying conditions of image orientation, scale, and illumination. The proposed Overlapped Multi-oriented Tri-scale Local Binary Pattern (OMTLBP) texture descriptor also remains insensitive to additive white Gaussian noise. The wavelet decomposition stage of the OMTLBP provides robustness to photometric variations, while the two subsequent stages - overlapped multi-oriented fusion and multi-scale fusion - provide resilience against geometric transformations within an image. Isolated encoding of constituent pixels along each scale in the joint histogram enables the proposed descriptor to capture both micro and macro structures within the texture. Performance of the OMTLBP is evaluated by classifying a variety of textured images belonging to Outex, KTH-TIPS, Brodatz, CUReT, and UIUC datasets. The experimental results validate the superiority of the proposed method in terms of classification accuracy when compared with the state-of-the-art texture descriptors for noisy images.

Objective: Electrical impedance myography (EIM) measures bioimpedance over muscles. This paper proposes a circuit-based modelling methodology originated from finite element analysis (FEA), to emulate tissues and effects from anthropometric variations, and electrode placements, on EIM measurements. The proposed methodology is demonstrated on the upper arms and lower legs. Methods: FEA evaluates impedance spectra (Z-parameters), sensitivity, and volume impedance density for variations of subcutaneous fat thickness (tf), muscle thickness (tm), and inter-electrode distance (IED), on limb models over 1Hz-1MHz frequency range. The limbs models are based on simplified anatomical data and dielectric properties from published sources. Contributions of tissues to the total impedance are computed from impedance sensitivity and density. FEA Z-parameters are imported into a circuit design environment, and used to develop a three Cole dispersion circuit-based model. FEA and circuit model simulation results are compared with measurements on ten human subjects. Results: Muscle contributions are maximized at 31.25kHz and 62.5kHz for the upper arm and lower leg, respectively, at 4cm IED. The circuit model emulates variations in tf and tm, and simulates up to 89 times faster than FEA. The circuit model matches subjects measurements with RMS errors < 36.43 and < 17.28, while FEA does with < 36.59 and < 4.36. Conclusions: We demonstrate that FEA is able to estimate the optimal frequencies and electrode placements, and circuit-based modelling can accurately emulate the limbs bioimpedance. Significance: The proposed methodology facilitates studying the impact of biophysical principles on EIM, enabling the development of future EIM acquisition systems.

This paper presents a low-distortion current-mode sinusoidal signal generator for bioimpedance spectroscopy measurements. The proposed full current-mode operation enables linearity enhancement and potential savings in silicon area and power consumption. Programmability in the low-pass filter and current driver enables impedance measurements from 0.2 Ω to10 kΩ over a wide frequency range from 1 kHz to 1 MHz.The current generator, designed in a 0.18 μm CMOS process, consumes between 736 μW at the lowest frequency and gain, and 1.70 mW at the highest frequency and gain, and occupies 1.76 mm² silicon area. Post-layout simulation results show a spurious-free dynamic range larger than 40 dBc over the entire frequency range, which enables bioimpedance measurements with errors below 1%, as it is required for wearable devices evaluating neuromuscular disorders.

Measurements in the atmosphere and at the surface of Venus are required to understand fundamental processes of how terrestrial planets evolve and how they work today. While the European Venus community is unified in its support of the EnVision orbiter proposal as the next step in European Venus exploration, many scientific questions also require in situ Venus exploration. We suggest a long-duration lander at Venus, which would be capable of undertaking a seismometry mission, operating in the 460°C surface conditions of Venus. Radar maps have shown Venus to be covered with volcanic and tectonic features, and mounting evidence, including observations from Venus Express, suggests that some of these volcanoes are active today. Assessing Venus' current seismicity, and measuring its interior structure, is essential if we are to establish the geological history of our twin planet, for example to establish whether it ever had a habitable phase with liquid water oceans. Although some constraints on seismic activity can be obtained from orbit, using radar or ionospheric observation, the most productive way to study planetary interiors is through seismometry. Seismometry requires a mission duration of months or (preferably) years. Previous landers have used passive cooling, relying on thermal insulation and the lander's thermal inertia to provide a brief window of time in which to conduct science operations - but this allows mission durations of hours, not months. Proposals relying on silicon electronics require an electronics enclosure cooled to < 200 °C; the insulation, cooling and power system requirements escalate rapidly to require a > 1 ton, > €1bn class mission, such as those studied in the context of NASA flagship missions. However, there are alternatives to silicon electronics: in particular, there have been promising advances in silicon carbide (SiC) electronics capable of operating at temperatures of 500°C. Within the coming decade it will be possible to assemble at least simple circuits using SiC components, sufficient to run a seismometry lander. We are proposing a Venus Long-Lived Surface Package (VL2SP) consisting of power source (RTG), science payload (seismometer and meteorology sensors), and ambient temperature electronics including a telecommunications system weighing < 100 kg. We do not specify how this VL2SP gets to the surface of Venus, but we estimate that an orbiter providing data relay would be essential. This presentation is based on a response sumitted to ESA's Call for New Scientific Ideas in September 2016. 

Venus is our closest planet, but we know much less about it than about Mars. The main reason for this is the extreme conditions, with a dense atmosphere of mainly CO2 at 92 bar atmosphere and 460 °C temperature at the surface. Only six spacecraft have succeeded to land on Venus and transmit data back to Earth; however none survived for long due to the high temperature. Venera-13 has the record, with 127 minutes at the surface of Venus in 1982. There are many compelling reasons to learn more about the sister planet of Earth, which requires measurements over months rather than minutes on the surface of Venus. Perhaps the single-most challenging task for long-term data taking on the surface of Venus is to build electronics that can operate at temperatures up to 500 °C without cooling. It seems that such technology must be based on wide bandgap semiconductors, such as GaN, SiC or diamond. At KTH, research with SiC devices and integrated circuits has been done for more than 20 years, demonstrating high voltage devices and digital integrated circuit operation at 600 °C. In 2014 the project Working On Venus launched, with funding from Knut and Alice Wallenberg Foundation. The goal is to demonstrate all the electronics for a complete working lander, with all electronics from sensors through amplifiers and analog-to-digital converters to microcontroller with memory and radio, including power supply. The particular sensors the project has in mind are seismic, gas and image sensors. So far, a 200 device level integration has been demonstrated at 500 °C and a 5000+ device level 4 bit microcontroller is being fabricated in an in-house bipolar technology. As for all devices for space, radiation is another concern. SiC integrated circuits have survived exposure to 3 MeV protons with fluences of 1013 cm-2 and gamma rays with doses of 332 Mrad. The dedicated project SUPERHARD IC will study manufacture methods for radiation hardened instrument components that could go beyond Venus, for example for Jovian system exploration. Members of Working on Venus are discussing with scientists seeking opportunities for a Venus Long-Life Surface Package (lander). In 2016 a response was submitted to ESA's Call for New Scientific Ideas. 

Efficiency of Network-on-Chip based many-core microprocessors to implement parallel fault simulation methods for different circuit sizes is explored in this paper. We show that a naive and straightforward execution of fault simulation programs on such systems does not provide the maximum speedup due to severe bottlenecks in off-chip shared memory access at memory controllers. In order to exploit the available massive parallelism of homogenous many-core microprocessors, a runtime approach capable of adaptively balancing the load during the fault simulation process is proposed. We demonstrate the proposed adaptive fault simulation approach on a many-core platfonn, Intels Single-chip Cloud Computer showing up to 45X speedup compared to a serial fault simulation approach.

The radiation hardness of two dielectrics, SiO2 and Al2O3, deposited on low doped, ntype 4H-SiC epitaxial layers has been investigated by exposing MOS structures involving these materials to MeV proton irradiation. The samples are examined by capacitance voltage (CV) measurements and, from the flat band voltage shift, it is concluded that positive charge is induced in the exposed structures detectable for fluence above 1×1011 cm-2. The positive charge increases with proton fluence, but the SiO2/4H-SiC structures are slightly more sensitive, showing that Al2O3 can provide a more radiation hard passivation, or gate dielectric for 4H-SiC devices.

While the effectiveness of fog computing in Internet of Things (IoT) applications has been widely investigated in various studies, there is still a lack of techniques to efficiently utilize the computing resources in a fog platform to maximize Quality of Service (QoS) and Quality of Experience (QoE). This paper presents a resource management model for service placement of distributed multitasking applications in fog computing through mathematical modeling of such a platform. Our main design goal is to reduce communication between the candidate nodes hosting different task modules of an application by selecting a group of nodes near each other and as close to the source of the data as possible. We propose a method based on a greedy principle that demonstrates a highly scalable and near-optimal performance for resource mapping problems for multitasking applications in fog computing networks. Compared with the commercial Gurobi optimizer, our proposed algorithm provides a mapping solution that obtains 93% of the performance, attributed to a higher communication cost, while outperforming the reference method in terms of the computing speed, cutting the mapping execution time to less than 1% of that of the Gurobi optimizer.

This paper presents our in-house fabricated 4H-SiC n-p-n phototransistors. The wafer mapping of the phototransistor on two wafers shows a mean maximum forward current gain (βFmax) of 100 at 25 ºC. The phototransistor with the highest βFmax of 113 has been characterized from room temperature to 500 ºC. The βFmax drops to 51 at 400 ºC and remains the same at 500 ºC. The photo current gain of the phototransistor is 3.9 at 25 ºC and increases to 14 at 500 ºC under the 365 nm UV light with the optical power of 0.31 mW. The processing of the phototransistor is same to our 4HSiC-based bipolar integrated circuits, so it is a promising candidate for 4H-SiC opto-electronics onchip integration.

An image sensor based on wide band gap silicon carbide (SiC) has the merits of high temperature operation and ultraviolet (UV) detection. To realize a SiC-based image sensor the challenge of opto-electronic on-chip integration of SiC photodetectors and digital electronic circuits must be addressed. Here, we demonstrate a novel SiC image sensor based on our in-house bipolar technology. The sensing part has 256 ( $16\times 16$ ) pixels. The digital circuit part for row and column selection contains two 4-to-16 decoders and one 8-bit counter. The digital circuits are designed in transistor-transistor logic (TTL). The entire circuit has 1959 transistors. It is the first demonstration of SiC opto-electronic on-chip integration. The function of the image sensor up to 400 degrees C has been verified by taking photos of the spatial patterns masked from UV light. The image sensor would play a significant role in UV photography, which has important applications in astronomy, clinics, combustion detection and art.

It remains a challenge to run Deep Learning in devices with stringent power budget in the Internet-of-Things. This paper presents a low-power accelerator for processing Convolutional Neural Networks on the embedded devices. The power reduction is realized by exploring data reuse in three different aspects, with regards to convolution, filter and input features. A systolic-like data flow is proposed and applied to rows of Processing Elements (PEs), which facilitate reusing the data during convolution. Reuse of input features and filters is achieved by arranging the PE array in a 3D tiled architecture, whose dimension is 3 x 14 x 4. Local storage within PEs is therefore reduced and only cost 17.75 kB, which is 20% of the state-of-the-art. With dedicated delay chains in each PE, this accelerator is reconfigurable to suit various parameter settings of convolutional layers. Evaluated in UMC 65 nm low leakage process, the accelerator can reach a peak performance of 84 GOPS and consume only 136 mW at 250 Mhz.

Fast aging of components has become one of the major concerns in Systems-on-Chip with further scaling of the submicron technology. This problem accelerates when combined with improper working conditions such as unbalanced components' utilization. Considering the mapping algorithms in the Networks-on-Chip domain, some routers/links might be frequently selected for mapping while others are underutilized. Consequently, the highly utilized components may age faster than others which results in disconnecting the related cores from the network. To address this issue, we propose a mapping algorithm, called lifetime-aware neighborhood allocation (LaNA), that takes the aging of components into account when mapping applications. The proposed method is able to balance the wear-out of NoC components, and thus extending the service time of NoC. We model the lifetime as a resource consumed over time and accordingly define the lifetime budget metric. LaNA selects a suitable node for mapping which has the maximum lifetime budget. Experimental results show that the lifetime-aware mapping algorithm could improve the minimal MTTF of NoC around 72.2%, 58.3%, 46.6% and 48.2% as compared to NN, CoNA, WeNA and CASqA, respectively.

Chopper amplifiers for biopotential acquisition commonly suppress differential electrode DC offsets by using a DC-servo loop (DSL). However, the noise contribution of the DSL is always neglected in noise analysis. The noise introduced by the DSL, in particular at low frequencies, is of great importance in biosensor applications. This work presents the noise modeling of a current-balancing chopper amplifier with DSL and describes the effect of the DSL on the noise performance. Two different DSL implementations are analyzed. It is found that the exact placement of the chopper in the DSL has a strong impact in the noise performance; therefore, its placement can not be arbitrarily selected. A circuit topology to minimize its noise contribution is then proposed and verified by simulation.